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Micro/Nano Lithography

Tatsuhiko Higashiki: Applying NIL for device fabrication and challenges in nano-defect management

Presented at SPIE Advanced Lithography 2017.

14 March 2017, SPIE Newsroom. DOI: 10.1117/2.3201703.14

Cost reduction is a critical factor for the fabrication of high performance memory devices and will continue to be a focus for future generations of devices. However, investment costs in pattern shrinking technologies, such as multi-patterning and EUVL have become enormous, and encompass additional etch and deposition systems as well as the infrastructure equipment necessary to support these technologies.

The framework surrounding these pattern shrinking technologies has not been able to provide lower-cost semiconductor devices. Therefore, in order to significantly reduce investment cost in lithography, nanoimprint lithography (NIL) technology has aggressively been developed

In this keynote address, Tatsuhiko Higashiki of Toshiba Corp., discusses nanoimprint lithography applications to semiconductor devices, and progress in nanoimprint related technology, including updates of NIL performances and NDM challenges.

Higashiki also discusses nanoimprint lithography for high volume manufacturing along with key challenges that must be addressed and the role of EIDEC in identifying these challenges and developing NDM solutions.

Tatsuhiko Higashiki is a senior fellow at Toshiba Corp. where he is the supervisor for advanced mask and lithography technology. His current research interests are advanced lithography and mask technologies such as multi patterning, EUVL, Nano imprint, DSA (directed self-assembly), and nano-defect-management.