Aggressive scaling of transistor dimensions and increasing chip complexity have satisfied the demand for increased performance of integrated circuits for many decades. In these ways, the supply voltage and capacitance of the devices can be reduced by scaling down the device dimensions. Small geometry effects, however, play a major role in the degradation of integrated circuit performance levels. These effects cause an increase in the leakage current, and consequently the static power dissipation.1 The power dissipation and corresponding die temperature of integrated circuits have therefore continuously increased. It is known, however, that the scaling limit of silicon (dictated by Moore's law) will soon be reached.2 As part of an effort to find a suitable substitute for silicon in integrated circuits, a large group of emerging materials is now being extensively studied.
Graphene has an atomically thin planar structure, a high carrier concentration, high carrier mobility, and good thermal conductivity.3 These characteristics thus allow for more aggressive supply voltage scaling (along with simultaneously higher drive current) with graphene than with silicon metal-oxide semiconductor (MOS) field-effect transistors (FETs). In addition, a graphene nanoribbon (GNR)—narrow stripes of graphene—is a promising alternative channel material in MOS-type structures. The atomistic calculated thickness of a GNR also provides the maximum possible surface-to-bulk ratio, which enables the design of high-performance temperature sensors.4–7
An all-graphene architecture, in which all the transistors and interconnects can be fabricated from concurrent patterning of a graphene sheet, has recently been proposed.8 Since all the components in this architecture must be made from graphene, we have explored the feasibility of using a thin oxide GNR array as a high-performance temperature sensor for the detection of local on-chip temperatures at the nanometer scale. Our proposed nanoscale temperature sensor (see Figure 1) consists of multiple armchair-shaped GNRs (used as the sensing material) and a highly doped silicon substrate (for the back-gate contact). The high power density at the nanometer scale causes generation of local heat that can be transported through the top area of our sensor, or through the substrate beneath the graphene sheet. The high electrical and thermal conductivity of our miniaturized temperature sensor means that it has high sensitivity, low power consumption, and a fast response time.3
Figure 1. Schematic diagram of the back-gate multi-channel graphene nanoribbon (GNR) field-effect transistor (FET) temperature sensor device. A vertical cross section of the device is shown in (a) and a 3D view in (b). LG, WG: Graphene length and width, respectively. Wsp: Spacing width. WGNR: GNR width.
In this work,7 we have developed a physical analytical model for our GNR-based temperature sensor. Our model can also be used for the circuit implementation of a multi-channel GNR FET, as shown in Figure 2(a) and (b). We modeled the carrier transport in each independent ribbon as the two-current source associated with the thermionic emission of the carriers and the band-to-band tunneling of the carriers from the drain to channel regions. In our method, four capacitors are used to model the electrostatic coupling of the channel to the potentials at the electrodes. In addition, a voltage-controlled voltage source is used to account for the charging and discharging of the carriers in the GNR. Our model also incorporates different scattering mechanisms in graphene, including the intrinsic acoustic phonons, intrinsic optical phonons, interaction of carriers with optical phonons of the substrate, and line-edge roughness in narrow GNRs. The heat imparted to the graphene surface causes an increase in the scattering rate (from carrier collisions) and thereby modulates the conductance of the GNRs. This can be measured by correlating the temperature to the variation in its resistance.
Figure 2. (a) Circuit implementation of the multi-channel GNR FET temperature sensor. CGD and CGS: Gate-drain and gate-source capacitance, respectively. (b) Energy band diagram and the equivalent circuit model of the device. VS, VD, VG, and VB: Source, drain, gate, and bulk voltages. VCH: Voltage-controlled voltage source. IT and IBTBT: Thermionic and band-to-band tunneling currents. CG, CH, CD, CH, CS, CH, and CB, CH: Gate-channel, drain-channel, source-channel, and bulk-channel capacitances. EFS and EFD: Fermi level in the source and drain regions. Ec: Conduction band. Ev: Valence band. (c) Dispersion relation of GNR (WGNR of 0.75nm) expressed on an energy-momentum (E-k) diagram.
We have investigated the temperature sensitivity of our device for various back-gate biases and GNR widths. The former modulates the carrier population in the upper sub-bands of GNRs, and the latter alters the bandgap of GNRs because of the change in quantum confinement of the carriers, as illustrated in Figure 2(c). We thus calculated the temperature coefficient of resistance (TCR) of our proposed GNR FET-based temperature sensor as , where ΔT and ΔR are the change in temperature and resistance, respectively, and R0 is the resistance at room temperature.
The results of our TCR variation measurements (conducted at room temperature, 300K) are shown in Figure 3. We find that the maximum TCR depends on the GNR width and the gate bias. For instance, when the gate bias (VGS) is 0.3V, the maximum TCR is 6 × 10−3K−1 at 450K: see Figure 3(a). The maximum TCR increases, however, to 8.5 × 10−3K−1 at 350K for a VGS of 0.4V applied on a wider GNR (about 11nm): see Figure 3(b). By increasing the gate bias to 0.5V—see Figure 3(c)—we can achieve a maximum TCR of 2.1 × 10−2K−1 at room temperature for this wider GNR. However, for a VGS of 0.55V—see Figure 3(d)—the same maximum TCR occurs at room temperature for all the GNRs, such that the TCR is almost independent of GNR width.
Figure 3. Temperature coefficient of resistance (TCR) measurements, illustrating the dependence on WGNR and gate bias (VGS). N: GNR index number.
In summary, we have demonstrated a new graphene-nanoribbon-based temperature sensor that can be used for the circuit implementation of a multi-channel GNR FET. Our temperature coefficient of resistance computation reveals that the best gate bias voltage for our proposed sensor is 0.55V. With this bias, the TCR is at a maximum (2.1 ×10−2K−1) at room temperature and is independent of GNR width. Our device is thus suitable for embedding into an integrated circuit chip for the monitoring of hot spots. Our future work will be focused on the experimental design, fabrication, and testing of the GNR FET temperature sensor. We also aim to develop the technology for integration with CMOS and thus achieve sensing of hot spots across a chip that are caused by larger power dissipation.
Yaser M. Banadaki
Southern University and Louisiana State University (LSU)
Baton Rouge, LA
Yaser Banadaki is currently a PhD student in electrical engineering at LSU and an assistant professor at Southern University.
Ashok Srivastava, Safura Sharifi
Baton Rouge, LA
Ashok Srivastava is the Wilbur D. and Camille V. Fugler, Jr. Professor of electrical and computer engineering.
Safura Sharifi is a student in the master of natural science program.
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