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Micro/Nano Lithography

Implications of industry template adoption at 10 and 7nm

A novel technique for optimally determining a limited set of layout patterns called templates accounts for circuit needs and navigates sources of process variability with no power, performance, or area penalty.
19 November 2015, SPIE Newsroom. DOI: 10.1117/2.1201510.005846

At the 10nm node (i.e., next-generation chip technology) all major foundry platforms will be template-based. Quantized legal layout shapes and locations within predefined cell images are replacing free-form rules-based layouts to maximize pitch (feature size) scaling. The relative success of each technology platform will depend on the timely ability of each foundry to support the process requirements embedded in their formulation. But behind the headline-grabbing lithography choices and scaling targets, the economic battle at 10nm will be determined by the capabilities of each fabless (i.e., outsourcing designer) and foundry to exploit the disruptive opportunities available with templates. Fabless and foundries will be faced with ‘business as usual’ versus template co-optimization choices in design for manufacturability (DFM), silicon characterization, modeling, product and process ramp and debug, process control, and product testing. Fabless and foundries will thus need to adapt, migrate, and adopt the tools and approaches needed to take advantage of these opportunities.

Purchase SPIE Field Guide to Optical LithographyOver the past decade there has been relatively little change in industry flows to address these issues. This was largely the result of the growing complexity of layout patterns and design rules, which forced manufacturers into silos as a defense against patterning challenges. But the history of our industry, and the electronics industry more broadly, has shown that the principle of ‘conservation of modularity’ always reigns. When one slice of the design or manufacturing stack becomes more modular, adjacent portions of the stack capitalize on this modularity to drive co-optimization. For the first time in many nodes, we are entering this phase of heightened modularity in layout patterns. This will feed disruptive innovation in template co-optimization.

Templates and DFM are not synonymous. Selecting the optimal limited set of layout patterns to be used in a given template is the new essence of DFM. These layout patterns must take into account circuit needs and anticipate sources of process variability. Process variability must be characterized in silicon to identify the layout patterns with sufficient process margin (i.e., error tolerance). This in turn will create demand for advances in silicon characterization capabilities.

Moreover, device scaling and the application of stressors—such as epitaxially grown silicon germanium source/drain regions in PMOS transistors or dual-stress-line NMOS transistors (where PMOS and NMOS refer to positive- and negative-channel metal oxide semiconductors)—in modern device architectures will require exhaustive silicon characterization of transistor behavior. Device modeling will need to shift its focus to characterization of a specific limited set of transistor layout patterns and neighborhoods, rather than (as previously) general-purpose models that span a broad rule space. Evidence gained from silicon results in the technology scaling from 32nm to 14nm reveals the process margin and parametric benefits that template adopters experienced in conjunction with advanced silicon characterization. As an example of the benefits of templates, Figure 1 shows the transistor leakage (a measure of static power dissipation) in the tail of the distribution as measured in standard cells.

Figure 1. Transistor leakage is measured in standard cells. This is a key parameter that determines the integrated circuit product static power dissipation.

Perhaps the greatest opportunity provided by templates at 10 and 7nm is the ability to capture all layout patterns that will be present in products, before any products are designed. If executed properly, this will enable fabless and foundries to eliminate the months or, in some cases, years of physical debug efforts that have plagued lead product ramps at advanced nodes.

While lithographic patterning has extended pitch scaling by employing multipatterning and sidewall image transfer procedures, the resolution limitations of defect inspection have not enjoyed similar advances. Electron-beam (e-beam) inspection has overcome the resolution limitations of bright-field inspection at the cost of throughput. The resulting decrease in sampling coverage has relegated current e-beam inspection to limited applications. Importantly, neither of these types of inspection tools is capable of catching the subsurface defects that are the critical yield limiter in FinFET (double-gate device) processes. The small finite set of layout patterns in templates introduces the ability to optimize inspection pattern sampling, take advantage of otherwise unused white space on product wafers, and improve throughput by five orders of magnitude or more. All of this can be achieved while observing defects that were previously unobservable with pre-existing inspection methods.

In summary, we have shown1 that the tools and technology required to capitalize on the opportunities offered by templates are already available. We have reviewed the results achieved in each of the relevant domains, as well as the key factors that will determine the ability of fabless and foundries to leverage these applications. Similar applications will become available to tune physical fault models in product test generation. In a limited pattern world, product testing should be able to adapt to the specific process conditions that were recorded for each reticle shot. This will enable product testing to improve test escapes without degrading test time or test cost. This is crucial for product economics at advanced nodes where the cost of product testing may be as high as 25% of the total product wafer cost.

Andrzej J. Strojwas
PDF Solutions Inc.
San Jose, CA

Andrzej J. Strojwas is Joseph F. and Nancy Keithley Professor of Electrical and Computer Engineering at Carnegie Mellon University. Since 1997 he has served as chief technologist at PDF Solutions Inc. In 1990 he was elected IEEE Fellow.

1. A. J. Strojwas, Layout optimization for the upcoming 10nm and 7nm printability scenarios. Presented at SPIE Advanced Lithography 2015.