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Micro/Nano Lithography

Ultra-low-k material cryoetching plasma process for interconnects

Cryoetching that minimizes plasma-induced carbon depletion was successfully tested on advanced low-k materials used in back-end-of-the-line CMOS technology.
7 July 2015, SPIE Newsroom. DOI: 10.1117/2.1201506.005770

Ultra-low-k (ULK) dielectrics are a class of insulating materials that act to minimize capacitance in microelectronic circuits. ULKs are distinguished from ordinary low-k dielectrics by their porosity. In particular, porous organosilicate glasses (OSGs) such as SiOCH (carbon-doped silicon oxide) are now commonly used for interconnects in nanoelectronics to lessen the RC delay time (the product of the resistance of the metal lines and their interline capacitance) of CMOS devices.1, 2 Nanopores and methyl groups are introduced in the material by plasma-enhanced chemical vapor deposition or by spin coating to reduce the polarizability of the material, as measured by its low dielectric constant. Although these OSGs are in principle very suitable in terms of the dielectric constant value, they can be severely damaged during the subsequent plasma processes required to pattern the substrate or clean its surface.

Purchase SPIE Field Guide to Optical LithographyUsually, fluorocarbon-based plasma gas chemistry is used to etch the ULK material because it enables high selectivity of the hard mask (in other words, the etch rate of the mask is low compared with the etch rate of the ULK).3 However, radical species may diffuse through the pore channels of such plasmas and degrade the underlying material.4This problem can be mitigated, for instance, by a technique known as post-porosity plasma protection (P4) using sacrificial polymers,5 which reduce penetration of active radicals and vacuum-UV light into the film. This P4 technique is efficient but still poses a few challenges, such as its impact on several steps of the patterning, metallization, and possible deformation of ULK film during the process. Here, we propose a cryogenic etching process for patterning ULK material without significantly altering it.

Cryoetching of silicon was first introduced by a Japanese team in the late 1980s.6 Standard cryoetching of silicon basically relies on a SF6/O2 (sulfur hexafluoride/oxygen) plasma interacting with a silicon wafer cooled down to a low temperature of typically –100°C. At this very low temperature, a SiOxFy(fluorinated silicon oxide) passivation layer forms on the silicon sidewalls, obviating lateral etching.7, 8 Cryoetching processes are usually used for deep silicon etching of micrometer-scale patterns. Very high-aspect-ratio silicon microstructures can be created using a wide variety of mask materials. Recent reports have shown that cryoetching can also be used successfully to etch nanoscale features.9, 10 We recently proposed use of cryoetching to etch OSGs.11

The goal of our work on porous OSG cryoetching is to minimize plasma-induced carbon depletion. We introduced the concept of ‘equivalent damaged layer’ (EDL) determined by ellipsometry and Fourier transform IR spectroscopy experiments to evaluate the damage caused by the plasma. We also measured the change in dielectric constant after plasma exposure.

We performed etching experiments with SF6 plasmas on patterned and blanket wafers. Figure 1 shows a histogram representing the pristine and EDL thicknesses versus chuck (i.e., the mechanical substrate holder) temperature after a 30s plasma treatment. The initial thickness of the ULK material was 265nm. Note the marked decrease in the EDL as a result of low temperature. In porous OSG ULK materials, pores can be filled with the introduced chemicals and/or etch by-products so that plasma-induced damage is significantly reduced. Although the passivation layer evaporates at ambient temperature, some condensate by-products (carboxylic acids) remain stable at room temperature. However, this condensate can easily be removed by high-temperature annealing without additional damage to the ULK materials.

Figure 1. Pristine material and equivalent damaged layer thicknesses versus chuck temperature after a SF6(sulfur hexafluoride) plasma etching process. EDL: Equivalent damaged layer.

Cryoetching of ULK material used in back-end-of-the-line technology in integrated circuit fabrication is a promising technique for reducing the plasma-induced damage typical of more conventional plasma etching processes. We have shown that the equivalent damaged layer was significantly decreased by SF6 plasma simply by decreasing the substrate temperature down to –120°C. As a next step, we plan to investigate other gases in cryoetching, such as fluorocarbon-based gases, to further reduce the diffusion of fluorine species inside the ULK material and completely eliminate plasma-induced damage.

Remi Dussart, Thomas Tillocher, Floriane Leroy, Philippe Lefaucheux
GREMI CNRS – Université d'Orléans
Orléans, France
Koichi Yatsuda and Eiishi Nishimura
Tokyo Electron
Tokyo, Japan
Kaoru Maekawa
Tokyo Electron
Albany, NY
Liping Zhang, Jean-François de Marneffe, Mikhail Baklanov
Leuwen, Belgium

1. K. Maex, M. R. Baklanov, D. Shamiryan, F. Iacopi, S. H. Brongersma, Z. S. Yanovitskaya, Low dielectric constant materials for microelectronics, J. Appl. Phys. 93, p. 8793, 2003.
2. M. Darnon, N. Casiez, T. Chevolleau, G. Dubois, W. Volksen, T. J. Frot, R. Hurand, et al., Impact of low-k structure and porosity on etch processes, J. Vac. Sci. Technol. B 31, p. 011207, 2013.
3. G. Dubois, W. Volksen, Low-k materials: recent advances,in M. R. Baklanov, P. S. Ho, and E. Zschech (eds.), Advanced Interconnects for ULSI Technology, ch. 1, Wiley, 2012.
4. N. Posseme, T. Chevolleau, O. Joubert, L. Vallier, N. Rochat, Etching of porous SiOCH materials in fluorocarbon-based plasmas, J. Vac. Sci. Technol. B 22, p. 2772, 2004.
5. T. Frot, W. Volksen, S. Purushothaman, R. Bruce, G. Dubois, Application of the protection/deprotection strategy to the science of porous materials, Adv. Mater. 23, p. 2828-2832, 2011.
6. S. Tachi, K. Tsujimoto, S. Okudaira, Low-temperature reactive ion etching and microwave plasma etching of silicon, Appl. Phys. Lett. 52, p. 616, 1988.
7. X. Mellhaoui, R. Dussart, T. Tillocher, P. Lefaucheux, P. Ranson, M. Boufnichel, L. J. Overzet, SiOxFy passivation layer in silicon cryoetching, J. Appl. Phys 98, p. 104901, 2005.
8. R. Dussart, T. Tillocher, P. Lefaucheux, M. Boufnichel, Plasma cryogenic etching of silicon: from the early days to today's advanced technologies, J. Phys. D: Appl. Phys. 47, p. 123001, 2014.
9. X. Gu, Z. Liu, I. Gunkel, S. T. Chourou, S. W. Hong, D. L. Olynick, T. P. Russell, High aspect ratio sub-15 nm silicon trenches from block copolymer templates, Adv. Mater. 24, p. 5688, 2012.
10. Z. Liu, Y. Wu, B. Harteneck, D. Olynick, Super-selective cryogenic etching for sub-10 nm features, Nanotechnology 24, p. 015305, 2013.
11. L. Zhang, R. Ljazouli, P. Lefaucheux, T. Tillocher, R. Dussart, Y. A. Mankelevich, J.-F. de Marneffe, S. de Gendt, M. R. Baklanov, Low damage cryogenic etching of porous organosilicate low-k materials using SF6/O2/SiF4, ECS J. Solid State Sci. Technol. 2, p. N131, 2013.