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Micro/Nano Lithography

Lithography continues to drive Moore's law

The semiconductor industry relies on perpetual miniaturization, and for this to continue requires a holistic approach to the entire lithography process and a move to extreme UV lithography.
19 December 2014, SPIE Newsroom. DOI: 10.1117/2.1201412.005602

The semiconductor industry takes its impulse from Moore's law, an observation made by Gordon Moore in 1965 that the number of transistors in an integrated circuit doubles approximately every two years. This trend results in smaller, more powerful, and less expensive chips, allowing consumer electronics companies to deliver more functionality to their customers while decreasing product cost. To date, Moore's law has been driven by shrink (making devices ever smaller), and for this to continue, device scaling needs to continue to provide both lower cost and improved performance as we approach the 10nm node (i.e., next-generation technology) and beyond. This requires a comprehensive approach to the entire lithography process, extending the use of immersion lithography (the current state-of-the-art standard wherein a droplet of water is used as the last lens element to enable a larger lens aperture) as well as moving to the next wavelength: extreme UV (EUV) lithography.

Purchase SPIE Field Guide to Optical LithographyFollowing Rayleigh's criterion (minimum resolution = k1 × exposure wavelength/numerical aperture), the industry has for decades focused on decreasing the wavelength of the imaging source and increasing the numerical aperture of the lens to achieve finer printing of chip patterns. These efforts, supplemented with various low-k1 imaging enhancement methods, have pushed feature printing to the theoretical limit of k1 = 0.25.

Today's leading-edge scanners employ a wavelength of 193nm and a numerical aperture of 1.35, resulting in a theoretical resolution limit of 38nm. To go beyond 38nm requires the use of multipatterning techniques, which create unique challenges that must be addressed to achieve the cost-effective manufacturing and high-yielding die that chipmakers require. Continued development of immersion technology along with a holistic lithography approach to the process can both drive productivity and address the yield challenges associated with overlay (a key component of multipatterning) and focus control.

Recently, we achieved new milestones in 300mm wafer scanner productivity. A TWINSCAN NXT:1950i system that we developed operating at 230 wafers per hour processed more than 5250 wafers in a single day in production. Another NXT:1950i completed a record 1.5 million wafers processed in a one-year period. The newest NXT:1970Ci system runs at 250 wafers per hour and will extend these milestones even further. These gains in productivity are necessary for cost-effective manufacturing in multipatterning schemes.

In addition, resolution scaling using multipatterning introduces pattern placement and intralayer overlay challenges that are being met through enhancements we made in the immersion scanner module and overall system improvements.1 These include tighter focus and overlay capability and improved thermal stability at the wafer stage, reduced errors in the lens, process-robust leveling and improved edge focus control at the UV focus sensor, and improved lens heating and reticle heating control. These improvements will support scaling down to the 10nm node. In addition, a holistic approach to lithography addresses three areas that are key to further improving overlay and focus: process window enlargement through computational modeling, process control using on-product metrology, and calibration schemes correlated between simulation and measurement (see Figure 1).


Figure 1. Holistic lithography aims at enlarging the semiconductor device process window to lower costs while improving performance. It involves three key aspects of computational lithography (tuning the mask pattern before manufacturing), scanner lithography (fine tuning scanner parameters based on computational modeling), and metrology (feedback on process drift for real-time correction).

A return to single-exposure lithography is possible with EUV, which is being developed for insertion at the 10nm logic node, the next process step on the semiconductor manufacturing roadmaps.2 Our EUV NXE:3300B systems meet aggressive 2D logic imaging requirements, having demonstrated various device patterns at or below specification, e.g., 16nm lines and spaces (see Figure 2). Likewise, full-wafer matched-machine overlay has been shown below 4nm. For insertion into volume manufacturing, EUV productivity must increase. Productivity is a combination of source power, required resist dose, system transmission, system overhead, and system availability. For production qualification purposes, 500 wafers per day is needed at the end of 2014, rising to volume production levels of typically 1500 wafers per day in 2016. At multiple customer sites, NXE:3300B systems have already exposed more than 600 wafers in a 24-hour period.


Figure 2. EUV (extreme UV) lithography meets aggressive 2D logic imaging requirements. CD: Critical dimension.

In addition to the scanner, a robust industry EUV infrastructure is required. We believe the current EUV infrastructure development has made good progress. We have been able to produce full-field pellicles (protective covers), allowing the mask to stay defect-free during use.3 Mask blank defect reduction has steadily improved. Zeiss has been making good progress in actinic wavelength inspection along with other mask inspection solution providers. And resist manufacturers are seeking novel solutions to increase resist absorption through the use of nanoparticles, relaxing the tension between resist resolution and resist sensitivity.

Overall, we believe the progress of EUV to date is substantive enough to allow chipmakers to qualify their production processes, while continuing development of the overall system and infrastructure to the needed production insertion levels. We will continue to develop the NXT immersion and NXE EUV platforms in parallel, while broadening our holistic lithography technologies to provide chipmakers the tools and flexibility they require to continue to push Moore's law.


Martin van den Brink
ASML
Veldhoven, The Netherlands

Martin van den Brink is president and chief technology officer of ASML. He joined the company when it was founded in early 1984. He earned a degree in electrical engineering from HTS Arnhem, and a degree in physics (1984) from the University of Twente, both in the Netherlands.


References:
1. W. P. de Boeij, R. Pieternella, I. Bouchoms, M. Leenders, M. Hoofman, R. de Graaf, H. Kok, Extending immersion lithography down to 1x nm production nodes, Proc. SPIE 8683, p. 86831L, 2013. doi:10.1117/12.2021397
2. R. Peeters, S. Lok, J. Mallman, M. van Noordenbrug, N. Harned, P. Kuerz, M. Lowisch, EUV lithography: NXE platform performance overview, Proc. SPIE 9048, p. 90481J, 2014. doi:10.1117/12.2046909
3. C. Zoldesi, K. Bal, B. Blum, G. Bock, D. Brouns, F. Dhalluin, N. Dziomkina, Progress on EUV pellicle development, Proc. SPIE 9048, p. 90481N, 2014. doi:10.1117/12.2049276