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Electronic Imaging & Signal Processing

A better CMOS image sensor for ultra-high-definition TV

Nanofabrication improves the sensitivity of a 33Mpixel 120fps CMOS image sensor by increasing the conversion gain from electron charge to signal voltage.
3 June 2014, SPIE Newsroom. DOI: 10.1117/2.1201405.005420

Ultra-high-definition television (UHDTV), which promises a clearer and more aesthetically pleasing viewing experience than currently possible, has attracted much attention in recent years. International standards for the technology are being established by ITU-R (the International Telecommunication Union Radiocommunication Sector)1 and industrial standards by the SMPTE (Society of Motion Picture and Television Engineers),2 all aimed at making UHDTV a reality. For its part, NHK (Japan Broadcasting Corporation) has been researching and developing an ‘8K Super Hi-Vision’ (SHV) system that features 8K resolution and 22.2 multichannel audio with the aim of providing audiences with a sense of ‘being there.’ Table 1 shows the video parameter values for SHV. These parameters are compliant with international standards.

Table 1. Parameters of SHV. H: Horizontal. V: Vertical. RGB: Red, green, blue.
Pixel count 7680 (H) × 4320 (V)
Frame frequency 120Hz, 60Hz
Scanning Progressive
Sampling structure 4:4:4, 4:2:2, 4:2:0
Tone reproduction 12 bit, 10 bit
Color reproduction Wide-gamut RGB

We are currently developing an image sensor (see Figure 1) for a ‘full-spec’ SHV camera system. In the full-spec SHV system, the video signal is characterized by 7680 (H)×4320 (V) pixels (approximately 33Mpixel per frame) with a 4:4:4 RGB (red, green, blue) sampling structure, 120fps (frames per second) progressive scanning, 12-bit tone reproduction, and a wide color gamut. To realize full-spec SHV, we designed and fabricated CMOS image sensors and prototyped a color camera system.3–5

Figure 1. Photo of the 8K Super Hi-Vision (SHV) image sensor.

The image sensor in this system is capable of shooting 33Mpixel and 120fps movies with 12-bit ADC (analog-to-digital converter) resolution. The so-called column-parallel ADC architecture (see Figure 2)—a common CMOS image sensor technology—and our newly developed two-stage cyclic ADC enable high-speed operation and power consumption as low as 2.5W, simultaneously. Within the two-stage cyclic ADC, the first and second cyclic ADCs operate in a pipelined configuration (see Figure 3). Nonetheless, because of its smaller pixel area and a quarter the exposure time, our prototyped three-chip color camera is not as sensitive as existing HDTV cameras, which typically feature 1920×1080 pixels and 30fps. Consequently, we place a high priority on improving sensitivity.

Figure 2. Architecture of the SHV image sensor for ultra-high-definition TV. CML: Current mode logic. LVDS: Low-voltage differential signaling (digital data transfer circuit). CDS: Correlated double sampling (noise reduction circuit). ADC: Analog-to-digital converter.

Figure 3. Structure of the two-stage cyclic ADC. Here, V indicates voltage.

Doing so requires either increasing the output signal (voltage) of each pixel per incoming light or reducing the noise generated in the sensor (i.e., improving the signal-to-noise, or S/N, ratio). We decided to increase the output signal of the pixels (i.e., their sensitivity) through nanofabrication. Pixel sensitivity is determined by multiplying ‘quantum efficiency’ by ‘conversion gain.’ Quantum efficiency refers to the rate at which photons incident on a pixel area are converted to electrons. Conversion gain represents the amount of voltage generated by a single electron in the floating diffusion amplifier (FDA) in the pixel. Nanofabrication reduces the capacitance of the FDA, thus increasing conversion gain, which is inversely proportional to the capacitance. We used a fabrication process suited to a 0.11μm CMOS image sensor instead of 0.18μm, as for the previous device.6

The main difference between the two sensors fabricated with the 0.11 and 0.18μm design rules was the pixel structure, especially the FDA capacitance. Figure 1 shows the fabricated image sensor, and Table 2 lists its specifications. This sensor exhibited a conversion gain of 110μV/e and a sensitivity of 2.4V/lx·s. The conversion gain matched our design value, and the pixel sensitivity increased by 1.6 times. As a result, the input-referred random noise, which gives an indication of the S/N ratio of the sensor, was reduced from the previous sensor's 3.0erms to 2.1erms.

Table 2. Fabricated image sensor specifications. CIS: CMOS image sensor. CIE: International Commission on Illumination.
Process 0.11μm 1P4M CIS
Number of active pixels 7680 (H)×4320 (V)
Number of total pixels 7836 (H)×4372 (V)
Pixel pitch 2.8×2.8μm
Frame frequency 120Hz (maximum)
Conversion gain 110μV/e
Sensitivity 2.4V/lx·s (CIE A-light, IR cut filter)
Random noise 2.1erms (at 120Hz and gain=15)

These experimental results confirmed the effect of nanofabrication on conversion gain and thus the pixel sensitivity. Because a further increase in conversion gain could degrade the dynamic range, we are planning to increase the quantum efficiency by optimizing the pixel design. Refining the design and installing low-profile wiring would increase the aperture ratio and raise the sensitivity. We are continuing to investigate additional means of improving the sensitivity of the image sensor for the practical use of full-spec SHV.

This image sensor is being developed through a collaboration between NHK and Shizuoka University in Japan.

Toshio Yasue
Tokyo, Japan

Toshio Yasue has been researching CMOS image sensors and camera systems at the Science and Technology Research Laboratories of NHK. He received his ME in applied physics from the University of Tokyo in 2008.

1. Parameter values for UHDTV systems for production and international programme exchange, Tech. Rep. ITU-R Rec. BT2020, International Telecommunication Union, Geneva.
2. Ultra high definition television—image parameter values for program production, Tech. Rep. SMPTE ST 2036-1:2013 , Society of Motion Picture and Television Engineers, 2013.
3. T. Watabe, K. Kitamura, T. Sawamoto, T. Kosugi, T. Akahori, T. Lida, K. Isobe, et al., A 33Mpixel 120fps CMOS image sensor using 12b column-parallel pipelined cyclic ADC, ISSCC Dig. Tech. Papers, p. 388-389, 2012.
4. K. Kitamura, T. Watabe, T. Sawamoto, T. Kosugi, T. Akahori, T. Lida, K. Isobe, A 33-megapixel 120-frames-per-second 2.5-watt CMOS image sensor with column-parallel two-stage cyclic analog-to-digital converters, et al., IEEE Trans. Electron. Devices 59(12), p. 3426-3433, 2012.
5. H. Shimamoto, K. Kitamura, T. Watabe, H. Ohtake, N. Egami, Y. Kusakabe, Y. Nishida, et al., 120 Hz frame-rate super hi-vision capture and display devices, SMPTE Mot. Imag. J. 122(2), p. 55-61, 2013.
6. T. Yasue, T. Hayashida, J. Yonai, K. Kitamura, T. Watabe, H. Ootake, H. Shimamoto, et al., A 33-mpixel 120-fps CMOS image sensor using 0.11-μm CIS process, Proc. SPIE 9100, 2014. doi:10.1117/12.2049145