SPIE Startup Challenge 2015 Founding Partner - JENOPTIK Get updates from SPIE Newsroom
  • Newsroom Home
  • Astronomy
  • Biomedical Optics & Medical Imaging
  • Defense & Security
  • Electronic Imaging & Signal Processing
  • Illumination & Displays
  • Lasers & Sources
  • Micro/Nano Lithography
  • Nanotechnology
  • Optical Design & Engineering
  • Optoelectronics & Communications
  • Remote Sensing
  • Sensing & Measurement
  • Solar & Alternative Energy
  • Sign up for Newsroom E-Alerts
  • Information for:
    Advertisers
SPIE Photonics West 2017 | Register Today

SPIE Defense + Commercial Sensing 2017 | Call for Papers

2017 SPIE Optics + Photonics | Call for Papers

Get Down (loaded) - SPIE Journals OPEN ACCESS

SPIE PRESS




Print PageEmail PageView PDF

Astronomy

A microprocessor tough enough for space missions

Processors manufactured with tailored silicon-on-insulator technology can withstand the high levels of radiation in space.
12 June 2013, SPIE Newsroom. DOI: 10.1117/2.1201306.004883

Growing interest in space exploration has increased the demand for vehicles that can achieve high computational speed using minimal power. Here, we describe a new, 1.5cm-wide thin silicon processor that combines these attributes.

The chip, developed by Mitsubishi Heavy Industries Ltd. and Japan's Institute of Space Astronautical Science, comprises a 32-bit processor with a floating-point unit (for numerical operations), and an interface configured for the spacecraft communications network SpaceWire. It achieves a computational speed of 100 mega-instructions per second (MIPS), using less than 1W. The chip is tough, constructed from a commercial hardened silicon-on-insulator (SOI) substrate, which ensures reliability but is also more affordable than some of the specialized SOI materials used in other space chips.

Microprocessors for space applications demonstrate ever-increasing speed, yet their performance remains far slower than that of chips used on earth.1 Achieving 100+ MIPS using less than 1W reduces the energy available for carrying one-bit information. This increases the chip's sensitivity to noise, including high-energy particles such as cosmic rays. In silicon technologies, charged particles that penetrate the chip's substrate create electrons and holes (noise carriers) along their tracks. These intrude into the surface circuit region and lead to malfunctions. As a result, the development of defenses against radiation damage has been a major challenge in producing devices for use in the harsh environment of space. Historically, developers have used SOI structures combining a radiation sensor and an intelligent, large-scale integrated circuit on a monolithic chip to reduce scattering and increase pixel size.2 But these devices remain sensitive to noise,3 therefore we need to carefully tailor SOI devices and circuit structures to maximize the benefits of the technology.


Figure 1. A photomicrograph of the silicon-on-insulator chip.

In an SOI structure, an insulator—namely a buried oxide layer just beneath the circuit—prevents the entrance of noise carriers. However, the insulator also prevents the escape of this charge from the top circuit layer, resulting in noise signal amplification.4 The buried oxide reduces the size of capacitors connected to the circuits. This increases the operation speed, but at the same time increases sensitivity to noise signals.

To mitigate these undesired effects, we conducted numerical and circuit-level simulations of the effects of radiation on SOI devices, to consider how best to optimize them. For our model we used a commercially available 0.2m SOI chip. The device is based on a fully depleted structure, where the silicon layer atop the buried oxide is very thin, and generates limited leakage current. The technology generally exhibits lower noise amplification, and uses less power than other comparable structures. We considered using the body-tie (BT) technique, an electrode design that provides an ‘escape hatch’ for the charge stored in the top surface layer. We also examined the use of two resistor-capacitor (RC) filters, to compensate for the anticipated reduction in capacitance, which would, theoretically, slow operation.

Having selected the RC option, however, we were able to minimize the signal delay to ≤30%, due to the noise level reduction using the BT technique. We successfully reduced the radiation sensitivity of the static random access memory (SRAM): the circuit most sensitive to irradiation (see Figure 2). For a 4Mb SRAM installed on equipment in geostationary orbit, the estimated error rate was 3.1×10−7 per device per day. 5


Figure 2. Radiation sensitivities of static random access memory circuits (SRAMs). Radiation strikes can upset bit data stored in the circuits. We can measure probabilities or cross sections of such events for ions with various linear energy transfers (LETs). Note that the number of noise electrons/holes becomes greater for high LET particles. Even when fabricated with silicon-on-insulator technology, the memory structure exhibits high sensitivity, therefore stronger protection is needed for the circuits to be used in space. BT: body-tie electrode design. RC: resistor-capacitor filters. MeV: milli-electron volt.

We plan to launch the chip on satellites soon. For future space missions, with advanced information and communication systems, we are developing a radiation-hardened analog-circuit clock generator (which produces a timing signal to synchronize the circuit's operation) to increase the chip's computation speed.


Daisuke Kobayashi, Kazuyuki Hirose, Hirobumi Saito
Institute of Space and Astronautical Science
Japan Aerospace Exploration Agency
Sagamihara, Japan

Daisuke Kobayashi is an assistant professor specializing in the reliability of semiconductor devices. His focus is on transient radiation effects on silicon-on-insulator devices.

Kazuyuki Hirose is a professor working on the research and development of semiconductor devices for space applications.

Hirobumi Saito is a professor focused on the research and development of small satellites.


References:
1. R. C. Lacoe, J. V. Osborn, R. Koga, S. Brown, D. C. Mayer, Application of hardness-by-design methodology to radiation-tolerant ASIC technologies, IEEE Trans. Nuclear Sci. 47, p. 2334-2341, 2000.
2. Y. Arai, T. Miyoshi, Silicon-on-insulator technology enables next-generation radiation image sensors, SPIE Newsroom, 2009. http://spie.org/x36212.xml.
3. D. Kobayashi, K. Hirose, H. Saito, Radiation-tolerant microprocessors in Japanese scientific space vehicles: how to maximize the benefits of commercial SOI technologies, Proc. SPIE 8725, p. 872517, 2013. doi:10.1117/12.2015658
4. V. Ferlet-Cavrois, C. Marcandella, G. Giraud, G. Gasiot, T. Colladant, O. Musseau, C. Fenouillet, J. du Port de Poncharra, Characterization of the parasitic bipolar amplification in SOI technologies submitted to transient irradiation, IEEE Trans. Nuclear Sci. 49, p. 1456-1461, 2002.
5. K. Hirose, H. Saito, Y. Kuroda, S. Ishii, Y. Fukuoka, D. Takahashi, SEU Resistance in advanced SOI-SRAMs fabricated by commercial technology using a rad-hard circuit design, IEEE Trans. Nuclear Sci. 49, p. 2965-2968, 2002.