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Micro/Nano Lithography

Integrating wafer-scalable graphene with ubiquitous silicon technology

Synthesis of nearly defect-free monolayer graphene can be combined with silicon technology to create innovative next-generation electronic and optical systems and sensor devices.
21 May 2013, SPIE Newsroom. DOI: 10.1117/2.1201305.004876

Very large-scale integrated (VLSI) silicon technology has endured and advanced so much over the last six decades that it is now a ubiquitous platform, allowing affordable applications in diverse industries ranging from defense to consumer electronics. In contrast, graphene is a relatively new material, consisting of a single atomic sheet of carbon atoms arranged in a hexagonal crystalline pattern, with an electronic structure that makes it an outstanding conductor.1–3 Graphene has several unique properties beyond those offered by silicon, including k efficient electrical/thermal conductance, rich infrared and optical behavior, and a large surface-area-to-volume ratio. Consequently, combining graphene with mature silicon VLSI technology (see Figure 1) promises the best of both materials, yielding a wealth of advanced electronic, thermal, and photonic systems and sensor devices.

Figure 1. (Top) Illustration of graphene-silicon hybrid nanotechnology. (Bottom) Graphene integrated on a 0.18μm commercial silicon chip. The single-layer graphene is not visible but can be identified by its characteristic Raman peaks. G marks the graphite peak and 2D marks the two-dimensional graphene peak. a.u.: arbitrary units.

However, graphene only grows on certain surfaces, and this excludes silicon. The challenge, therefore, is the transfer of graphene from a growth surface onto the target silicon wafer. The popular method of synthesizing high-quality graphene on copper foils,4 while ideal for integration with flexible substrates, does not lend itself to straightforward integration with silicon in a manner compatible with industrial VLSI processes: the foils are not sufficiently rigid. Other approaches, such as the use of rigid (thick) single-crystal metal substrates or discs are costly and lead to substantial metal consumption and waste.

To overcome these problems, we have developed a method of growing graphene on copper-coated oxidized silicon wafers from where they can be subsequently transferred. The technique is scalable to arbitrary wafer sizes (see Figure 2).3Importantly, the graphene synthesized offers material quality comparable to pristine exfoliated graphene flakes from natural graphite ore, which are recognized to be of the highest material quality produced so far. Further, our graphene synthesis, originally achieved on 100mm silicon wafers, has been successfully scaled to 300mm wafers in a commercial chemical vapor deposition system manufactured by Aixtron. This is an important milestone for integrating graphene with silicon VLSI, which is widely based on the 300mm wafer size.

Figure 2. Photograph of a polymer/graphene sheet transferred onto a 100mm oxidized silicon wafer. The polymer serves as a support layer during transfer and is subsequently removed.

After extensive initial exploratory investigations in our lab to find the optimal growth conditions, the entire process is now routine. We begin by depositing thin copper films (∼1μm) on silicon oxide/silicon substrates. These are subsequently annealed at high temperatures to crystallize the copper into the so-called (111) phase, the hexagonal close-packed atomic surface of which promotes high-quality graphene synthesis. We use diffraction spectroscopy to confirm that the copper (111) phase has formed correctly, and scanning electron microscopy to determine the copper grain size.

Graphene synthesis is then carried out by flowing methane over the copper substrate at ∼1000°C. We use Raman spectro-scopy to confirm the growth of high-quality graphene—see Figure1 (bottom)—and scanning tunneling microscopy to confirm the presence of a single atomic graphene layer. To optimize growth conditions, we suppress copper evaporation by increasing the surface pressure, which leads to large grains of wrinkle-free graphene ∼50μm in size. We also impregnate the copper film with hydrogen, which serves as a co-catalyst for graphene growth.2 The limited availability of hydrogen in the copper film is an optimal condition for the production of defect-free single-layer graphene. An excessive amount of hydrogen tends to produce graphene of lower quality.5

During the course of these studies, we developed our own metrology software, called GRISP, to aid in evaluating material quality by statistically analyzing large Raman maps collected across a wafer.6 GRISP is freely available at the online portal nanohub.org. Extensive analysis of growth reveals a uniform sheet of graphene with material quality comparable to pristine samples made by mechanical exfoliation, one of the most common methods of making graphene.

We were also able to transfer graphene onto 100mm oxidized silicon wafers using the lift-off method. Our initial studies of fabricated graphene transistors typically indicated mobilities of less than 2000cm2/Vs under ambient conditions, a value four to five times lower than comparable transistors based on exfoliated flakes.7 The reduced mobility is due to residual contamination during the lift-off process. To mitigate this issue, we have collaborated with the Ruoff and Dodabalapur groups at the University of Texas at Austin to establish novel techniques. These include the use of dilute polymers for the lift-off transfer to minimize residue, and post-transfer formamide or fluoropolymer treatment to restore graphene's electrical properties.8,9 As a result, our recent graphene transistors on oxidized silicon have achieved outstanding performance: mobilities of 4000–10,000cm2/Vs, electron-hole symmetry, and field-effect ON/OFF current modulation of greater than an order of magnitude (see Figure 3).8, 9

Figure 3. Electrical characteristics of a high performance graphene transistor on oxidized silicon, showing strong electron-hole symmetry and gate modulation of about 15, where R is resistance in ohms. Measurements were taken at room temperature.

In summary, our work on synthesizing graphene at the wafer-scale and subsequent transfer to silicon has substantially advanced the practical prospects of graphene-silicon technology to the extent that our results have now been scaled to 300mm wafers. Graphene-silicon technology is of great interest because it will enable the unique properties of graphene to be combined with ubiquitous VLSI technology, and so realize great improvements in integrated device capability and performance. Our ongoing effort has integrated graphene devices with 0.18μm commercial silicon technology: see Figure 1. Our future work involves exploring wafer bonding as a more compatible automated graphene transfer method onto commercial VLSI wafers, and the design of hybrid circuits composed of graphene and silicon devices.

We acknowledge fruitful discussion and collaboration with Rod Ruoff and Ananth Dodabalapur at the University of Texas at Austin. This work is supported in part by an NSF CAREER award. Wafer-scale graphene was grown in an Aixtron BM CVD chamber.

Deji Akinwande
University of Texas
Austin, TX

Deji Akinwande received his PhD degree in electrical engineering from Stanford University in 2009. He is currently an assistant professor at the University of Texas at Austin, where he works on nanomaterials and nanoelectronics. He has received a number of awards including the 2012 IEEE NANO ‘Geim and Novoselov’ graphene prize.

1. A. K. Geim, K. S. Novoselov, The rise of graphene, Nat. Mater. 6(3), p. 183-191, 2007.
2. L. Tao, J. Lee, H. Chou, M. Holt, R. S. Ruoff, D. Akinwande, Synthesis of high quality monolayer graphene at reduced temperature on hydrogen-enriched evaporated copper (111) films, ACS Nano 6, p. 2319-2325, 2012.
3. L. Tao, J. Lee, M. Holt, H. Chou, S. McDonnell, D. Ferrer, M. Babenco, R. Wallace, S. Banerjee, R. Ruoff, D. Akinwande, Uniform wafer-scale chemical vapor deposition of graphene on evaporated Cu (111) film with quality comparable to exfoliated monolayer, J. Phys. Chem. C 116, p. 24068-24074, 2012.
4. X. Li, W. Cai, J. An, S. Kim, J. Nah, D. Yang, R. Piner, A. Velamakanni, I. Jung, E. Tutuc, S. K. Banerjee, L. Colombo, R. S. Ruoff, Large-area synthesis of high-quality and uniform graphene films on copper foils, Science 324(5932), p. 1312-1314, 2009.
5. I. Vlassiouk, M. Regmi, P. Fulvio, S. Dai, P. Datskos, G. Eres, S. Smirnov, Role of hydrogen in chemical vapor deposition growth of large single-crystal graphene, ACS Nano 5(7), p. 6069-6076, 2011.
6. M. G. Babenco, L. Tao, D. Akinwande, Graphene Raman imaging and spectroscopy processing: characterization of graphene growth, Proc. SPIE 8466, p. 84660O, 2012. doi:10.1117/12.928711
7. A. Venugopal, L. Colombo, E. M. Vogel, Issues with characterizing transport properties of graphene field effect transistors, Solid State Commun. 152(15), p. 1311-1316, 2012.
8. J. W. Suk, W. H. Lee, J. Lee, H. Chou, R. D. Piner, Y. Hao, D. Akinwande, R. S. Ruoff, Enhancement of the electrical properties of graphene grown by chemical vapor deposition via controlling the effects of polymer residue, Nano Lett., 2013.
9. T. J. Ha, J. Lee, D. Akinwande, A. Dodabalapur, The restorative effect of fluoropolymer coating on electrical characteristics of graphene field-effect transistors, IEEE Electron Device Lett. 34(4), p. 559-561, 2013.