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Micro/Nano Lithography

Directed self-assembly for ever-smaller printed circuits

A novel patterning technique directly forms 29nm-pitch fins etched into silicon on insulator, making logic and memory components.
5 April 2013, SPIE Newsroom. DOI: 10.1117/2.1201303.004743

Field effect transistors (FETs) composed of discrete silicon (Si) active regions or ‘fins,’ referred to as finFETs, have superior electrostatic properties compared to planar devices (see Figure 1).1 As a result, they are likely to play a role in further miniaturization of electronic devices.2 However, density requirements for fin patterning have exceeded what can be achieved through direct printing by 193nm immersion (193i) lithography. Consequently, sublithographic patterning techniques that can extend the resolution of 193i to the sub-80nm pitch regime (i.e., where the distance between identical features is less than 80nm) are now of vital importance.

Figure 1. A 3D schematic of a finFET device. Because the gate wraps around the channel region between source and drain of a finFET, the same level of gate control can be achieved with a shorter gate length. Dfin: Fin width. Hfin: Fin height. Lg: Gate length.

Sidewall image transfer (SIT) is now commonly used to manufacture 22nm-node finFET-based technology (meaning the transistor is 22nm across).2 The SIT process doubles the spatial frequency of a template or mandrel shape printed by a conventional lithography through a sequential deposition and etch process. This forms a feature along the sidewalls of the template shape similar to an offset spacer in a CMOS transistor. By removing the template shape selectively, the remaining sidewall features can be used for further pattern transfer. Coupled with 193i, SIT can be used to fabricate grating-like features with a minimum full pitch of ∼40nm. A further lithography step can be used to customize the grating pattern into a circuit pattern provided it obeys certain design rule restrictions determined by the SIT process.

Extending SIT to the sub-40nm pitch regime requires us to reduce the template pitch to less than 80nm. This can be achieved using multiple interleaved 193i exposures or a higher resolution lithography, such as extreme ultraviolet or electron beam lithography. Another option is to perform a further iteration of the SIT process, resulting in a tripling or quadrupling of pitch. While these approaches can all lead to finer pitch patterning, each has an associated risk, increased process complexity, or both. Furthermore, the accuracy of the lithography used to customize the resulting grating patterns needs to improve as the feature pitch is reduced. This is especially a concern when lines need to be removed from the long axis of the grating, requiring that customized shapes land precisely between the grating features. This requirement may not be readily achievable in the sub-30nm pitch regime, barring major advancements in overlay and pattern placement control.

The impending limitations of self-aligned multiple patterning and the continued delays in a post-193nm exposure option have created an opportunity for sublithographic line space patterning based on the directed self-assembly (DSA) of block copolymers (BCPs). DSA combines lamellae-forming self-assembling materials with lithographically defined template patterns to produce grating-like structures (see Figure 2).3–7 Track-compatible DSA patterning processes have demonstrated that low-defectivity wafer-scale gratings with 25nm pitch can be achieved after selective removal of one of the BCP domains.7–9 Although this enables fantastic pitch-scaling, a strategy is required to apply DSA to manufacturing circuit patterns without aggressive customization strategies and the same stringent overlay requirements as self-aligned multiple patterning.

Figure 2. Directed self-assembly (DSA) uses lithographically defined lines to guide the phase separation of a block co-polymer film. Block co-polymer films naturally phase separate into periodic patterns with a feature size pre-defined by the molecular weights of the block co-polymer. By combining bottom up lamellae forming self-assembling materials with top down lithographically defined template patterns, gratings at very small pitches can be achieved. CD: Critical dimension.

We previously demonstrated robust etch transfer of DSA patterns into three commonly used device integration materials: silicon, silicon nitride, and silicon dioxide based on tetraethyl orthosilicate.10 We studied the evolution of the critical dimension, line edge roughness (LER), and line width roughness during pattern transfer. This work showed that co-optimization of etch process parameters and materials used in the multilayer masking film stack can improve the quality of the final transferred pattern. We also demonstrated that the use of post-etch annealing can further reduce the LER of DSA-patterned silicon on insulator (SOI) lines from ∼3nm to less than 2nm. These results laid a solid foundation for studying DSA for advanced CMOS circuit patterning applications.

We continue to develop next-generation patterning technologies with DSA (see Figure 3). For example, we can now pattern-transfer circuit-like DSA patterns into materials of relevance for front-end-of-line device integration.12 We also developed two patterning strategies for generating sub-30nm pitch line-space patterns with DSA using grapho-epitaxy13 and chemo-epitaxy.14 Both techniques provide a method to directly form local, small area gratings with controlled numbers of lines and deterministically controlled spaces between groups of lines. These innovations circumvent the need for customization lithography with aggressive overlay requirements. We used these techniques to pattern finFET logic and static random-access memory circuits, which have implications for circuit design and circuit scaling.11 Finally, we also demonstrated a prototype computational toolset to enable early leaning on how design style impacts pattern printability.15 By co-optimizing both the circuit design and patterning process, we expect to enable DSA patterning of semiconductor devices and circuits in a 300mm product development environment.16

Figure 3. A fin patterning example for a logic library design.11(a) Fin design. (b) Directed self-assembly (DSA) fins after etch transfer into a silicon-on-insulator (SOI) substrate. The pitch of all dense lines is 29nm.

In summary, our DSA-based patterning technique directly forms 29nm-pitch fins etched onto SOI, and this allowed us to implement a library of miniaturized finFET logic and SRAM patterns. High-resolution, high-throughput patterning techniques are required to enable continued scaling of high-volume CMOS manufacturing beyond the 10nm node. We are now closing the gaps between research and development and are actively seeking industrial partners to position DSA as a vital technique for patterning of the single-digit process nodes.

This work is sponsored by the Defense Advanced Research Projects Agency ‘GRATE’ (Gratings of regular arrays and trim exposures) program under Air Force Research Laboratory (AFRL) contract FA8650-10-C-7038. The views expressed are those of the author and do not reflect the official policy or position of the Department of Defense or the US Government. Approved for Public Release, Distribution Unlimited.

HsinYu Tsai, Michael Guillorn
IBM TJ Watson Research Center
Yorktown Heights, NY

HsinYu (Sidney) Tsai received her PhD from the EECS department at MIT in 2011. She is currently working in the Nanofabrication and Electron Beam Lithography group. Her main research activity is developing next-generation lithography for circuit applications with directed self-assembly.

Gregory Doerk, Joy Cheng, Daniel Sanders
IBM Almaden Research Center
San Jose, CA
Kafai Lai
Semiconductor Research and Development Center
Hopewell Junction, NY
Chi-Chun Liu, Matthew Colburn
Albany NanoTech
Albany, NY

1. C.-H. Lin, W. Haensch, P. Oldiges, H. Wang, R. Williams, J. Chang, M. Guillorn, Modeling of width-quantization-induced variations in logic FinFETs for 22nm and beyond, 2011 Symp. VLSI Technol. (VLSIT), p. 16-17, 2011.
2. C. Auth, C. Allen, A. Blattner, D. Bergstrom, M. Brazier, M. Bost, M. Buehler, V. Chikarmane, T. Ghani, T. Glassman, A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors, Proc. IEEE VLSI Symposium (Symp. VLSI Tech. Dig.) 131, 2012. doi:10.1109/VLSIT.2012.6242496
3. C. T. Black, R. Ruiz, G. Breyta, J. Y. Cheng, M. E. Colburn, K. W. Guarini, H-C. Kim, Y. Zhang, Polymer self assembly in semiconductor microelectronics, IBM J. Res. Dev. 51(5), p. 605-633, 2007. doi:10.1147/rd.515.0605
4. J. Y. Cheng, D. P. Sanders, H. D. Truong, S. Harrer, A. Friz, S. Holmes, M. Colburn, W. D. Hinsberg, Simple and versatile methods to integrate directed self-assembly with optical lithography using a polarity-switched photoresist, ACS Nano 4(8), p. 4815-4823, 2010. doi:10.1021/nn100686v
5. S. J. Jeong, H. S. Moon, B. H. Kim, J. Y. Kim, J. Yu, S. Lee, M. G. Lee, H.Y. Choi, S. O. Kim, Ultralarge-area block copolymer lithography enabled by disposable photoresist prepatterning, ACS Nano 4(9), p. 5181-5186, 2010. doi:10.1021/nn101212q
6. C.-C. Liu, P. F. Nealey, A. K. Raub, P. J. Hakeem, S. R. J. Brueck, E. Han, P. Gopalan, Integration of block copolymer directed assembly with 193 immersion lithography, J. Vac. Sci. Technol. B 28(6), p. C6B30-C6B34, 2010. doi:10.1116/1.3501348
7. C. Bencher, J. Smith, L. Miao, C. Cai, Y. Chen, J. Y. Cheng, D. P. Sanders, M. Tjio, H. D. Truong, S. Holmes, W. D. Hinsberg, Self-assembly patterning for sub-15nm half-pitch: a transition from lab to fab, Proc. SPIE 7970, p. 79700F, 2011. doi:10.1117/12.881293
8. B. Rathsack, M. Somervell, J. Hooge, M. Muramatsu, K. Tanouchi, T. Kitano, E. Nishimura, K. Yatsuda, S. Nagahara, I. Hiroyuki, K. Akai, T. Hayakawa, Pattern scaling with directed self assembly through lithography and etch process integration, Proc. SPIE 8323, p. 83230B, 2012. doi:10.1117/12.916311
9. P. A. Rincon Delgadillo, R. Gronheid, C. J. Thode, H. Wu, Y. Cao, M. Somervell, K. Nafus, P. F. Nealey, All track directed self-assembly of block copolymers: process flow and origin of defects, Proc. SPIE 8323, p. 83230D, 2012. doi:10.1117/12.916410
10. H. Tsai, H. Miyazoe, S. Engelmann, B. To, E. Sikorski, J. Bucchignano, D. Klaus, Ch.-Ch. Liu, J. Cheng, D. Sanders, N. Fuller, M. Guillorn, Sub-30nm pitch line-space patterning of semiconductor and dielectric materials using directed self-assembly, J. Vac. Sci. Technol. B 30(6), p. 06F205, 2012. doi:10.1116/1.4767237
11. K. Vaidyanathan, S. H. Ng, D. Morris, N. Lafferty, L. Liebmann, M. Bender, W. Huang, K. Lai, L. Pileggi, A. Strojwass, Design and manufacturability tradeoffs in unidirectional and bidirectional standard cell layouts in 14nm node, Proc. SPIE 8327, p. 83270K, 2012. doi:10.1117/12.916104
12. H. Tsai, Pattern transfer of directed self-assembly patterns for CMOS device applications, Proc. SPIE 8685, p. 8685-19, 2013. (Invited paper.)
13. H. Tsai, Directed self-assembly pattern generation of basic FinFET circuit constructs, Proc. SPIE 8680, p. 8680-32, 2013. (Invited paper.)
14. G. Doerk, Fabrication of deterministically isolated gratings through directed self-assembly of block copolymers, Proc. SPIE 8680, p. 8680-33, 2013. (In press).
15. K. Lai, Computational aspects of optical lithography extension by directed self assembly, Proc. SPIE 8683, p. 8683-3, 2013. (In press.)
16. C.-C. Liu, Directed self-assembly process integration in a 300mm pilot line environment, Proc. SPIE 8680, p. 86820K, 2013. doi:10.1117/12.2012018