Electronic devices on silicon chips have been reducing steadily in size for over 40 years. From the very beginning in the 1960s, Gordon Moore predicted that the number of transistors on a silicon chip would double every two years. This trend, the famous Moore's law, has become a self-fulfilling prophecy, driving industry requirements for each new generation of silicon chips and leading to dramatic increases in the speed and performance of integrated circuits. Here, the basic circuit building blocks are semiconductor transistors, devices that act as valves to control the circuit current. Each transistor contains a ‘channel’ region where current can flow. This current can be switched on or off by a voltage applied to a ‘gate’ region in close proximity to the channel, allowing charge to be controlled and transferred within the circuit.
Existing large-scale integrated circuits use CMOS technology based on silicon field-effect transistors (MOSFETs). Each successive generation of CMOS circuits has seen a reduction in the dimensions of the MOSFET, and at present, the minimum dimensions of this device are only ∼35nm. It is expected that the MOSFET can remain viable down to the 10nm scale. However, below this, difficulty in controlling the device current, and the strong influence of quantum mechanical effects such as electron tunneling, may require new devices. Furthermore, increasing difficulty in fabricating large numbers of highly nanoscale devices using conventional optical lithographic techniques greatly compounds the problem. This implies that a different approach may be essential to create a ‘beyond-CMOS’ generation of electronic devices, perhaps as soon as 2018.
(a) Development-less, positive-tone closed-loop scanning probe lithography (SPL) on calixarene-based molecular glass resist, using self-actuating, piezoresistive scanning probes. (b) Scanning electron microscopy image of a corner pattern written in 10nm-thick 4M1AC6 resist, with 40V bias voltage and 30nC/cm line dose.4
(c) Atomic force microscopy image of lithographic test features written with 30V bias voltage and a line dose of 32nC/cm (broad lines) and 20nC/cm (small lines), respectively. The image was taken directly after lithography with the same cantilever.
Fabricating future devices in nanoelectronics, nanophotonics, and nanoelectromechanical systems requires lithography at the single-nanometer level with high alignment accuracy between patterns, acceptable throughput, cost, and reliability.1 To address this, we have been working on technology using a combination of high-resolution scanning probe lithography (SPL) and nanoimprint lithography (NIL). We believe this combination is a promising candidate for high-throughput device fabrication even at the sub-5nm scale.
Scanning probes are capable of confined nanoscale interactions for imaging, probing of material properties, and lithography at the single-nanometer scale or even smaller. We are investigating novel single-nanometer manufacturing technologies using modified scanning probes to pattern molecular-glass-based resist materials (see Figure 1).1–4 Due to the small particle size (<1nm) and truly monodisperse nature (i.e., the particles are all of similar size) of molecular resists, a more uniform and smaller lithographic pixel size can be defined in comparison with conventional resists. Our lithographic process4 uses the same nanoprobe for atomic force microscope (AFM) pre-imaging to allow pattern overlay alignment, direct writing of features into calixarene molecular resist using a highly confined, development-less resist removal process via emission of low-energy electrons, and AFM post-imaging for final in situ inspection.
(a) Room-temperature single-electron transistor (SET) defined in nanocrystalline silicon material. (b) Single-electron oscillations in the SET shown in (a).7
(c) Silicon nanochains prepared by thermal evaporation of silicon dioxide. (d) A room-temperature Coulomb staircase in a SET fabricated using a single silicon nanochain.8
: Drain-source current. Vds
: Drain-source voltage. Vgs
: Gate-source voltage.
In the near term, a combination of SPL/NIL may enable a transition from non-planar so-called Fin-FET devices to planar silicon nanowire devices5 that have a FET channel fully surrounded by gates and the channel cross-section measuring ∼10nm in both dimensions. However, a far greater technological challenge would be a transition to quantum-effect devices such as single-electron and quantum-dot devices operating at room temperature, allowing control of charge at the single-electron level. Unlike classical devices, these devices inherently improve in performance with reduction in size. The single-electron transistor (SET) in silicon (see Figure 2),6 with dimensions ∼10nm, is perhaps the most widely investigated of these devices for practical application. We may use purely lithographic approaches to fabricate SETs, or a combination of lithography and material morphology. For example, following the latter approach, we have fabricated room-temperature SETs using electron-beam lithography and silicon nanocrystals ∼10nm in size (see Figure 2).7,8 However, high-throughput fabrication of devices at the sub-5nm scale is necessary for practical application, and the SPL/NIL approach may enable this. SPL techniques have already been used to fabricate devices of these dimensions. For example, quantum-dot devices have been constructed with atomic-level precision.9
In conclusion, combining SPL and NIL offers a promising route toward reliable single-nanometer lithography. We can improve throughput drastically by employing parallel, self-actuated, and self-sensing probe arrays. Probe-based closed-loop lithography can be used for sub-5nm fabrication of nanoimprint templates, as well as rapid nanoscale prototyping of ‘beyond CMOS’ nanoelectronic devices. Ultimately, it is possible to envisage a transition from classical, advanced FET devices to quantum-effect devices at the single-nanometer scale. As a next step, we are working to make quantum-effect semiconductor devices only a few nanometers in size and enable the practical application of quantum-dot and single-electron devices.
Imperial College London
London, United Kingdom
Zahid Durrani is a senior lecturer, working on nanoscale electronic devices. These include single-electron and quantum-dot devices in silicon, silicon nanowire FETs, and thermoelectric devices using semiconductor nanostructures.
Marcus Kaestner, Manuel Hofer, Tzvetan Ivanov, Ivo Rangelow
Ilmenau University of Technology
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7637, p. 76370V, 2010. doi:10.1117/12.852265
2. M. Kaestner, I. W. Rangelow, Scanning proximal probe lithography for sub-10nm resolution on calixresorcinarene, J. Vac. Sci. Technol. B 29, p. 06FD02, 2011.
3. M. Kaestner, I. W. Rangelow, Scanning probe lithography on calixarene, Microelectron. Eng. 97, p. 96, 2012.
4. M. Kaestner, I. W. Rangelow, Multi-step scanning probe lithography (SPL) on calixarene with overlay alignment, Proc. SPIE
8323, p. 83231G, 2012. doi:10.1117/12.916263
5. M. Zaremba-Tymieniecki, C. Li, K. Fobelets, Z. A. K. Durrani, Field-effect transistors using silicon nanowires prepared by electroless chemical etching, IEEE Elec. Dev. Lett. 31, p. 860, 2010.
6. Z. A. K. Durrani, Single-Electron Devices and Circuits in Silicon, Imperial College Press, London, 2010.
7. Y. T. Tan, T. Kamiya, Z. A. K. Durrani, H. Ahmed, Room temperature nanocrystalline silicon single-electron transistors, J. Appl. Phys. 94, p. 633, 2003.
8. M. A. Rafiq, Z. A. K. Durrani, H. Mizuta, A. Colli, P. Servati, A. C. Ferrari, W. I. Milne, S. Oda, Room temperature single electron charging in single silicon nanochains, J. Appl. Phys. 103, p. 53705, 2008.
9. M. Fuechsle, S. Mahapatra, F. A. Zwanenburg, M. Friesen, M. A. Eriksson, M. Y. Simmons, Spectroscopy of few-electron single-crystal silicon quantum dots, Nat. Nanotechnol. 5, p. 502, 2010.