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Micro/Nano Lithography

Multiple-electron-beam direct-write comes of age

For the first time in half a century, electron-beam lithography shows signs of living up to its promise of manufacturing semiconductor circuits in high volume.

14 January 2013, SPIE Newsroom. DOI: 10.1117/2.1201212.004609

Electron-beam (e-beam) imaging supports resolution and depth of focus superior to conventional lithography techniques, but single-beam writing has never been able to compete with massively parallel optical systems in throughput and cost. Now, three developments have convinced us that the time for e-beam lithography has arrived. Digital electronics can affordably provide a gigabit per second data rate in a manageable space, enabling very high wafer throughput. Microelectrical mechanical systems and packaging techniques have advanced sufficiently to support a several order of magnitude increase in beam number and high-speed beam writing. And e-beam techniques generally offer higher resolution than optical systems. Pushed to the limit, optical systems must resort to pitch splitting with multiple patterning, driving up complexity and cost. Alternatively, to match e-beam resolution, optical systems must reduce their imaging wavelength to 13.5nm, which also is costly and difficult.

We at Taiwan Semiconductor Manufacturing Company (TSMC) together with KLA-Tencor have proposed a reflective e-beam lithography (REBL) system that can potentially enable multiple-e-beam direct-write for high-volume manufacturing.1, 2 REBL consists of reflective electron optics, a dynamic pattern generator, temporal dose integration, optical wafer alignment, and magnetic levitation stage technologies (see Figure 1).

Figure 1. The reflective e-beam lithography (REBL) system. EXB: Electromagnetic. WMS: Wafer metrology site. (Printed with permission of KLA-Tencor.)

In the REBL system, the oblique electron gun shoots a beam of electrons into a series of lenses. The lenses bend the beam so that it illuminates the dynamic pattern generator at a 90° angle, and decelerate it to a very low voltage. The dynamic pattern generator is a CMOS circuit with its last layer of metal pads facing the illumination. Some of the pads have negligible voltage to absorb incident electrons, while other pads with negative voltage of ∼2 volts reflect the electrons back through the optics. These reflected electrons etch their pattern onto the wafer. The pads' voltage can be switched as quickly as the data processors can work, enabling a fast, smooth direct-write process. The electron column is designed for 10cm diameter to accommodate the eventual high-volume manufacturing system. Such a small diameter facilitates column clustering on the wafer, as shown in Figure 2. As many as 36 columns can be clustered on either a rotary stage or six linear stages.

Figure 2. Linear stages for REBL high-volume manufacturing. (Printed with permission of KLA-Tencor).

REBL is potentially low cost because small-field electron columns are much less expensive than large-field high numerical aperture (NA) optical lenses. The major cost advantage of multi-e-beam direct-write systems is their ability to dynamically change each pixel in real time. For larger features, a larger blur size is allowed, thus permitting a higher beam current to increase throughput. In addition, resists of higher sensitivity can be used because the shot noise effect is less severe for larger features. Since each column supports more wafers per hour, fewer e-beam columns and platforms are needed. Each e-beam column costs several hundred thousand dollars, while one optical column costs many tens of millions. The difference is more than two orders of magnitude: a very significant savings in favor of e-beam technology.

The exposure cost of three systems per silicon area per hour is shown in Figure 3. The four types of scanners represent the exposure tool used for the critical layers of each node. These scanners consist of a dry 0.93 NA scanner using 193nm light, a 1.35 NA 193nm water-immersion scanner using single patterning, a similar immersion scanner using double patterning, and a 0.33 NA extreme UV scanner using 13.5nm light. The commercial cost of scanners is used for the comparison with the cost of the multi-e-beam systems, calculated according to a proposal from a potential supplier.

Figure 3. Cost per silicon area per hour of 300mm scanners, 300mm multi-e-beam systems, and 450mm multi-e-beam systems. The half-pitch for the four logic nodes shown is 65, 32, 22, and 16nm respectively. Multi-e-beam systems are less expensive than their corresponding scanner counterparts. MEB DW: Multi-e-beam direct-write.

We have simulated e-beam imaging with actual electron column parameters and shown that the depth of focus—i.e., the longitudinal distance the wafer can be misplaced and still get usable imaging—exceeds 1μm with 10% exposure latitude. Optical systems struggle with <100nm depth of focus. The overlay accuracy is expected to be better than that of optical systems because the overlay budget from the mask is eliminated and the e-beam position can be manipulated in real time. Multi-e-beam direct write using the REBL writing strategy for all layers removes the 26x33mm2 field-size limitation imposed by the mask and the scanner lens.

A direct-writing tool such as REBL can be used for prototyping to prove out a given design, or explore the characteristics of a next-generation device, without the cost and time required to design optical masks. The repairs, inspections, contamination, and cycle time inherent in optical systems can also be eliminated. However, more wafer inspection will be needed initially for multi-e-beam direct-write systems. In the long run, data-generation errors can be prevented with electronic data checking. If a platform is used to expose many wafers simultaneously, there is ample space to place monitoring and characterizing sensors for real-time adjustments and corrections. Of course, these advantages are not limited to the REBL system, and different multi-e-beam direct-write systems can be designed to fit the specific high-volume manufacturing need. Our next steps in this area will build dynamic pattern generators, 100mm columns, and full-wafer exposure systems for 16nm half-pitch manufacturing.

Burn Lin
Hsinchu, Taiwan

Burn Lin is a distinguished fellow and vice president of research and development at TSMC, a member of the US National Academy of Engineering, IEEE Fellow, and SPIE Fellow. Prior to TSMC, he worked at IBM's T. J. Watson Research Center and General Technology Division before founding Linnovation, Inc.

1. B. J. Lin, Future of multiple-e-beam direct-write systems, J. Micro/Nanolith MEMS MOEMS 11(3), p. 033011, 2012. doi:10.1117/1.JMM.11.3.033011
2. M. A. McCord, P. Petric, U. Ummethala, A. Carroll, S. Kojima, L. Grella, S. Shriyan, C. T. Rettner, C. F. Bevis, REBL: design progress toward 16nm half-pitch electron-beam lithography, Proc. SPIE 8323, p. 832811, 2012. doi:10.1117/12.919744