A mask is a tool required to replicate a set of complicated IC geometries numerous times to produce microchips in large volume. It is a key element in the new product introduction cycle, and arguably the most critical part in the manufacturing process due to its huge impact if not done right. Today, the definition of right means perfection. Whether for data completeness or pattern fidelity (placement and size), the requirement is zero flaws. Moreover, mask-making, including the optical proximity correction (OPC) photolithography enhancement technique, serves as a bridge that carries design data to manufacturing and feeds back OPC-unfriendly layouts to designers so they can improve design for manufacturing (DFM).
This process has worked well in the past and allowed end users in fabless as well as integrated device manufacturer companies to build the most complicated chips in the world. An example is NVIDIA's Kepler graphics processor unit manufactured using 28nm technology (see Figure 1). It consists of 3.5 billion transistors, 10 billion contacts, and 12 billion vias among the 10 interconnect layers.
Figure 1. The complex Kepler GK104 chip, with 3.5 billion transistors, in a graphics card.
While we are making test chips for future technology nodes and design rules, we also are facing new challenges and will encounter even more as we follow Moore's law—the doubling of the number of transistors on ICs every two years—to build future chips with higher performance, less power dissipation, and more function. There are basically three major technological challenges, namely performance, precision, and perfection, and they all critically depend on mask-making capabilities.
Efficient performance referred as perf/Watt, is the most important figure of merit for chips made today. We define performance in terms of giga floating-point operations per second. It is proportional to the product of transistor count and circuit speed. Figure 2 shows the continuous increase of chip performance as technology advances.1
Under power constraints, most performance improvement comes from doubling the transistor density based on Moore's law.2 This is done with ever-shrinking design rules that have been achieved by replicating finer lines and spaces through higher resolution masks. Meanwhile, the amount of data and hardware needed for making masks has increased tremendously. Not only are we challenged to print smaller geometries but to print more of them all the time.
Precision in dimension and placement is another challenge that we are facing. Every nanometer counts because our transistors will be approaching 20nm in length. At that size, their electrical behavior changes significantly for just 1nm variation. If a 20nm-long transistor becomes 21nm, it can lose 5% in speed when it's ON, but if it becomes 19nm, it can leak 2x more current when it's OFF. Designers today can purposely bias the length of the transistor by a couple of nanometers to create another type of transistor for either higher speed or low leakage. However, if the critical dimension control cannot be handled precisely, the two types of transistors can hardly be distinguished.
Figure 2. Scaling graphics processing unit performance (perf) with technology where perf is number of giga floating point operations per second.
The placement of the geometries is more critical today than ever because of the narrower spaces between the features in the same masking layer and in the adjacent masking layers. Figure 3 shows the narrow spacing between a via 1 (V1) at the end of a metal 1 (M1) line and an adjacent M1 that must be precisely controlled to allow sufficient space. (Otherwise, a short may occur.) Even with a space, if it's too narrow, it may lead to dielectric breakdown over time. A short kills yield, and an almost-short is even worse because it manifests itself as a time-dependent dielectric breakdown related to reliability problems.3
Figure 3. (a) Layout and (b) scanning electron microscope cross-section showing the precision control of the narrow space between via 1 (V1) and metal 1 (M1). V1 is the via connecting M1 to M2 (metal 2).
We define perfection as the degree of flawlessness. Imperfection is quantified as defective parts per million or billion (DPPM or DPPB). For a chip with billions of contacts or vias, one must have the corresponding defect at less than 1 DPPB, near perfection. Even though designers apply DFM, such as redundant vias and rectangular vias, to mitigate the problem, a large number of single minimum-size, worst-case vias in the range of a few hundred million are often left on the chip to keep a reasonably competitive die size. Using the example in Figure 3 with some typical numbers for illustration purposes, we can see how much precision and perfection are required.
Figure 4. Chip failure rate in defective parts per million vs. nth via (VIAn)-nth metal (Mn) misalignment standard deviation (σ) in nm for a chip with a 100M worst-case vias made by 20nm technology.
With 100 million worst-case vias on a 20nm chip, if 10nm is the minimum spacing required to guarantee product lifetime reliability, chip failure would be about 240 DPPM if the standard deviations (σ's) of nth via (VIAn) and nth metal (Mn) layer critical dimensions (CDs) are controlled at 2.0nm and 1.4nm, respectively, and the VIAn-to-Mn alignment σ is as tight as 2.3nm. Sensitivity analyses show that a sub-nm difference in the σ of the Mn CD, VIAn CD, or misalignment distribution can alter the product lifetime drastically. Figure 4 shows that just one tenth of a nanometer less in this critical overly control would increase the chip failure rate by as much as an order of magnitude. As the number of vias increases further, the precision requirement is more stringent, and the defect level needs to be zero or almost zero.
As an end user of these products, I admire what lithography experts and mask makers have accomplished so far. Looking into the challenges ahead, considering nanometer resolution, complicated patterns, and huge numbers of geometries, I must underscore the need for performance, precision, and perfection to advance Moore's law for many generations to come.
Santa Clara, CA
John Chen is vice president of technology. He was previously vice president for R&D and E-Beam Mask Making at TSMC. Earlier, he worked on e-beam lithography and CMOS and published 100 papers and a book on CMOS. He received a PhD in electrical engineering from the University of California at Los Angeles.
1. J. Y. Chen, GPU Technology Trends and Future Requirements, Int'l. Electron Devices Meeting Paper 1.1, Baltimore, MD, 2009.
2. G. Moore, Cramming more components onto integrated circuits, Electronics 38(8), April 1965.
3. W. Liu, Y. K. Lim, J. B. Tan, W. Y. Zhang, H. Liu, S. Y. Siah, Study of TDDB Reliability in Misaligned Via Chain Structures, Int'l. Reliability Physics Symp. Paper 3A.4.1, Anaheim, CA, 2012.