A high-performance planar organic thin-film transistor

Recently, pentacene-based organic thin-film transistors (OTFTs) have attracted great interest because of their potential advantages for low-cost and/or flexible electronic devices such as smart cards, radio-frequency identification (RFID) tags, and mobile phone displays, including active-matrix organic LEDs (AMOLEDs).¹ These are low power and low cost, but require a high pixel aperture ratio (the ratio between the transparent area and the whole pixel area) for a bright, high-quality output. This necessitates an array of small OTFTs.

An OTFT with a conventional bottom-contact (cBC) structure, where the organic semiconductor layer is deposited on the source/drain (S/D) electrodes and the gate insulator, uses lithography to define the S/D and channel regions before the pentacene semiconductor layer is deposited and the channel length can be shrunk to <5μm:² see Figure 1(a). Moreover, the channel dimension of the cBC-structured OTFT device can easily be scaled down, making it suitable for high-aperture-ratio AMOLEDs.^{3, 4}

However, the thickness of the S/D electrodes causes a step change in height along the edge of the gate insulator, resulting in discontinuous growth of the pentacene semiconductor layer near the edge of the S/D regions:⁵ see Figure 1(b). This discontinuity impedes carrier injection, resulting in increased contact resistance and impaired electrical characteristics.⁵ We have removed the step caused by the S/D electrodes by embedding them in the gate insulator: see Figure 1(c).

Figure 1. (a) Cross section of the conventional bottom-contact (cBC) structure and (b) atomic force microscopy image for the cBC structure. (c) Cross section of the embedded source/drain (S/D) structure and (d) atomic force microscopy image of the embedded S/D.

Figure 2. Transfer curves of the organic thin-film transistors (OTFTs) with continuous pentacene film (red solid line) and with discontinuity (black dash line). W: Channel width of OTFTs. L: Channel length of OTFTs.

To control this planarization process, we have proposed a new scheme for selectively etching the gate insulator. Selectivity must be high enough to etch the precise pit depth to embed the electrodes. Moreover, we do not immediately remove the etching mask (the photoresist) that defines the S/D electrodes after etching. We keep this as a ‘self-aligned’ deposition mask for S/D metal deposition, and then remove it (by lift-off) to pattern the S/D region until metal deposition is complete.

In this way, the pentacene semiconductor layer near the edge of the S/D regions is deposited as a continuous plane: see Figure 1(d). This planarity in turn enhances carrier injection and reduces contact resistance for better electrical performance of the OTFT device.⁶ The OTFT transfer curves (see Figure 2) clearly show that the on current increases by almost an order of magnitude when the pentacene film is continuous, and the extracted field-effect mobility increases from 2.7×10⁻³cm²/V·sec to 5.9×10⁻²cm²/V·sec.

In summary, we have fabricated a high-performance OTFT with a submicron BC structure that has the source and drain electrodes embedded in the gate insulator. OTFTs with such small geometry can integrate the driver and pixel circuits for high-resolution, flexible AMOLED display screens and other low-cost and/or flexible electronic devices, such as smart cards and RFID tags. We are now working to realize practical applications of this and other improvements^{7, 8} we have proposed for bottom-contact OTFTs.