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Optoelectronics & Communications

Flexible wireless transceivers

Advanced digital-dominant circuitry techniques enable low-power, programmable, and efficient wireless devices that can adapt to modern communication standards.
17 May 2011, SPIE Newsroom. DOI: 10.1117/2.1201104.003707

Present-day electronic devices, such as cell phones and wireless sensor nodes, integrate several transceivers to support the various types of wireless communication. Examples of current wireless communication standards include Wi-Fi, ZigBee (used in sensor networks), and GSM (global system for mobile communications). The need to support several of these platforms increases the design complexity of wireless transceiver circuits and increases the size, cost, and power consumption of the electronic gadgets that use them. At the same time, advances in circuit-fabrication technology favor digital rather than analog components and make the latter more difficult to design. Therefore, next-generation wireless transceivers should implement circuit operations that are more digital and must be sufficiently configurable to support many standards.

Most transceiver designs are based on the superheterodyne technique, a method pioneered by Edwin Armstrong in the 1920s that efficiently picks out a wanted wireless signal. In contrast, recently proposed schemes are more configurable and inherently more digital. For example, a high-frequency sampling receiver1,2 and a frequency-mixing and sampling receiver3 demonstrated performance that meets the requirements of prevalent communication standards. Still, these systems can be further improved by optimizing across the entire architecture. Wireless transmitters tend to be power hungry, and the use of analog components makes them less suited for integration in modern digital processes. Many of the transmitters reported in the literature,4 which are based on digital rather than analog circuits, are inferior in performance to their analog counterparts and suffer from problems such as the generation of spurious tones.

We have developed a low-power, digital-dominant phase-locked-loop (PLL) based transmitter.5 (A PLL is a circuit that can take a reference-clock signal with a certain frequency and generate an output with a different frequency.) We have also developed a flexible receiver6 with configurable filtering that is embedded in a successive approximation register (SAR) analog-to-digital converter (ADC). Such a device employs an iterative approach to determine a digital value to represent an analog signal. The configurable filter allows the receiver to easily tune to different types of wireless signals. Both transmitter and receiver achieve comparable performance to analog counterparts.

The architecture of our devices simplifies analog circuits and shifts much of the functionality to digital ones. In addition, our proposed scheme alleviates some shortcomings associated with traditional digital PLL-based transmitters. A significant challenge in the design of a receiver is the filtering of unwanted interfering signals, which is traditionally implemented with analog circuits or off-chip discrete filters. A flexible but energy-intensive alternative is to make a digital representation of the wireless spectrum with a fast, high-resolution ADC and perform filtering with digital-signal-processing (DSP) techniques. As an energy-efficient alternative, we introduce a flexible receiver that embeds a configurable discrete-time (DT) filter within the ADC. Such a filter combines samples of a signal from different times to block out some frequency bands and allow wanted frequencies to pass through. Furthermore, a wideband, inductor-less front-end ensures compatibility with a wide range of carrier frequencies.

Figure 1 shows the block diagram of a low-power digitally dominant PLL-based transmitter. This device is well-suited to integration in nanometer complimentary-metal-oxide-semiconductor (CMOS) processes that are commonly used to construct integrated circuits. Phase or frequency modulation can be achieved with a PLL by adjusting the feedback divider ratio. The PLL architecture is ‘fractional-N,’ meaning that it enables non-integer divide ratios permitting small changes in output frequency or phase. The transmitter is comprised of a mostly-digital fractional-N PLL modulator and a simple power amplifier. A digital phase detector compares the reference clock and the divided-down voltage-controlled-oscillator (VCO) output. In this design, the phase detector is formed with a 1-bit over-sampled phase quantizer, thus reducing the risk of spurious tones. A digital low-pass filter averages the phase detector output and sets the VCO control voltage. The filter's output is converted to the analog domain by a resistor string digital-to-analog converter (DAC) that uses ΣΔ modulation (a method for encoding high-resolution signals into lower-resolution ones). Two control paths, incorporating two DACs and a digital sampler, enable frequency modulation at a high rate. A simple power amplifier delivers power to the transmit antenna.

Figure 1. Block diagram of our digital phase-locked-loop-based transmitter. PD: Phase detector. LPF: Low-pass filter. ΣΔ: Sigma-delta modulator. DAC: Digital-to-analog converter. VCO: Voltage-controlled oscillator. PA: Power amplifier.

In our receiver,6 a wideband front-end converts the radio-frequency signal to baseband, where it is amplified before digitization and filtering by a SAR ADC. A traditional SAR ADC consists of a capacitive DAC that performs the successive approximation register process. The innovation here is to use the same capacitors to implement both filtering and digitization. Both the DAC and the analog DT filter use unit capacitors and switches. Hence, we implement a DT pre-filter by modifying the ADC sampling process. Since the switches are programmable, the filter configuration is flexible and can be tailored to different wireless communication standards. Figure 2 shows a photo of the fabricated receiver die.

Figure 2. Die photo of the configurable wideband receiver.

This new architecture supports many communication standards and bands. By configuring the DT filter with different sampling rates and filter parameters in the receiver, we have demonstrated standard-compliant reception of the 915MHz and 2450MHz bands of IEEE (Institute of Electrical and Electronics Engineers) 802.15.4 packets. We have also verified successful reception of IEEE 802.11 (Wi-Fi) packets.

As modern devices integrate increasingly more wireless connectivity into a single chip, traditional architectures have to be abandoned in favor of digital-dominant approaches. Our receiver and transmitter achieve good performance by employing a design strategy that shifts analog complexity to mixed-signal and digital circuits that perform well in advanced nanoscale integrated-circuit technologies. We foresee next-generation wireless transceivers as intelligent systems that constantly adjust gain, filtering, ADC conversion rate, and other parameters in real-time, to optimize both energy use and performance. The continuing development of such flexible and energy-efficient transmitters and receivers represents the focus of our future work.

Michael Flynn, David Lin, Mohammad Ghahramani, Li Li
University of Michigan
Ann Arbor, MI 

Michael Flynn received his PhD from Carnegie Mellon University in 1995 and joined the University of Michigan in 2001. He received the National Science Foundation Early Career Award in 2004, a Guggenheim fellowship in 2008, and the Education Excellence Award from the University of Michigan in 2011.

1. R. B. Staszewski, K. Muhammad, D. Leipold, C.-M. Hung, Y.-C. Ho, J. L. Wallberg, C. Fern, All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS, IEEE J. Solid-State Circuits 39, pp. 2278-2291, 2004. doi:10.1109/JSSC.2004.836345
2. K. Muhammad, Y.-C. Ho, T. L. Mayhugh, C.-M. Hung, T. Jung, I. Elahi, C. Lin, The first fully integrated quad-band GSM/GPRS receiver in a 90-nm digital CMOS process, IEEE J. Solid-State Circuits 41, no. 8, pp. 1772-1783, 2006. doi:10.1109/JSSC.2006.877271
3. R. Bagheri, A. Mirzaei, S. Chehrazi, M. Heidari, M. Lee, M. Mikhemar, W. Tang, A. Abidi, An 800-MHz-6-GHz software-defined wireless receiver in 90-nm CMOS, IEEE J. Solid-State Circuits 41, no. 12, pp. 2860-2876, 2006. doi:10.1109/JSSC.2006.884835
4. L. Xu, S. Lindfors, K. Stadius, J. Ryynanen, A 2.4-GHz low-power all-digital phase-locked loop, IEEE J. Solid State Circuits 45, no. 8, pp. 1513-1521, 2010. doi:10.1109/JSSC.2010.2047453
5. M. A. Ferriss, M. P. Flynn, A 14 mW fractional-N PLL modulator with a digital phase detector and frequency switching scheme, IEEE J. Solid-State Circuits 43, no. 11, pp. 2464-2471, 2008. doi:10.1109/JSSC.2008.2005435
6. D. T. Lin, L. Li, S. Farahani, M. P. Flynn, A flexible 500MHz to 3.6GHz wireless receiver with configurable DT FIR and IIR filter embedded in a 7b 21MS/s SAR ADC, IEEE Custom Integrated Circuits Conf., pp. 1-4, 2010. doi:10.1109/CICC.2010.5617620