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Micro/Nano Lithography

Advances in nanostencil lithography

Shadow masks are used for patterning organic materials or structuring sub-micrometer features on flexible and non-planar substrates.
10 March 2011, SPIE Newsroom. DOI: 10.1117/2.1201102.003510

Smaller, denser features on silicon-based platforms, organic semiconductor circuits, flexible and transparent electronics, and bio-sensors are needed for higher functionality and cost efficiency.1,2 To achieve this, nanoscale patterning requires processing techniques that comply with novel organic materials as well as topographically-rich thermally-sensitive substrates. Traditionally, a uniform resist layer is spun and then patterned upon exposure to thermal treatment, radiation, and liquid solvents. The resist is then used as a shadow mask (stencil) to transfer the design onto the other material layers, with a thinner resist yielding higher resolution. Most organic semiconductors and flexible polymeric substrates cannot withstand the heat load and chemical interactions involved in these steps. Thus, patterning on the sub-micrometer scale for non-planar substrates remains a challenge.

While many serial processes—such as scanning probe microscopy3 and electron-beam lithography—can be adapted to a variety of substrates, successive patterning impedes cost efficiency. Though parallel techniques have been developed for silicon-based technologies, they are more rigid and present various drawbacks, such as intrinsic resolution limits (as in deep ultra-violet lithography) and failure on mechanically fragile substrates (as in nano-imprinting). Nanostencil lithography circumvents many of these problems by using micro-machined shadow masks with sub-micrometer apertures.

Shadow masks were first used by prehistoric people who placed their hands against cave walls and blew pulverized pigment around them. Modern stencils have evolved such that they enjoy use in many modes and applications, achieving sub-micrometer dimensions for nanotechnology. Full 100mm silicon wafers can be micro-machined to obtain dense arrays of low-stress silicon nitride (LS-SiN) membranes, each containing design-specific apertures through which the patterning is performed. The stencil is held to the substrate to allow deposition, etching, or ion implantation through its apertures (see video4).

Recently, we focused on improving the resolution and reliability of deposited patterns smaller than 100nm. Accurate aperture geometry transfer depends on the setup configuration and deposition parameters. Blurring can enlarge the transferred structure—the stencil-to-source gap, material type, aperture size, deposition rate, and substrate temperature all influence the severity of this problem.5 We improved resolution by reducing the gap and tuning the deposition parameters (see Figure 1).

Figure 1. Blurring for different metals.5 Scanning electron micrographs of different metals deposited through slope-stencils with differing slit width and stencil-to-source gap (G) size. Al: Aluminum. Au: Gold. Pt: Platinum. Ti: Titanium. Cr: Chromium. G0: Smallest Gap.

Another important factor for their continued use is the reusability of nanostencils. Because the apertures are fabricated using electron-beam lithography, a stencil needs to be reusable to be truly cost efficient. The material deposited on the apertures during evaporation gradually clogs the openings—normally reducing the active lifetime of the shadow mask. We demonstrated that stencils can be cleaned ex situ, using wet etching, without damaging the chemically inert LS-SiN membrane material.6 We are currently developing a self-cleaning stencil, which will eliminate clogging in situ by heating the membranes using embedded electrodes. This is of special interest for dynamic deposition, where the stencil can move relative to the substrate inside the deposition chamber—a process that favors material accretion on the membranes (see video7).8

Besides the standard benefits of static stenciling, dynamic stencil lithography adds the ability to structure variable-thickness, multi-material, and closed-contour patterns. The pattern's height can be varied by translating the stencil with various speeds while keeping the evaporation rate constant. A single stencil can include several layer designs, all to be fabricated in one cycle by moving the stencil to the correct position during deposition to a particular layer. Additionally, we demonstrated that arbitrary geometries can be built by allowing stencil arrays of round apertures to follow different trajectories (see Figure 2). The challenges that remain include having a small gap and preventing the material from clogging the apertures.

Figure 2. Parallel fabrication of multi-material surface ‘house’ structures made with dynamic stencil lithography.8 (a) The stencil design contains an array (19×19) of 2μm apertures spaced 50μm apart. (b) Sequential actuation patterns drawn along the trajectory indicated by arrows, at a speed of 2 μm/s. (c) Scanning electron microscopy (SEM) image of the parallel micropatterns fabricated using the array of apertures shown in (a), moving along the trajectory shown in (b), with gold (Au) deposited along path 1 and silver (Ag) along path 2. (d) Detailed SEM image of the Au/Ag houses.

In parallel with pushing the limits of nanostenciling, we have explored deposition in a variety of projects. For example, we fabricated flexible, thin-film organic transistors with channel dimensions of 10×3μm2 using stencil-deposited pentacene as the organic semiconductor. All subsequently aligned lithographical steps were also patterned by stencils (see Figure 3).9 We also made superconducting tunnel junctions in situ by angle deposition over a stencil bridge with an intermediate oxidation step.10 We patterned and electrically characterized metallic nanowires at full wafer scale11,12 and applied the stencil for gate-patterning.13 We also performed etching through a stencil, where we structured various substrates such as polycrystalline silicon, LS-SiN, polyimide, poly(methyl methacrylate), and an assembly of 100nm latex nanoparticles using reactive-ion etching through a stencil mask.14,15 Additionally, using a carbon ion beam (500keV and 5mm in size), the profile of a topologically-complex stencil membrane was etched into a polymer substrate.16

Figure 3. (a) Full-wafer stencil used for the fabrication of (b) thin film organic transistors on a flexible polyimide substrate.9

In summary, nanostenciling provides particular advantages. We characterized its resolution in a large experimental parameter space, leading to recipes for optimal settings and found ways to prolong stencil lifetime. We exploited its non-invasiveness and unique capabilities for use on fragile and non-planar substrates as well as with organic materials. We are currently developing an advanced dynamic mode that will allow in situ, successive patterning of multiple materials and layers, opening the door to novel, more cost effective device fabrication.

This work was supported by the Swiss National Science Foundation Ambizione grant for young researchers (PZ00P21923).

Veronica Savu, Juergen Brugger
Swiss Federal Institute of Technology (EPFL)
Lausanne, Switzerland

Veronica Savu was awarded a three-year Ambizione grant from the Suisse National Science Foundation for young researchers. Her current interests include applications of stencil lithography, such as nanowire-based transistors, flexible and organic electronics, and novel device functionalities provided by dynamic nanostencils.

Juergen Brugger is an associate professor whose research combines methods of cleanroom technologies with emerging micro- and nanopatterning methods, such as scanning probes, stencil lithography, and inkjet printing for information technology and life science applications.

1. R. Chau, S. Datta, M. Doczy, B. Doyle, B. Jin, J. Kavalieros, A. Majumdar, M. Metz, M. Radosavljevic, Benchmarking nanotechnology for high-performance and low-power logic transistor applications, IEEE Trans. Nanotechnol. 4, pp. 153-158, 2005. doi:10.1109/TNANO.2004.842073
2. T. Sekitani, T. Someya, Stretchable, large-area organic electronic, Adv. Mater. 22, pp. 2228-2246, 2010. doi:10.1002/adma.200904054
3. A. W. Knoll, D. Pires, O. Coulembier, P. Dubois, J. L. Hedrick, J. Frommer, U. Duerig, Probe-based 3-D nanolithography using self-amplified depolymerization polymers, Adv. Mater. 22, pp. 3361-3365, 2010. doi:10.1002/adma.200904386
4. Video shows patterning through a stencil, first via material deposition, then during ion etching. Credit: Guillermo Villanueva, California Institute of Technology. http://spie.org/documents/newsroom/videos/3510/StLitho.avi
5. O. Vazquez-Mena, L. G. Villanueva, V. Savu, K. Sidler, P. Langlet, J. Brugger, Analysis of the blurring in stencil lithography, Nanotechnol. 20, pp. 415303-415312, 2009. doi:10.1088/0957-4484/20/41/415303
6. O. Vazquez-Mena, G. Villanueva, M. A. F. van den Boogaart, V. Savu, J. Brugger, Reusability of nanostencils for the patterning of aluminum nanostructures by selective wet etching, Microelectron. Eng. 85, pp. 1237-1240, 2008. doi:10.1016/j.mee.2007.12.083
7. Video shows dynamic stencil lithography. Various patterns can be ‘written’ as the stencil moves during material deposition with a single membrane aperture. http://spie.org/documents/newsroom/videos/3510/DynSt.avi
8. V. Savu, M. A. F. van den Boogaart, J. Brugger, J. Arcamone, M. Sansa, F. Perez-Murano, Dynamic stencil lithography on full wafer scale, J. Vac. Sci. Technol., B 26, pp. 2054-2058, 2008. doi:10.1116/1.2987953
9. K. Sidler, N. V. Cvetkovic, V. Savu, D. Tsamados, A. M. Ionescu, J. Brugger, Organic thin film transistors on flexible polyimide substrates fabricated by full wafer stencil lithography, Procedia Chem. 1, pp. 762-765, 2009. doi:10.1016/j.proche.2009.07.190
10. V. Savu, J. Kivioja, J. Ahopelto, J. Brugger, Quick and clean: stencil lithography for wafer-scale fabrication of superconducting tunnel junctions, IEEE Trans. Appl. Supercond. 19, pp. 242-244, 2009. doi:10.1109/TASC.2009.2019075
11. V. Savu, S. Neuser, G. Villanueva, O. Vazquez-Mena, K. Sidler, J. Brugger, Stenciled conducting bismuth nanowires, J. Vac. Sci. Technol., B 28, pp. 169-172, 2010. doi:10.1116/1.3292630
12. O. Vazquez-Mena, G. Villanueva, V. Savu, K. Sidler, M. A. F. van den Boogaart, J. Brugger, Metallic nanowires by full wafer stencil lithography, Nano Lett. 8, pp. 3675-3682, 2008. doi:10.1021/nl801778t
13. D. Sacchetto, V. Savu, G. De Michelli, J. Brugger, Y. Leblebici, Ambipolar silicon nanowire FETs with stenciled-deposited metal gate, Microelectron. Eng., (in press), 2010. doi:10.1016/j.mee.2010.12.117
14. G. Villanueva, O. Vazquez-Mena, M. A. F. van den Boogaart, K. Sidler, K. Pataky, V. Savu, J. Brugger, Etching of sub-micrometer structures through stencil, Microelectron. Eng. 85, pp. 1010-1014, 2008. doi:10.1016/j.mee.2007.12.068
15. B. Viallet, J. Grisolia, L. Ressier, M. A. F. van den Boogaart, J. Brugger, T. Lebraud, Stencil-assisted reactive ion etching for micro and nano patterning, Microelectron. Eng. 85, pp. 1705-1708, 2008. doi:10.1016/j.mee.2008.04.027
16. P. Weber, E. Guibert, S. Mikhailov, J. Brugger, L. G. Villanueva, Ion beam etching: replication of micro nano-structured 3D stencil masks, Application of Accelerators in Research and Industry, 1099, pp. 539-541, Springer, 2009.