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Micro/Nano Lithography

Printing semiconductor arrays onto arbitrary substrates

A fracture-transfer-print technique enables integration of multilayer semiconductor devices for efficient portable electronics applications.
22 November 2010, SPIE Newsroom. DOI: 10.1117/2.1201010.003353

Heterogeneous integration of multiple, single-crystal semiconductor devices with different physical, electrical, and optical characteristics on amorphous substrates is important for highly efficient portable and flexible electronics, optoelectronics, and energy-conversion devices. Several techniques, including wafer bonding, epitaxial liftoff, and heteroepitaxy,1 have been developed to address those needs. These methods allow for some high-performance devices. But they introduce issues that inhibit mass-manufacturing techniques to grow and integrate a variety of materials and devices on a host of surfaces/substrates, for example, CMOS-process incompatibilities from high growth temperature, high substrate cost, lack of substrate flexibility, interface defects, and traps caused by materials mismatches.

One approach to the challenges of integrating multifunctional materials is fabricating high-quality, single-crystal vertically oriented one-dimensional (1D) micro- or nano-scale pillars/wires of semiconductor materials by either direct growth2–4 on the final device substrates or by harvesting them to a low-cost, flexible carrier substrate.5,6 Such substrates can have advantageous properties such as flexibility, light weight, biocompatibility, low cost, and optical transparency. Plastic-based carrier substrates are not compatible for directly growing high-quality inorganic semiconductors using conventional microfabrication processes due to their low melting temperature of <220°C. Hence, high-temperature, compatible materials like refractory metal foils3 and quartz substrates are used. For plastic substrates, alternative transfer methods such as wet transfer,5 dry transfer,6 and contact printing7,8 have been pursued. Existing transfer methods either do not preserve the vertical orientation of the nanopillar/wire array on the carrier substrate (thus limiting the device to an equivalent 2D, single-crystal-film transfer) or are yet to be shown to be viable for vertical-process integration.

We recently demonstrated a technique to harvest and transfer vertically aligned, single-crystal semiconductor micro- and nano-pillars from a single-crystal (mother) substrate to a low-cost carrier substrate while simultaneously preserving the integrity, order, shape, and fidelity of the transferred pillar arrays.9 The transfer technique is based on a vertical embossing and lateral fracturing method using a transfer polymer. We achieved ohmic contact formation for electrical addressing using a composite of metals and a conducting polymer (see Figure 1). Highly crystalline nanowires fabricated by a bottom-up method and micro/nano-pillars fabricated by a transformative top-down method with diverse bandgaps and physical properties can be fabricated on appropriate mother substrates and transferred to form multilayered 3D stacks for multifunctional devices.

Figure 1. Fracture-transfer technique: (a) Micro/nano-pillars are embedded into the transfer polymer. Si: silicon. PMMA: polymethylmethacrylate. PAni: polyaniline. (b) Both substrates are moved relative to each other in opposing directions to successfully transfer from the mother to the carrier substrate through bending fracture. (c) Transferred pillars embedded in a polymer coated-carrier substrate.

We demonstrated the capability of this process by fabricating 25mm2 silicon photoconducting devices on a glass and polymer surface. A low fill factor contributed to lower leakage current, reduced parasitic capacitance, and higher efficiency of light absorption (see Figure 2). Our approach offers a more generic method where the ordered array of the 3D micro/nano-structures is preserved in their vertical orientation (direct 3D-to-3D) after transfer while increasing the final device's volume density. We are not restricted by any starting mother or carrier substrates (such as silicon-on-insulator) as required by other methods that involve ambient and/or low-temperature processes (<250°C). The choice of off-the-shelf transfer polymers (mainly insulating polymers) is not limited to polydimethylsiloxane (PDMS), polymethylmethacrylate (PMMA), polyimide, polystyrene, polycarbonate or SU-8 (a negative, epoxy-type, near-UV photoresist).

Figure 2. Vertically transferred, aligned silicon-micropillar array from a mother substrate into a polymethylmethacrylate polymer spin-coated on a glass-carrier substrate. Boxes (a) to (c) are tilted views of the transferred array with varying magnifications. The red box and arrow in (a) is the area replicated and enlarged in (b).

Our approach offers several important features. Low-temperature device fabrication with highly crystalline materials reduces the impact of thermal expansion and shrinkage, and it becomes critical when devices are fabricated on plastics, sheet metal, and other low-cost substrates and in a multilayer-stack with different semiconductors. Lower leakage current and reduced parasitic capacitance are demonstrated, which is potentially contributed from the low-fill factor. Effective photon-trapping and absorption leads to higher efficiency. Reusability of an expensive substrate for repeated reproduction of 1D pillars contributes to significantly reduced material consumption. We are working towards enhancing and optimizing these features, in particular the reduction of contact resistance of the transferred pillars. This capability will offer a universal platform for material integration and enable new 3D heterogeneously integrated device manufacturing for energy conversion, data storage, tactile sensing, imaging, solid-state lighting, displays, and silicon photonics.

The authors would like to thank Nibir Dhar of the US Defense Advanced Research Projects Agency's Microsystems Technology Office for the helpful suggestions on the micro/nano-pillar design and experimental methods. This work was supported in part by a University of California Davis research grant, by Army Research Office grant 55176-ELDRP and by National Science Foundation grant 0547679.

V. J. Logeeswaran
University of California, Davis
Davis, CA

V. J. Logeeswaran received his BEng and MEng degrees in mechanical engineering from the National University of Singapore in 1997 and 2001, respectively, and his PhD degree in electrical and computer engineering from UC Davis in 2010. He is currently a postdoctoral researcher with the UC Davis Department of Electrical and Computer Engineering (ECE).

Aaron M. Katzenmeyer, M. Saif Islam
Electrical & Computer Engineering, UC Davis
Davis, CA

Aaron M. Katzenmeyer received his BS in electrical engineering from Ohio University in 2005, the Erasmus Mundus Master of Nanoscience and Nanotechnology program in 2007 from the Delft University of Technology, The Netherlands, and the Katholieke Universiteit Leuven, Belgium. Since 2007 he has been working toward his PhD at the UC Davis ECE focused on nanowires.

M. Saif Islam received his BSc in physics from the Middle East Technical University, Ankara, Turkey, in 1994; his MSc in physics from Bilkent University, Ankara, in 1996; and his PhD in electrical engineering from the University of California Los Angeles in 2001. He was with Hewlett-Packard Laboratories and Optical Network Research Laboratory of SDL Inc./JDS Uniphase Corporation before joining UC Davis in 2004, where he is currently an associate professor with the ECE. He received a National Science Foundation Faculty Early Career Development Award in 2006, a College of Engineering Outstanding Junior Faculty Award in 2006, an IEEE Professor of the Year Award (in 2005 and 2009), and a UC Davis Academic Senate Distinguished Teaching Award in 2010.