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Carbon nanotubes for next-generation interconnects
Multi-walled carbon nanotubes and single-walled carbon-nanotube bundles can replace copper interconnection wires in very-large-scale integration circuits.
17 January 2011, SPIE Newsroom. DOI: 10.1117/2.1201012.003220
Nanometer CMOS technology, especially at 22nm and below, is plagued by performance degradation of conventional copper (Cu)/low-dielectric-constant (k) dielectrics, which are used as interconnects for gigascale integration. Koo and coworkers1mentioned the effect of scaling on surface and grain-boundary scattering and electromigration in Cu interconnects,2detailing the degradation of parameters such as latency and power dissipation. A subsequent need for materials to possibly replace Cu/low-k dielectric interconnections has brought forward development of novel technologies for next-generation very-large-scale integration (VLSI) circuit interconnects. Optical interconnects have been suggested for on-chip integration3–5 but face serious integration problems. Although optical interconnects are still being investigated because of their inherent advantages over Cu, other new technologies such as capacitively driven low-swing interconnects have also evolved.1 Carbon nanotubes (CNTs) and graphene nanoribbons have emerged as promising candidates for next-generation VLSI interconnects.6–13 In the search for novel interconnect technologies, no material has aroused as much interest as carbon nanomaterials since the discovery of the CNT in 1991.14
The excellent electrical, mechanical, and thermal properties15,16 of 1D CNTs have made them one of the most promising materials for applications in nano-electronics6,7,10,17 and micro/nanosystems.18 CNTs have a current density of ∼1010A/cm2, which is two to three orders of magnitude higher than Cu. Their mean free path is in the micrometer range, compared to ∼40nm for Cu. This large mean free path allows ballistic transport of electrons over a longer distance, resulting in reduced resistivity, while strong atomic bonds19 provide tolerance to electromigration.1,9 Meanwhile, higher thermal conductivity compared to Cu makes CNTs suitable for use as tall vias in 3D integrated circuits.13,20,21
Figure 1.Geometry of a single-walled carbon nanotube (SWCNT). r, l: Cylinder radius, length. S′: Shell.
We recently22,23 modified the 2D fluid model of CNTs to include electron-electron repulsive interaction and built a semi-classical 1D fluid model. In this model, a metallic single-walled CNT (SWCNT) is represented by a transmission-line model. The SWCNT is regarded as a single-atom-thick graphene sheet rolled to form a tube (see Figure 1). The cylinder's axis is oriented along the zaxis of the reference system. The conduction electrons are distributed on the lateral surface of the cylindrical shell. In addition to its accuracy, the 1D fluid model is mathematically simple and easy to extend to electronic-transport modeling of multi-walled CNTs (MWCNTs) and SWCNT bundles as interconnections. We used our fluid model to calculate each parameter in the distributed resistor-inductor-capacitor circuit models for SWCNT, MWCNT, and SWCNT-bundle interconnects.23,24
We also obtained an analytical solution for current transport (static model) in CNT field-effect transistors (FETs)25 and a dynamic model26 for analysis and design of CNT-FET-based integrated circuits. Figure 2 shows the CNT-FET inverter pair. The interconnect can be a Cu wire, MWCNT, or SWCNT bundle.
Figure 2.Inverter pair with interconnect. Each inverter has n- and p-type carbon nanotube (CNT) field-effect transistors (FETs). Vin, Vout: Input, output voltage. VDD, VSS: Positive, negative power-supply voltage.
Figure 3 shows the transient response of a CNT-FET inverter pair connected with 10μm-long MWCNT and SWCNT-bundle interconnects. It also shows a comparison of the transient response for an ideal interconnect (assuming direct connection) and a Cu interconnection wire. The propagation delays of MWCNT interconnects (β=1 and 1/3) are close to an ideal interconnect and smaller than SWCNT-bundle and Cu connections. Here, β is the ratio of the metallic to total number of shells in a MWCNT or the metallic to total number of SWCNTs in a SWCNT bundle. Compared to MWCNTs, the resistance of SWCNT-bundle interconnects is smaller, but their capacitance is much larger. As a result, the propagation delay of MWCNTs is smaller than that of SWCNT bundles. The propagation delays are smaller for β=1 than for β=1/3 for both MWCNT and SWCNT-bundle interconnects, because there are more interconnect channels when β increases.
Figure 3.Output waveforms of a CNT-FET inverter pair with copper (Cu), multi-walled CNT (MWCNT), and SWCNT-bundle interconnects of 10μm length. β: Ratio of metallic to total number of shells in MWCNT or metallic to total number of SWCNTs in SWCNT bundle.
We have used process parameters for the 22nm-technology node27 to simulate interconnect delays for different lengths of Cu wire, MWCNT, and SWCNT-bundle interconnects corresponding to ballistic-transport, local-, and global-interconnect lengths (see Figure 4). The increase in delay for Cu interconnects is larger than that for MWCNT and SWCNT-bundle interconnects. The delays of MWCNT interconnects are smaller than those of SWCNT-bundle and Cu interconnects. The delays are smaller for both MWCNT and SWCNT-bundle interconnects for β=1. For β=1/3, MWCNT interconnects show an increase in delay, but it is still lower than for SWCNT-bundle interconnects.
Figure 4.Propagation delays of interconnects of different lengths for 22nm technology.
Power dissipation is another challenge. We simulated power dissipation for MWCNT and SWCNT-bundle interconnects at the 22nm-technology node and compared it with Cu-wire interconnects. Table 1 summarizes the power-dissipation ratio of MWCNT and SWCNT-bundle (β=1/3 and 1) interconnects with respect to a Cu interconnect. CNT interconnects dissipate less power, especially for local interconnections. Maximum power dissipation in CNT interconnects is no more than the 8% of Cu interconnects.
Table 1.Power dissipation of CNT interconnects.
|Type of CNT||Normalized power dissipation (%)|
|SWCNT bundle (β=1)||0.011||0.015||0.079||0.137|
|SWCNT bundle (β=1/3)||0.036||0.047||0.256||0.688|
In summary, the 1D fluid model can be applied to CNT interconnects using low-resistance contacts in current low-voltage nanometer CMOS technologies. We theoretically explored the applicability of MWCNTs and SWCNT bundles as interconnect wires for next-generation integrated circuits and compared it with Cu interconnects at the 22nm-technology node. Our study shows that MWCNT and SWCNT-bundle interconnects perform better than Cu interconnects. CNT interconnects exhibit smaller delays and less power dissipation. Our study of scattering parameters23 using two-port network analysis shows that MWCNT and SWCNT-bundle interconnects exhibit higher transmission efficiencies, lower reflection losses, smaller delays, and less power dissipation. This is mainly caused by larger conductivity of MWCNTs and SWCNT bundles, which is proportional to both the number of conducting shells in a MWCNT and the number of conducting SWCNTs in a SWCNT bundle. The delays in MWCNT and SWCNT-bundle interconnects can be further decreased as β increases and approaches unity. With an increase in length, the delay of Cu interconnects increases faster than that of MWCNT and SWCNT-bundle interconnects. These findings suggest that MWCNTs and SWCNT bundles can replace Cu as interconnection wires in next-generation VLSI integrated circuits. This represents part of our future research efforts.
Part of this work is supported by the US Air Force Research Laboratory (AFRL) under agreement FA9453-10-1-0002. The US Government is authorized to reproduce and distribute reprints for Government purposes notwithstanding any copyright notation thereon. Authors thankfully acknowledge Clay Mayberry (US AFRL) for encouragement and support.
Ashok Srivastava, Yao Xu
Department of Electrical and Computer Engineering, Lousiana State University
Ashok Srivastava is a professor whose current research interests include low-power VLSI circuit design and testability (digital, analog, and mixed-signal), nano-electronics, and noise in devices and integrated circuits.
Yao Xu received his BS and MS degrees in photo-electronics from Tsinghua University (China) and the Chinese Academy of Sciences, respectively, and his MS in electrical engineering from Louisiana State University. His current research interests include nano-electronics (quantum-electronic devices, CNT interconnects, CNT-FETs, and integrated circuits), and low-power VLSI circuit design.
Electronics Foundations Group, US Air Force Research Laboratory/Space Electronics and Protection Branch (VSSE)
Kirtland Air Force Base
Ashwani Sharma received his BS, MS, and PhD in electrical engineering from the University of New Mexico. His research interests include physics of nanostructures, nanoscale semiconductor-device fabrication techniques, and nanodevices for high-speed and low-power-consumption electronic/opto-electronic applications. He also holds an electrical-engineering research-faculty position at the University of New Mexico.
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