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Electronic Imaging & Signal Processing

CMOS integration enables massively parallel single-photon detection

The next generation of single-photon image sensors offers performance comparable to that of their state-of-the-art counterparts implemented in dedicated technologies.
9 March 2011, SPIE Newsroom. DOI: 10.1117/2.1201102.003182

Solid-state, single-photon detectors have proved useful in many disciplines, including medicine, biology, robotics, safety, and security. The chief attraction of these devices is their amenability to time-resolved sensing, which has made possible such routine techniques as range finding, fluorescence lifetime imaging, and time-of-flight positron emission tomography. The most versatile and easy-to-use detectors are silicon avalanche photodiodes (APDs). A class of APDs known as single-photon avalanche diodes (SPADs) is of particular interest, because the sensors can be integrated in planar-silicon processes in combination with conventional digital and analog circuitries. The first SPADs implemented in a planar technology emerged in the 1980s.1,2 More recently, CMOS3 integration has enabled ever smaller feature sizes, to the point where it is now possible to envision large imaging systems based on SPADs.

A SPAD is essentially a p-n junction biased above breakdown. In this biasing regime, the photodiode operates in Geiger mode, i.e., its optical gain is virtually infinite. On absorption in the junction, a photon generates an electron-hole (negative and positive charge-carrier) pair that may be multiplied by impact ionization, thus generating an avalanche current. The avalanche is subsequently quenched and amplified by an appropriate circuitry, enabling direct single-photon detection. Figure 1 shows a cross section of a SPAD and the circuitry used to perform passive quench and recharge. When a SPAD detects a photon, it generates a digital pulse that is converted to a voltage level by means of pulse-shaping circuitry (also shown). SPADs are characterized by their sensitivity, measured as photon-detection probability, and noise performance, measured as the rate of spurious pulses caused by thermal events or dark-count rate. Other parameters include timing jitter or detection uncertainty, after-pulsing probability, and dead time, i.e., the cycle time associated with each detection.

Figure 1. (left) Single-photon avalanche diode (SPAD) cross section in a conventional CMOS process, and (right) passive quench and recharge circuitries, as well as pulse shaping (right). VOP: Voltage at which the SPAD is biased. Mq: Quenching transistor biased at voltage BIAS to ensure proper operation. p, n: Positive, negative charge.

SPADs are dynamic devices. Unlike conventional diodes, they cannot hold a charge proportional to the overall photon count. Photopulses must be counted in situ or read outside the image sensor and counted externally. Because of their reaction speed and low timing uncertainty, SPADs are most appropriate for photon time-of-arrival (TOA) evaluation. However, even this operation must be performed on photon detection. To address the problem, we and others have adopted a number of architectures that take advantage of the low propagation delay or high level of miniaturization achievable in standard submicron and deep-submicron CMOS technologies.4

The available architectures are in-pixel, in-column, and on-chip counting or TOA evaluation. With in-pixel architectures, all operations are performed and saved locally. The stored value is read out later in random-access or sequential mode. In-column or cluster counting implies sharing of operations of all pixels on the column or the cluster. The result is stored in column-based memory and read out on a column-by-column basis. Sharing generally involves trade-offs between pixel use, column and cluster size, and detection bandwidth. In these cases, understanding application specifications is key to appropriate use of the available techniques. On-chip counting or TOA is essentially an extension of the in-column architecture, where the working cluster is the entire chip. Similar trade-offs apply.

Here, we describe a few designs based on these architectures, from on-chip to in-pixel styles. The first design demonstrating the feasibility of large SPAD arrays comprised a matrix of 32×32 pixels, each with an independent SPAD, a quenching mechanism, and pulse-shaping and column-access circuitry.5 The readout scheme was based on random access. All time-sensitive operations had to be performed off-chip, and an overall jitter as low as 70ps was measured on a pixel while the array was operating.6 The main drawback of this design is that only one pixel can be read out at any time, and photons falling outside that pixel are lost. Figure 2 shows a micrograph of the chip.

Figure 2. A 32×32 SPAD array with random-access readout. The chip was implemented in 0.8μm CMOS technology. Vp+: Negative voltage that ensures operation in Geiger mode.

To address the readout bottleneck, we devised two approaches. The first, event-driven readout, uses the column as a bus that is addressed every time a photon is detected. The address of the relevant row is sent to the bottom of the column, where the TOA is evaluated, either off-chip6–8 or on-chip.9 The second approach, known as latchless pipelined readout, treats the column as a timing-preserving delay line. Every photon triggers a pulse that is injected into the pipeline at a precise location corresponding to the physical place where the pixel is situated. The row information is thus encoded in the timing of the pulse arrival at the end of the pipeline. Accordingly, it can be sequentially reconstructed by a single time-to-digital converter (TDC), a sort of miniaturized high-speed chronometer, at the bottom of the column. The TDC will also detect the exact TOA of the photon within a predefined time window. The chip shown in Figure 3 is an example of the latchless pipelined architecture implemented in CMOS.10

Figure 3. Example of latchless pipelined readout implemented in 0.35μm CMOS technology. TOA: Time of arrival.

In the third approach, time discrimination, photon counting, and any additional functionality, including local storage, is performed on-pixel. The advantage of this approach is the massive parallelism that can be achieved, potentially improving the number of photons that can be detected and processed at the same time at reasonable power consumption. Many embodiments of this approach exist, depending on the level of complexity implemented on-pixel. The simplest, shown in Figure 4, demonstrates detection and storage of photons at the pixel level. One-bit counters were integrated to minimize pitch. To construct multilevel images, a high-frequency readout was put in place that was capable of reading an entire 1bit frame in 2.88μs.11 Recently, with the implementation of the first SPADs in 130nm CMOS technologies,12,13 it has been possible to integrate more functionality on-pixel. In the European project MEGAFRAME, for example, each pixel implements a complete picosecond-resolution TDC1,14,15 and a time-to-amplitude converter.16

Figure 4. Example of in-pixel processing (in this case simple storage). The chip was implemented in 0.35μm CMOS technology.

In summary, this research has shown that it is possible to achieve significant functionality together with single-photon detection capability in deep-submicron CMOS chips with performance comparable to that of state-of-the-art single-pixel detectors implemented in dedicated technologies. The applications are endless, from biomedicine to chemistry, and from engineering to entertainment. As next steps, we intend to experiment with greater miniaturization, larger formats (up to 1 megapixel), and more diverse as well as new applications

Edoardo Charbon
Technical University of Delft
Delft, The Netherlands

Edoardo Charbon received his BS from the Swiss Federal Institute of Technology in Zurich, an MS from the University of California at San Diego, and his PhD from the University of California at Berkeley, all in electrical engineering and computer science. He has worked with Cadente Design Systems and Canesta Inc. He has also been professor at the Swiss Federal Institute of Technology in Lausanne and the Technical University of Delft, where he currently holds the Chair of VLSI (very-large-scale integration) Design in the Faculty of Electrical Engineering, Computer Science, and Mathematics.

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