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Optoelectronics & Communications

Ultra-low-power silicon-photonic modulator with integrated CMOS driver

An electro-optic modulator operates at 5Gbit/s with a high extinction ratio and record-high energy efficiency.
21 July 2010, SPIE Newsroom. DOI: 10.1117/2.1201006.003005

Scaling of high-performance, many-core computing systems calls for radical approaches to provide ultra-energy-efficient and high-bandwidth-density interconnects at very low cost. Silicon (Si) photonics is a promising solution because of its low latency, high bandwidth, high density, and low power consumption. For photonic solutions to prevail in intra/interchip applications, the communications-link power consumption, including all electronic circuits, must be scaled down aggressively from ~10pJ/bit at present to ~100fJ/bit in the near future. This demands development of innovative optical devices and system architectures,1 as well as novel circuit design and integration.

A key component required for low-power, dense Si-photonic interconnects is a high-speed, compact modulator with a low drive voltage. In recent years, high-speed waveguide Si modulators have been developed using the plasma-dispersion effect (a relatively weak electro-optic effect), where the refractive index of Si is changed by injecting or removing free carriers. Microresonator structures have been used to take advantage of strong light confinement in the resonator for reduction of power consumption. Modulators based on a metal-oxide-semiconductor capacitor, a forward-biased p-i-n diode, or a reverse-biased pn junction have been demonstrated,2–4 but none achieved low power, drive voltage, and insertion loss simultaneously. The forward-biased p-i-n modulator3 requires a drive voltage of ~3.5V and a complex pre-emphasis driving signal to overcome the carrier-lifetime-induced bandwidth limit. A Si microdisk modulator (using a reverse-biased vertical pn junction) demonstrated low power consumption (85fJ/bit) but also required a voltage swing of 3.5V.4 However, none managed to incorporate driver circuits. To advance the technology for practical applications, we developed a ring modulator with reverse-biased pn-junction modulation to achieve both low capacitance and low drive voltage. We designed a low-power CMOS driver and integrated the modulator with driver circuits into a complete, functional electro-optic device.

To construct a low-power, reverse-biased ring modulator with low drive voltage, we maximized the effective-index change by optimizing the design of both the ring waveguide and the pn junction.5 Figure 1(a) shows that our waveguide has dimensions of 0.5×0.25μm2 (width × height) and a slab height of 50nm to enable very tight mode confinement, an asymmetric pn junction with 5×1017 and 1×1018/cm3 p- and n-doping concentrations, respectively, and a junction offset of 50nm to maximize the mode overlap with the depletion region for maximum index change. We also optimized the device structure to minimize the dynamic-switching power required. As a result, we obtained a compact ring modulator with high modulation bandwidth for 15Gb/s modulation, very small capacitance (~15fF), low voltage swing (2V), a high extinction ratio (~7dB), and low optical loss (~2dB in the ‘on’ state): see Figure 1(b).


Figure 1. (a) Cross-sectional diagram of the phase-modulation waveguide. Si: Silicon. p++, n++: Heavily doped p-, n-type Si. (b) Microring modulator (top view).

A simple inverter can be used to drive a small capacitive load, like in a carrier-depletion ring modulator. However, to achieve the required voltage swing, we cannot simply apply 2V to an inverter driver, since voltages higher than 1.2V in 90nm CMOS (or higher than 1V in 40nm CMOS) technology will overstress and degrade transistors. Therefore, we used a cascade-driver-circuit architecture in which the 1V digital input was replicated into two versions that were shifted in voltage. These inputs drive inverters with different voltage references, which in turn drive the rails of a final driver (see Figure 2). The driver chip was fabricated using TSMCSM 90nm CMOS technology.

Low-power operation requires integration of Si-photonic devices and very-large-scale integration (VLSI) circuits with minimized electrical parasitics, where monolithic integration is preferred. However, state-of-the-art CMOS circuits and photonic devices normally require different substrates. To allow best-of-the-breed performance for both photonic devices and VLSI circuits, we used a low-parasitic microsolder bonding technique.1 We first added under-bump metallization to the bonding pads to both chips using electroless plating, and subsequently added low-profile and small-footprint microsolder bumps to the pads on the modulator chip with a few micrometers of vertical compliance. The two post-processed chips were then flip-chip bonded together by thermocompression. The microsolder connections had <1Ω resistance, while the parasitic capacitance due to bonding pads and microsolder bumps was <20fF.

We die attached and wire bonded the hybrid integrated modulator to a test printed-circuit board for power, control, and high-speed digital input/output connections (see Figure 2). The modulator chip was closely contacted with a copper heat sink to passively maintain the ring modulator's stability. We achieved a bit-error rate of <10−13 for 5Gbit/s operation with a record-low total power consumption of 1.6mW (or 320fJ/bit).6


Figure 2. Our hybrid-bonded transmitter wire bonded to a test printed-circuit board (PCB).

In summary, hybrid integration of a compact, reverse-biased Si ring modulator with a CMOS driver has demonstrated potential in achieving a complete optical link with sub-pJ/bit power that is critical for future high-performance computing systems. Our next step is to show that higher data rates (e.g., 10Gbit/s and beyond,) and stable operation of resonator devices can be achieved with active resonance control.

This work is supported by the Defense Advanced Research Projects Agency's (DARPA) Microsystems Technology Office under an Ultraperformance Nanophotonic Intrachip Communication program supervised by Jagdeep Shah under agreement HR0011-08-09-0001. The views, opinions, and/or findings contained in this article are those of the author and should not be interpreted as representing the official views or policies, either expressed or implied, of the DARPA or the Department of Defense.


Ashok Krishnamoorthy
Sun Labs Oracle
San Diego, CA