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Ultimate low-power devices
Self-powered, integrated systems-on-a-chip are key to developing extremely low-power devices for applications in commercial, defense, space, harsh-environment, and medical settings.
26 May 2010, SPIE Newsroom. DOI: 10.1117/2.1201005.002963
In today's world, consumer-driven technology is eyeing self-powered, handheld electronic gadgets. We are, therefore, working on reducing power consumption and supplying sufficient power to run such integrated devices. Ever-increasing consumer demand for more powerful mobile devices is driving the search for longer-lasting energy sources. In addition, harsh-environment applications, such as those used in the oil and gas industries, deep-sea exploration, and remote sensing, require long-lasting, unmanned devices.
To achieve this energy independence at the nanoscale, several critical technical challenges must be overcome, including nanofabrication of macro/microsystems. This requires developments incorporating light weight (thus portability), low power consumption, faster response, higher sensitivity, and batch production (low cost). In addition, advanced nanomaterials must be integrated to meet performance/cost targets. Nanomaterials may offer new functionalities that were previously underused at macro/microscale dimensions. Finally, energy efficiency must be achieved to reduce power consumption but still supply enough power to meet that low-power demand.
With these challenges in mind, we focus on the concept of an energy-independent system-on-a-chip (SoC) (see Figure 1). Our proposed device includes power-consuming and power-generating parts. The former consists of the main control unit, the communications circuit, and sensors. Collectively, they are responsible for controlling power supply to the load application. The power-generation section consists of a rechargeable lithium-ion battery, a microbial fuel cell, a thermoelectric generator, a solar cell, and a piezo-electric energy harvester. DC power is drawn from the battery, while the microbial fuel cell and thermoelectric generator serve as on-chip battery chargers.
Figure 1. Self-powered, integrated systems-on-a-chip. LIB: Lithium-ion battery. PNG: Piezo-electric energy harvester. TEG: Thermoelectric generator. uMFC: Microbial fuel cell.
We have worked extensively on high-k (dielectric constant)/ metal-gate-stack-based, low-standby-power devices for the 45nm technology node and beyond using both planar and nonplanar architectures.1–3 Our results show significant leakage-current reduction in the off state while attaining higher drive current for faster computation (see Figure 2). Since classical charge-transport-based devices will always fall short of beating the subthreshold slope of 60mV/decade, we also demonstrated electromechanical switching (physical attachment and isolation-based relay) at sub-100nm scales (see Figure 3).4,5 This type of device and its hybrid integration (combined with charge-transport-based devices) may enable fabrication of circuitry where high-performance computation is achieved using charge-transport devices and low-power operations are carried out by nano-electromechanical switches. We are also developing advanced nanofabrication technology for controlled integration of 1D nanowires and nanotubes that are compatible with the state-of-the-art CMOS-based platform.6 With intelligent circuit design and integration of smart, low-power transistors, we expect to develop ultralow to no-power-consumption circuit components.
Figure 2. A high Ion/Ioff current ratio (5 × 105) is achieved without any strain engineering (engr.) at a positive supply voltage, Vdd = 1V.
Figure 3. Scanning-electron micrograph of a laterally actuated nano-electromechanical switch.
While we continue to reduce power consumption on the SoC's ‘debit’ side, we are focusing on integrating energy-scavenging and storage devices, materials, and components. As we experience increased power dissipation and, thus, heated back surfaces of laptops, we show that (by integrating thin-film thermoelectric generators) we can take advantage of the thermal difference of the hot surface (up to 65°C) and room temperature (around 25°C), and convert it into electricity to run approximately 45,000 transistors on a 45nm-node chip. This effort represents our group's core objective to turn negative effects (recyclability) into positive opportunities. We are also working on improving the design of microbial fuel cells for integration with the SoC. Our recent design shows that we can introduce much higher surface-to-volume ratios than any previous demonstrations (see Figure 4).
Figure 4. With intelligent design, very high surface-to-volume ratios are achievable. Cr/Au: Chromium/gold.
In summary, we propose that energy-independent SoCs may operate in harsh-environment conditions characterized by significant temperature differences, changes in pressure, or abundant solar energy. SoCs may or may not be subjected to all these conditions at the same time. The idea is to harvest energy from whatever condition is available at any given time and place. We estimate that the maximum power that can be generated with the energy-independent SoC and high-k/metal gates, with all power-generation components active, is between 5.51 and 9.5mW. The recently developed Phoenix processor is a very-low-power device that consumes only 39pW.7 We estimate that an even larger number of transistors can be employed with carbon-nanotube and nanowire technology.
The author is indebted to SEMATECH Inc. (Austin, TX).
Muhammad M. Hussain
King Abdullah University of Science and Technology
Thuwal-Jeddah, Saudi Arabia
Muhammad Hussain obtained his PhD in electrical engineering from the University of Texas at Austin in December 2005. He is currently an assistant professor in electrical engineering, and has authored 71 peer-reviewed international journal and conference papers on nanofabrication. He is also editor-in-chief of the Journal of Applied Nanoscience (Springer).
1. C. S. Park, M. M. Hussain, J. Huang, C. Park, K. Tateiwa, C. Young, H. K. Park, M. Cruz, D. Gilmer, K. Rader, J. Price, P. Lysaght, D. Heh, G. Bersuker, P. D. Kirsch, H.-H. Tseng, R. Jammy, A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications, . Presented at Very Large Scale Integr. (VLSI) Conf. 2009.
2. C. S. Park, M. M. Hussain, K. Tateiwaa, J. Huang, J. Linb, T. Ngai, S. Lian, K. Rader, B. Taylor, P. Kirsch, R. Jammy, Alternative approaches for high-k/metal gate CMOS: low temperature process (gate last) and SiGe channel. Presented at VLSI-Technol. Syst. Appl. (TSA) 2010.
3. M. M. Hussain, C. E. Smith, R. Harris, C. Young, B. Sassman, H.-H. Tseng, R. Jammy, Gate first integration of high-k/metal gate CMOS FinFET with multi-VTh engineering, IEEE Trans. Electron Dev. 57, pp. 626-631, 2010. doi:10.1109/TED.2009.2039097
4. M. M. Hussain, C. E. Smith, D. Elata, K. Akarvardar, R. Parsa, K. Yoo, J. Provine, J. Williams, K. Rader, J. Barnett, C. Park, M. Cruz, P. D. Kirsch, H.-S. P. Wong, R. T. Howe, R. Jammy, Ultra low power sub-100nm laterally actuated nano-electro-mechanical (NEM) switch in an industry standard process flow for logic and memory applications, NATO Adv. Res. Wrksh. Adv. Mater. Technol. Micro/Nano Dev. Sens. Actuat. In press.