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Optoelectronics & Communications

Silicon nanophotonic chips enable greener and faster telecommunications networks

Optical data routing beyond 100Gb/s is now possible with a new generation of power-efficient, all-optical wavelength converters.
6 April 2010, SPIE Newsroom. DOI: 10.1117/2.1201003.002691

Power efficiency in telecommunications networks is of key importance for next-generation hardware development. Information and communication technology (ICT) alone is responsible for 2 to 10% of global energy consumption and ICT CO2 emissions will almost double by 2020, reaching 1.43Gt worldwide.1 The industry's energy-saving checklist features broadband core networks linking large, power-hungry routing machines. A top-class 640Gb/s-capacity electronic router consumes 10kW, weighs 720kg, and occupies 213×60×91cm3. Scaling these systems to terabyte-per-second capacities, although possible, would translate into huge space requirements and megawatt power consumption.

Photonic routers offer a promising solution for the scalability issues of today's electronic-carrier routing systems and contribute towards realizing eco-friendly optical-transport networks. Routing using photons (rather than electrons) is typically accomplished by exploiting the wavelength domain. A data packet entering a photonic router passes through wavelength converters and wavelength-selective elements that will switch it from an input to a specific output. Successful realization of chip-scale, terabyte-per-second-capacity wavelength routers strongly depends on the availability of highly integrated, power-efficient, all-optical wavelength converters (AOWCs). The latter must be very compact and capable of handling hundreds of gigabits, while consuming only a few tens of Watts. Thus far, densely integrated AOWCs have been fabricated either monolithically in indium phosphide (InP)2 or in a hybrid approach on silica-on-silicon substrates.3 The common feature of both techniques is that AOWCs are integrated as semiconductor optical amplifiers (SOAs), i.e., Mach-Zehnder interferometers (MZIs), each requiring two active elements (SOAs). They rely on the differential (‘push-pull’) switching scheme to operate at a maximum bit rate of 40Gb/s (equal to the line-rate capability of electronic systems). The hybrid solution offers optimum use of the 2in InP wafers. However, the low-index-contrast integration board does not accommodate sharp waveguide bends, thus forcing optical-chip-size increases. To tackle these problems, we have been working on a new, integrated AOWC device concept (see Figure 1). Our device is the first that operates at line rates of 160Gb/s. It combines a small footprint, reduced power consumption, and cost-effective fabrication in a silicon foundry.

Figure 1. Concept of our silicon-on-insulator (SOI) 160Gb/s all-optical wavelength converter. SOA: Semiconductor optical amplifier. MZI: Mach-Zehnder interferometer.

Our device includes two integrated periodic filters and a SOA. We use a silicon platform as base material to implement the waveguide optics (filters) and host the active device through hybrid integration. We employ the SOA to handle the nonlinear processes. It induces chirp in the converted probe signal because of the refractive-index modulation caused by the pulsed pump signal.4 The first cascaded periodic filter is slightly detuned with respect to the probe wavelength. By filtering the blue (fast) chirp, we achieve acceleration of the system's effective recovery time. The second filter restores the polarity of the optical pulses. Both periodic filters are passive MZI structures. They exhibit differential delays of 1 and 2ps, respectively, yielding a free spectral range (FSR) of 8 and 4nm, respectively. Given the periodicity of this comb-like filter structure, a high-speed optical packet injected into our AOWC can be converted using any of the continuous-wave wavelengths that coincide with a specific peak of the periodic response. Finally, the SOA can be flip-chip bonded on the same SOI board using gold/tin or tin/silver copper solder bumps.

We integrated the cascaded MZI structures with silicon-on-insulator (SOI)-rib waveguide technology on substrates with a 4μm-thick top silicon layer. All optical functionality is realized through a single etch step. We used standard contact lithography and reactive ion etching for rib etching. However, additional etching and metalization are required for hybrid integration of the SOA. The resulting mode size (~4μm) enables high coupling efficiency to lensed fibers and III--V semiconductor devices (~0.5dB loss per facet).

Figure 2 shows our new SOI AOWC platform with integrated heater elements for MZI-filter tuning. We tested the chip's performance in combination with a fiber-pigtailed 40Gb/s commercial SOA in a 160Gb/s wavelength-conversion experiment. We found that the inverted signal at the SOA output—see Figure 2(a)—is successfully restored to a proper 160Gb/s wavelength-converted stream—see Figure 2(b)—through the effective recovery-time acceleration and pulse-polarity restoration performed by the silicon chip. Figure 2(c) also shows a clear eye diagram of a demultiplexed 40Gb/s channel.

Figure 2. SOI all-optical wavelength converter. (a) Device blueprint. DI1, DI2: Delay interferometers. (b) Integrated SOI chip. Eye diagrams (data signal as a function of time) of (c) 160Gb/s inverted signal, (d) 160Gb/s noninverted wavelength-converted signal, and (e) 40Gb/s demultiplexed channel.

The SOI-delay interferometer (DI) AOWC scheme consumes approximately 2W, including the power to drive the SOA, tune the FSR of the SOI DIs, and that consumed by thermoelectric cooling. A quad array of SOI AOWCs with a total throughput of 640Gb/s would require approximately 8W (extrapolated), which is 1.5× less than the power consumed by a commercially available SOA-MZI array with a total chip throughput of 160Gb/s. Using silicon, the associated decrease in power consumption correlates with a fourfold increase in total chip throughput.

To construct the first fully operational silicon photonic-wavelength converter on a single chip, we must rely on hybrid integration of the SOAs on the silicon board. This is work in progress. Here, we present the first SOA bonding results. We fabricated SOA chips suitable for flip-chip mounting—see Figure 3(a)—as well as SOI motherboards that contain bumps, vertical alignment stands, contact lines for SOA driving, and waveguides: see Figure 3(b). We employed a high-precision Smart Equipment Technology® FC150 for SOA flip-chip bonding. Figures 3(c) and (d) show scanning-electron-microscope images of the bonded SOA chips. Inspection reveals alignment precision down to the micrometer level on all three axes and the absence of any tilt from the assembly. These results indicate that SOAs can be successfully integrated on SOI AOWC boards using a hybrid approach. We are currently working on the final run to generate the fully integrated devices.

Figure 3. (a) Flip-chip-compatible SOA. (b) SOI motherboard with gold/tin bumps for hybrid integration. (c) and (d) SOA mounted on SOI waveguide substrate. n, p contacts: Semiconductor electron- and hole-dominated contacts.

The European Commission is gratefully acknowledged for partial funding of the ICT-BOOM project as part of its Seventh Framework Programme.

Leontios Stampoulidis, Efstratios Kehayas
Constelex Technology Enablers
Athens, Greece
Konstantinos Vyrsokinos
National Technical University of Athens
Athens, Greece
Lars Zimmernann
Innovations for High Performance Micro-electronics
Frankfurt, Germany
Fausto Gomez-Agis
Technical University of Eindhoven
Eindhoven, Netherlands
Jochen Kreissl, Ludwig Moerl
Heinrich Hertz Institute
Fraunhofer Institute for Telecommunications
Berlin, Germany
Giovan Battista Preve
Nanophotonics Technology Center
Universidad Politécnica de Valencia
Valencia, Spain