In optical microlithography, circuit-design masks are transferred onto silicon wafers. It is therefore a key technology for the manufacturing of semiconductor logic. However, as the dimensions of design features approach or are reduced to less than the illumination wavelength (currently 193nm), distorted wafer images originate because of limitations imposed by the diffraction limit. Various resolution-enhancement techniques (RETs) have been devised to overcome these challenges and further improve resolution.
Optical-proximity correction (OPC) — an RET used for optical microlithography — reduces the distortion of wafer images by compensating the mask layout of design features. Conventional segment-based OPC employs edge fragmentation and parallel displacements for mask optimization, and therefore the solution space is limited to the neighborhood that design features can reach. As CMOS manufacturing enters the 32nm node and beyond using 193nm immersion lithography, conventional segment-based OPC is no longer sufficient for patterning critical layers. As a result, nonprinting subresolution assist features (SRAFs) are added to further enhance image resolution and improve pattern fidelity using some of the mask space not exploited by segment-based OPC. Although current methods for SRAF generation and placement are rather primitive — often involving simple rules obtained from empirical studies — the use of SRAFs and segment-based OPC is still favored among available RETs because of minimal technology-related transition risks and costs.
Alternatively, mask optimization can also be framed into an inverse problem, where the objective is to calculate the best unrestricted mask for printing the given design features by minimizing a particular cost function, as opposed to the conventional direct approach where the mask structures can only be modifications of the original design. Over the past few years, these inverse-lithography-technology (ILT) methods have allowed the full exploration of mask space without pattern-dependent heuristics.1–3 However, without properly designed algorithms, ILT usually gives rise to ideal wafer images at the cost of masks that are very challenging to manufacture. Issues such as dangling pixels and tile-stitching problems can significantly hinder mask fracturing and inspection, preventing ILT insertion into the current mask-making flows.
To achieve some of the optimized corrections produced by ILT while maintaining the convenience of standard OPC, we proposed a model-based pre-OPC flow, where the sizing of drawn patterns and placement of surrounding SRAFs are generated simultaneously in a single iteration using an inverse-lithography method. The complex patterns are then simplified to serve as the input to a conventional OPC solution: see Figure 1.
Figure 1. Modified design/manufacturing flow with the insertion of model-based subresolution assist features (SRAFs) and sizing using inverse-lithography technology (ILT). DRC: Design-rule check. OPC: Optical-proximity correction. ORC: Optical-rule check.
At the core of the approach, an efficient pixel-inversion-based ILT solution has been developed employing innovative wavefront expansion and wavefront-based damping techniques,4 both of which are inspired by ripples propagating on a lake. For any particular layout, the center pixels of drawn features are first determined and then pixels are given a ‘wavefront’ index according to their distance to the center. The wavefront-expansion technique is a biasing method to prioritize the flipping order of pixels, while wavefront-based damping is a weighting function based on the wavefront indices of individual pixels. Figure 2 shows examples of wavefront templates. These techniques drive the final mask toward configurations that are center symmetric to the drawn patterns while allowing fast convergence.
Figure 2. Wavefront templates for various masks. (a) An isolated via with a dimension of 100×100nm2and (b) the corresponding wavefront template, (c) three semi-nested vias of the same dimensions and (d) the corresponding wavefront template, (e) four semi-isolated vias and (f) the corresponding wavefront template.
The final result of this approach is shown in Figure 3. Panel (a) shows an uncorrected mask tile of four semi-isolated vias with dimensions of 100×100nm2. Panel (b) shows a corrected mask using conventional segment-based OPC and rule-based SRAFs in simple rectangular bars. Some of the SRAFs collide with neighboring features, which is a violation to mask-making, best illustrating the pattern-dependent limitation of rule-based SRAFs. Panel (c) shows the corrected mask using the pixel-inversion-based ILT solution in a single iteration, where the optimized mask features tend to be center symmetric in relation to the drawn features. To be compliant with standard mask-manufacturing techniques, this unrestricted mask can be simplified and snapped to 45° and axis-aligned line segments as shown in panel (d), which can serve as the input to conventional segment-based OPC. Note that the SRAFs sandwiched by two vias on the left-hand side are relatively small because of limited space. Also, the 45° SRAF for the bottom via would probably not have been captured by a simple rule-based procedure. We believe that this particular orientation is caused by a conflict in resolution with the lower-left via.
Figure 3. Example comparison. (a) Uncorrected mask tile of four semi-isolated vias, (b) corrected mask using conventional segment-based OPC and rule-based SRAFs, (c) corrected mask using the proposed single-iteration pixel-inversion-based ILT, and (d) the final simplified mask snapped to 45° and axis-aligned line segments.
In conclusion, the wavefront-expansion ILT algorithm offers optimized model-based SRAF generation and sizing with minimal insertion risks, making it a viable solution for the 32nm CMOS node and beyond. We are currently improving the stand-alone OPC algorithm to efficiently generate mask-rule-check-compliant masks. We plan to use a similar algorithm for the implementation of model-based design rules, offering an alternative to design-for-manufacturing approaches.
Peichen Yu, Jue-Chin Yu
Institute of Electro-Optical Engineering
National Chiao Tung University
1. Jonathan Ho, Yan Wang, Xin Wu, Wolfgang Leitermann, Benjamin Lin, Ming Feng Shieh, Jie-wei Sun, Real-world impact of inverse lithography technology, Proc. SPIE 5992, pp. 59921Z, 2005. doi:10.1117/12.632211