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Extreme UV lithography may be used with double patterning
Memory chip and other high-volume component makers will likely use extreme ultraviolet lithography alongside double patterning.
5 February 2009, SPIE Newsroom. DOI: 10.1117/2.1200901.1444
The semiconductor industry has depended on resolution improvements in lithography to enhance products and reduce cost. Historically, better resolution has been driven by improved exposure tools and lithographic processes. But there is no tooling available to increase resolution for the current transition from 45nm to 32nm half pitch. Instead, double patterning is being adopted to get the desired pattern density by adding processing steps. It is being used with the same resolution argon fluoride (ArF) immersion scanners as the previous generation.
New techniques such as extreme ultraviolet lithography (EUVL) promise higher resolution patterning. EUVL uses a much shorter wavelength and gives much better resolution than ArF lithography. Industry surveys indicate EUVL is the most promising higher resolution alternative to ArF.1 The question is: can EUVL be used alone or will it be used with double patterning?
In one method of double patterning, two equivalent exposures are used for the same patterned layer in order to get higher resolution or to print more complicated patterns. This is expensive because it requires more process steps, and can require the entire bottom anti-reflective coating, coat resist, expose, develop, etch and strip resist processes to be repeated.
In another method, one exposure pattern can be doubled by turning one line into a pair of lines. This process requires more deposition steps and more etching.2 It also requires at least a second lower-resolution lithography step to cut off the loops on the ends of the doubled lines.
Either approach to double patterning could theoretically halve the final feature size, but in practice they currently give about a 30% resolution benefit.3,4 This resolution improvement is roughly as much as the switch from dry to immersion ArF lithography, and it is equal to the shrink realized in an entire chip generation.
Figure 1. Experimental tradeoffs between line-edge roughness (LER) and the dose required to print the target feature. Y2007 and Y2008 show interference lithography (IL) results from the years 2007 and 2008. Each point shows the result from a particular resist. The boxed numbers indicate which of the particular resist samples corresponds to selected points on the graph. This enables a comparison of the same resist on the different tools used. For example, for the two graph points labeled “72,” this particular resist appeared somewhat faster but with the same LER on the alpha-demonstration tool (ADT) compared to the IL tool. (Figure courtesy of IMEC, a research center in Belgium.)
Alternately, EUVL uses soft X-rays with a wavelength of 13.4nm to improve resolution. This wavelength is significantly smaller than the current smallest one (193nm), and it can improve resolution with relatively low-aperture lenses. In the future, lens apertures could be increased, which could lead to high resolution, reasonable depth of focus, and potential extendibility.
To use EUVL in manufacturing, many new technologies have to be developed, including light sources, extreme UV mirrors for optics and masks, mirror-based optical designs, debris-mitigation systems, mask-inspection tools, and new resists. Prototypes of all these components exist, and they currently enable slow printing of wafers. Production-scale EUVL will require components that support fast printing of wafers and high-throughput production. A great deal of research and development effort is underway in the industry to develop the necessary equipment and techniques. Currently, demonstration tools with low throughput are being used to develop materials and to increase the understanding of EUVL. Early results show that the promised resolution improvements are real. Roadmaps presented in October suggest 100 wafer-per-hour scanners could be available between 2010 and 2012.5 Assuming the industry meets this schedule, it should be in time for the 22nm half-pitch node.
The applications and products for which EUVL is used will depend on cost. That issue was addressed in a recent paper by Wuest and colleagues at SEMATECH. The authors compared EUVL to various double-patterning options and concluded EUVL would be roughly 25% less expensive for the 22nm half-pitch node. The largest costs are tool throughput and masks. The throughput assumptions depend on resist suppliers meeting the Semiconductor Industry Association's (SIA's) roadmap resist-performance targets.
In fact, many papers have stated there is a difficult tradeoff between resist photo speed, resolution, and line-edge roughness (LER).5 Papers at the most recent EUVL conference showed improvements individually in photo speed and LER as well as excellent resolution, but no progress has been made to improve the tradeoff between photo speed and LER. Consider the result reported by Goethals and colleagues shown in Figure 1. Each point shows the result from a particular resist. ‘Y2007 IL’ indicates interference lithography results from 2007, ‘Y2008 IL’ indicates similar results from 2008, and ‘ADT’ indicates results from the alpha demonstration full-field tool installed.6 No progress was seen in the photoresist and LER tradeoff; although, the two types of tools showed different photo speed results. The results are still far from the SIA's roadmap target of 1.9nm line-width roughness (LWR)7 for the 36nm half-pitch node and 1.2nm LWR for 22nm half-pitch node. (LWR is related to LER, but it is typically larger by a factor of about 1.4, since it measures the variation in the entire line width rather than the variation in the position of one line edge. This means the points on the graph in Figure 1 would have higher LWRs than the LERs shown.)
No resist matches the SIA target, and the ones that come nearest print closer to 30mJ/cm2 rather than 10mJ/cm2. This is a significant problem. Improvements will likely occur, but it is unlikely they will close such a large gap. In that case, an EUVL user will have the choice of using a fast resist and a yet-to-be-invented, post-processing technique to reduce LER or accepting a lower throughput. Either alternative adds cost, suggesting current EUVL cost estimates are too low.
The cost estimates for double patterning reflect current processes. If there are materials and process improvements in the next two years, costs could be more favorable. This is likely given that there are many new approaches already proposed in the literature,8–10 and, historically, material improvements have provided more resolution enhancement than have tool improvements.11,12 If costs are higher than projected for EUVL and lower than projected for double patterning, then users who get many wafers per mask, such as memory makers, will probably find EUVL more expensive than double patterning.
This does not mean that EUVL will not be adopted. The resolution it delivers is spectacular. Already, single exposure 22nm half-pitch lines and spaces with reasonable profiles have been demonstrated, and 32nm half-pitch lines and space imaged with reasonable process windows have been printed.13,14 Unless some unexpected roadblock appears, the question is not whether EUVL will work, but how much it will cost relative to other processes. For companies that get a low number of wafers per mask, mask costs could be such that EUVL is the least expensive alternative. But for others, especially memory makers, the resolution of EUVL will be the most appealing feature, even though its cost may be higher than double patterning.
In any case, the cost benefit of using both and getting even smaller features will be irresistible. Integrated circuit manufacturers clearly found it worthwhile to pay the cost of double patterning in order to move from 45nm to 32nm half pitch. Since it made financial sense to do this, it also will be worthwhile to use EUVL because of the resolution achieved in a single exposure. Other things being equal, no memory manufacturer using just EUVL could compete with another producer using EUVL combined with double patterning. The second manufacturer would have 30% resolution and a 2X density improvement compared to the first manufacturer. This suggests memory makers will use EUVL technology to enhance the resolution provided by double patterning.
EUVL shows feasibility, and it promises resolution improvements. So, it will likely become the lithography of choice for a future generation of chips. For producers of high-volume parts, like memory producers, EUVL is likely to be used with double patterning rather than replacing it.
AZ Electronic Materials Corp.
Mark Neisser, global technology director for bottom anti-reflective coating and global applications, joined AZ Electronic Materials in 2000 after working for two years at Arch Microelectronic Materials and 16 years at IBM. He received an AB in chemistry from Cornell University and an MS and PhD in organic chemistry from the University of Michigan. He is the author of more than a dozen patents and 50 technical papers. He is one of the inventors of double exposure as a resolution enhancement technique, having published and filed patents in 1998. He is a member of SPIE.
5. Recent roadmaps were presented at the 2008 EUVL Symposium, held from September 28 to October 1, 2008 in Lake Tahoe, CA. For scanner roadmaps, see H. Meiling et al., EUV alpha demo tools - stepping stones towards volume production, slide 5; T. Miura, Nikon EUVL development progress update, slide 4; and S. Uzawa et al., Development status of Canon's full-field EUVL tool, slide 4. For source roadmaps, see D. Brandt et al., Laser produced plasma source system development, slides 13 and 23; A. Endo et al., CO2 laser-produced Sn plasma source for EUV lithography, slides 3 and 17; M. Corthout and M. Yoshiaka, EUV sources based on DPP, slide 19, K. Takenoshita et al. Time-multiplexed solid-state laser-driven EUV sources for beta-tools and HVM, slide 16; and G. Biannucci et al., Design and fabrication consideration of EUVL collectors for HVM, slide 10.