Iris recognition (IR) is one of the most accurate biometric identification methods available, with custom algorithms deployed globally in a variety of systems ranging from personal computers to portable scanners. The overall performance of these systems—based on their size, shape, speed, power, and accuracy—is of considerable interest to commercial and military vendors alike. As IR systems increase in popularity, the new algorithms are revealing their capabilities in greater detail. Recently, we developed the ridge energy direction (RED) algorithm,1 to improve performance for the end user.
The iris, an internal part of the eye protected by the cornea, sustains its appearance over decades. After an image of the iris is digitally captured (see Figure 1), the image is transformed from a 2D array of pixels into a 2D encoded string of bits for comparison, a process referred to as templating (see Figure 1, upper left).2
Figure 1. Measurable iris area detected by the algorithm. Top left shows the associated 2D encoding of the iris image.
The IR system must reliably match the new template with one previously enrolled. The newly encoded iris is compared to a database using a fractional hamming distance (HD) calculation, defined as follows:
The exclusive-or operator () detects disagreement between pairs of bits in the two templates, while represents the binary AND function. Masks A and B identify the values in each template that are not corrupted by artifacts (e.g., eyelids/eyelashes and specularities). The denominator ensures that only the bits that matter are included in the calculation after discounting such artifacts. To make a match or non-match declaration, the fractional HD between two templates is compared to a predetermined threshold value. As a task that is repeated many times, the HD calculation is a critical part of IR. It is extremely parallel, which means that all 2,048 bits can be compared simultaneously.
Currently, enrolling a new iris can take up to ten seconds and a database match can even take longer. IR technologies were originally developed for use with central processing unit (CPU)-based systems, which are general purpose machines designed for all types of applications. With such non-specialized hardware, parallelizing an application becomes a challenge and, indeed, CPUs are known as sequential processing devices. Because parts of the IR algorithm can be parallelized, CPU-based processing in this context is inefficient.
By comparison, field programmable gate arrays (FPGAs) are complex programmable logic devices, essentially a ‘blank slate’ integrated circuit that can be programmed with nearly any parallel logic function. They are fully customizable. The designer can prototype, simulate, and implement a parallel logic function without the added cost of a new integrated circuit manufactured from scratch. FPGAs are commonly programmed via very high speed integrated circuit (VHSIC) hardware description language (VHDL). Statements in VHDL are inherently parallel, not sequential, and the programmer may dictate the type of hardware that is synthesized on an FPGA.
We have implemented the HD using VHDL on a modern FPGA, and compared performance against a state-of-the-art CPU. The CPU used for this experiment was an Intel Xeon X5355 workstation-class machine, while the FPGA was executed on a DE2 board provided by Altera Corporation, which includes a Cyclone-II EP2C35 chip, as well as the required programming interface. Execution and acceleration times, shown in Figure 2, indicated 383ns per match for the optimized Xeon version versus 20ns per match for the FPGA. Thus, the principal result so far demonstrates that the HD calculation on a FPGA of modest size is approximately 19 times faster than a state-of-the-art CPU design. (We note that the Cyclone-II is not built for high performance nor is its design the current state of the art.) Estimates of the performance of a faster Cyclone-II (100MHz) and also a state-of-the-art Stratix IV FPGA are also provided in Figure 2. Given traditional scaling of FPGAs, we anticipate that the latter at 500MHz would be able to perform a match in just 2ns.
To meet commercial and military demands for an accurate, timely, and compact IR system, we believe a parallelized FPGA-based option presents an exciting alternative. As part of our future work, we plan to explore parallelization of the complete IR algorithm.
Figure 2. Field programmable gate arrays compared with central processing unit machines for iris match execution.
Ryan Rakvic, Randy Broussard, Lauren Kennell, Jim Matey
United States Naval Academy (USNA)
Ryan Rakvic is an assistant professor in the Electrical and Computer Engineering Department at the USNA. Prior to joining the USNA, Ryan spent five years in the computer research lab at the Intel Corporation. He received his BS degree in computer engineering and his MD and PhD degrees from Carnegie Mellon University.
Randy P. Broussard received a BS degree in electrical engineering from Tulane University in 1986, an MS in computer engineering from the Florida Institute of Technology in 1991, and a PhD in electrical engineering from the Air Force Institute of Technology in 1997. He is currently an assistant professor in the Department of Systems Engineering at USNA, where he teaches computer engineering, computer vision, and control systems. His research interests research include aspects of pattern recognition.
Lauren Kennell is currently a research professor at USNA. Among her current fields of interest are biometrics and mathematics.
Jim Matey, retired in 2008 from the Sarnoff Corporation after 30 years of service, is now a research professor in the Biometric Signal Processing Laboratory at USNA. He served as the lead scientist/engineer and architect for Sarnoff's Iris on The Move systems.
Southern Methodist University
Delores M. Etter holds the Texas Instruments Distinguished Chair in Engineering Education in the School of Engineering at Southern Methodist University. A former professor in Electrical/Computer Engineering at USNA, she served as Assistant Secretary of the Navy for Research, Development, and Acquisition from 2005 to 2007.