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Micro/Nano Lithography

Monolithic integration of light-emitting devices and silicon transistors

Dislocation-free, lattice-matched, Si/nitride/Si layers allow fabrication of compound-semiconductor-based light-emitting diodes and Si-based metal-oxide-semiconductor field-effect transistors on a single substrate.
19 November 2007, SPIE Newsroom. DOI: 10.1117/2.1200711.0914

Silicon is the foundation for integrated circuits, but it does not emit light efficiently at room temperature. Optical devices, by contrast, are usually built from compound semiconductors chosen from the III V element groups. Monolithically integrating light-emitting devices with Si large-scale integrated circuits (LSI) on a single chip is a long-standing dream. The resulting optoelectronic integrated circuits (OEICs) could be useful for parallel information processing, optical interconnection, and other applications.1

Three problems have prevented development of such monolithic OEICs: first,the large number of dislocations when III-V compounds are grown on lattice-mismatched Si; also, the incompatible fabrication processes between Si LSI and III-V devices; and finally, the increase in the number of process steps by sequentially fabricating the Si LSI and light-emitting devices.

We have overcome the first problem by using better matched III-V nitride (III-V-N) alloys instead of conventional III-V compounds. As shown in Figure 1, dislocation-free Si and GaPN (shorthand for GaP(1-x)N(x)) layers were grown by molecular-beam epitaxy on a Si substrate.2,3 Although GaP has an indirect bandgap, the nitrogen alloy GaPN emits luminescence.4 If GaPN-based light-emitting devices are realized, Si/GaPN-based layers can allow monolithic OEICs.5

Figure 1. Cross-sectional transmission-electron-microscope (TEM) image of dislocation-free Si and GaPN layers grown on a Si substrate.

To overcome the second and third problems, we have developed a new fabrication process for monolithic OEICs.6 The basic devices are Si metal-oxide-semiconductor field-effect transistors (MOSFETs) and III-V-N-based light-emitting diodes (LEDs).7 Integrated circuits composed of Si MOSFETs drive the LED, as shown in Figure 2(a). The starting Si/GaPN-based layers in Figure 2(b) are grown by the dislocation-free growth process.5,6 The MOSFETs and LEDs can be fabricated in the topmost Si layer and the InGaPN/GaPN double heterostructure (DH) layer, respectively.

Figure 2. (a) Schematic cross-section of the completed optoelectronic integrated circuit (OEIC), showing a representative metal-oxide-semiconductor field-effect transistor (MOSFET) driving a light-emitting diode (LED). (b) Starting Si/GaPN layer structure, including the double heterostructure (DH) that will form the LED, grown on a migration-enhanced epitaxy (MEE) GaP layer on a Si substrate.

Figure 3. Steps in the fabrication process flow for OEICs, based on a conventional MOSFET process. The LED is formed in the III-V layers of the starting material, shown in orange. CVD: chemical-vapor deposition.

Figure 3 shows the fabrication processes for the OEIC6,7 by which p-type MOSFETs and LEDs were simultaneously formed with the same precision. A pn junction around the LED was etched off and a 1μm-thick SiO2 film was deposited as a field oxide and as encapsulation for the LEDs. After forming the active region of the MOSFETs, the source, drain, and contact to the Si layer were formed by ion implantation. A 16nm-thick gate oxide was grown in a wet O2 ambient for 10min at 900°C. This process provided the thermal annealing after the ion implantation and improved the luminescence efficiency of InGaPN layer.4

Figure 4. (a) Photograph of OEIC-test chip. (b) Photograph of a wafer containing several chips. Four LEDs, denoted by a dotted ellipse, emit red light.

Figure 4(a) shows a fabricated 2.5mm×2.5mm test chip. All MOSFETs and LEDs in the chip operated.

The gate length of the MOSFETs was 10μm. The gate widths varied from 30 to 400μm. The threshold voltage of the MOSFET was as large as −3.1V due to a high electron concentration in the Si epitaxial layer.

The LED areas varied from 20×45 to 300×300μm2. The photograph of a wafer is shown in Figure 4(b). Four LEDs, each with an active area of 100×100μm2 and biased at 10mA, are emitting red light through the metal probes.6

We electrically contacted the LED and the MOSFET with the probes and synchronously switched the emission by applying a voltage to the gate. These results show that an optimized process flow could effectively realize monolithic OEICs.

In summary, by using a Si/InGaPN/GaPN DH LED structure on Si, we developed a fabrication process to monolithically merge LEDs and Si-based MOSFETs in a single chip for the first time. To realize intelligent monolithic OEICs, the threshold voltage should be lowered and smaller LEDs should be fabricated. For high performance, InGaPN or GaAsPN, either of which has a direct bandgap, should be used as an active layer. One application of OEICs is massively parallel information processing in biological sensors and brains.7 The light emission would also be useful for the optical interconnections within or between chips.

Yuzo Furukawa, Hiroo Yonezu, Akihiro Wakahara 
Toyohashi University of Technology
Toyohashi, Japan