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Physical characterization of breakdown in metal-oxide-semiconductor transistors

Gate-dielectric breakdown in field-effect transistors depends not only on the gate dielectric but on the electrode materials and the overall structure.
17 October 2007, SPIE Newsroom. DOI: 10.1117/2.1200710.0888

Silicon-based semiconductor devices have evolved from the micro- to the nano-regime over the last few years. Critical dimensions in conventional metal-oxide-semiconductor (MOS) field-effect transistors (MOSFETs) have shrunk so that the gate length is about 30nm, while the thickness of the dielectric separating it from the substrate is about 1.5nm. These tiny devices can suffer dielectric breakdown that differs markedly from that of their larger cousins.

There have been few previous attempts to physically characterize breakdown failures in MOS structures. Emission microscopy, which detects very faint light emission from weak points in Si devices, has been routinely used to locate ‘defects’ in gate dielectrics, but it suffers from low spatial resolution and provides no chemical information about the failure defects. To get more insight into the nature of the breakdown path, we have been working on a new approach that combines ultra-precise sample preparation with elementally and chemically sensitive transmission electron microscopy (TEM) with nanometer resolution.

Figure 1. Top-view of a nanometer-size transistor. L and W are its length and width, respectively. The shaded area includes the ultrathin (<2nm) gate dielectric, sandwiched between a polycrystalline-silicon (poly-Si) gate electrode and the silicon substrate.

Figure 2. Transmission electron microscopy (TEM) images of dielectric-breakdown-induced epitaxy (DBIE), originating near the cathode, and associated thermal damage of the Si lattice at the breakdown site of a poly-Si/SiO2 (a) n-channel and (b) p-channel metal-oxide-semiconductor field-effect transistor (MOSFET).2 Gox: gate oxide. Sub: substrate. Poly-Si: poly-crystalline silicon.

First, to precisely locate the nanometer-sized breakdown-induced defects for further TEM analysis, we restrict the gate-dielectric breakdown ‘spot’ to an area less than 500nm long and 200nm wide, as shown in Figure 1. This is achieved by performing accelerated voltage stressing on nanometer-sized MOSFETs until a dielectric breakdown event is detected. We then use a precision focused-ion-beam (FIB) technique to prepare lamellae that are ∼100nm thick in the width direction of the original transistor, as shown in Figure 1. Selecting a transistor width of about 200nm is critical to ensuring a better−than−90% chance of catching the failure site within the lamellae.

Figure 3. Breakdown−induced thermochemical reactions in (a) poly−Si gate and (b) p−Si substrate of n−channel MOSFETs. The gate dielectric is 4.8nm−thick HfO2.4 BD: breakdown. IL: interfacial layer. Sub: substrate. Poly−Si: polycrystalline silicon.

Figure 4. Electron energy−loss spectroscopy (EELS) spectra of (a) oxygen K edge and (b) Hafnium O2,3 edge at various locations in the n−channel MOSFET shown in Figure 3(a).4 Arb: arbitrary.

Figure 5. High−resolution transmission electron micrograph of a breakdown spot of a poly−Si/HfO2 device, stressed with the voltage polarity that induces electrical inversion in the substrate.3 Sub: substrate. DBIE: dielectric−breakdown−induced epitaxy.

We used high−resolution TEM imaging to study the breakdown−induced defects in a cross−section along the length direction of the original transistor. Traditional MOSFETs employ a polycrystalline Si (poly−Si) gate with a SiO2 dielectric. For this transistor structure, a Si ‘hillock,’ resulting from a process called dielectric−breakdown−induced epitaxy (DBIE), always evolves from the cathode towards the anode,1,2 as shown in Figure 2. We proposed a physical model that relates the Si epitaxy to thermal migration of Si atoms due to a surge of ‘electron−wind’ current in the vicinity of the breakdown site.1

Figure 6. A proposed TEM/EELS procedure to chemically analyze breakdown paths in ultrathin gate dielectrics. White dots are locations for the EELS data recording5 across the ‘possible’ breakdown path in a gate dielectric revealed by DBIE. Sub: substrate. Poly Si: polycrystalline silicon.

Figure 3 shows the breakdown−induced formation of a ‘ball−shaped’ capping−layer in both the poly−Si gate and substrate of n−channel MOSFETs employing a poly−Si gate with a high dielectric constant (high−κ) HfO2 dielectric.3,4 The elemental analysis in Figure 5 shows that DBIE is a universal dielectric−breakdown−induced defect, independent of gate electrode and dielectric materials.1–5 The physical evidence in Figure 4 points to a complex thermochemical interaction among the gate, high−κ dielectric, and substrate materials.

We have recently acquired the scanning transmission electron microscope with the world's highest (commercially available) energy resolution, the Monochromatic TITAN 80-300KV Analytical scanning TEM. The new TEM has an energy resolution of approximately 0.15eV, allowing very precise chemical and structural analysis of the breakdown site. For example, in Figure 6, we show proposed locations to obtain local electron energy-loss spectroscopy (EELS) spectra at atomic resolution, both at the breakdown spot/path and its vicinity.5 With these advanced nanoanalytical techniques, our ultimate aim is to decode the nature of the breakdown path and its associated failure mechanism in sub-4.0nm thick gate dielectric materials.

The authors would like to acknowledge IMEC, Chartered Semiconductor Manufacturing and A*STAR for their support towards this project.

Kin-Leong Pey
Division of Microelectronics
School Electrical and Electronic Engineering
Nanyang Technological University
Singapore, Singapore

Kin-Leong Pey is an associate professor, head of the Microelectronics Division, program director of the Si Technology Research group, laboratory supervisor of the MicroFabrication Facility and the director of the Microelectronic Center in the School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore, and holds a concurrent Fellowship appointment in the Singapore-MIT Alliance (SMA).

Chih-Hang Tung
Institute of Microelectronics
Singapore, Singapore