SPIE Membership Get updates from SPIE Newsroom
  • Newsroom Home
  • Astronomy
  • Biomedical Optics & Medical Imaging
  • Defense & Security
  • Electronic Imaging & Signal Processing
  • Illumination & Displays
  • Lasers & Sources
  • Micro/Nano Lithography
  • Nanotechnology
  • Optical Design & Engineering
  • Optoelectronics & Communications
  • Remote Sensing
  • Sensing & Measurement
  • Solar & Alternative Energy
  • Sign up for Newsroom E-Alerts
  • Information for:
SPIE Photonics West 2019 | Register Today

SPIE Defense + Commercial Sensing 2019 | Register Today

2019 SPIE Optics + Photonics | Call for Papers



Print PageEmail PageView PDF


Simplifying hybrid semiconductor-nanodevice circuits

A rotating technique that connects nanowires to a silicon chip could enable rapid advances in integrated circuits to continue.
3 August 2006, SPIE Newsroom. DOI: 10.1117/2.1200607.0325

The current revolution in information technology arose from exponential progress in integrated circuits thanks largely to miniaturization.1 Over the next decade, however, that progress looks set to slow, for the following reason. The workhorse device of integrated circuits is the silicon field-effect transistor, which requires accurate lithographic creation of several dimensions, including the length and width of its conducting channel. As these devices are scaled down, quantum-mechanical effects demand increasingly precise lithography,2 which is much more expensive. At some point, scaling will bring diminishing returns. Unfortunately, alternative electronic devices either run into similar fabrication problems, have lower functionality, or both.

Nonetheless, recent experimental and theoretical research indicates one plausible solution: hybrid semiconductor-nanodevice circuits,2–4 in which a silicon chip is augmented by a top layer of very small, simple (two-terminal) nanodevices. These two-terminal devices depend on only one crucial dimension, the distance between two electrodes. Moreover, film thickness controls that parameter with subnanometer precision, without overly expensive equipment.

Although simple two-terminal devices cannot amplify signals, they might work as a latching switch, or programmable diode (see Figure 1). At low applied voltage, such a device operates as a diode, which means that it has a nonlinear, monotonic current-voltage (I-V) curve. High voltage, though, can switch it from this ‘ON’ state into the virtually nonconductive ‘OFF’ state and back. Thus the device could operate as a memory cell, storing one bit of information.

Figure 1. (a) Combining semiconductor and two-terminal nanodevices can make a latching switch as shown in this current-voltage (I-V) curve. (b) The level of current applied determines the state of the switch.5

For efficient operation, these nanodevices must connect with a silicon-transistor subsystem. In the current focus of this field, latching switches form at each crossing point of a lattice of nanowires (see Figure 2).3–9 This configuration does not require alignment between the two nanowire levels. Hence, it can be fabricated by newer patterning techniques, such as nanoimprint lithography. As shown in Figure 2(b), we used this technique to make a 1,000-device system at 30nm half-pitch.6 This approach may be scalable down to a few nanometers.

Figure 2. (a) Two layers of nanowires can create nanodevices. (b) This scanning electron micrograph shows an experimental sample.6

Even with the crossbar geometry, individual nanowires must be accessible to reach each crosspoint device. Although several techniques based on stochastic doping of semiconductor nanowires have been suggested to solve this issue,3 the CMOS/molecular hybrid (CMOL) interface2,4 seems the most general and easiest to implement. In this approach (see Figure 3), sharp-tipped pins—distributed over the circuit area—provide the silicon-nanowire interface. Here, rotating a nanowire crossbar relative to the rectangular grid of pins, as shown in Figure 3(b), allows the CMOS subsystem to contact every nanowire, thereby addressing each nanodevice. Nanoscale alignment of the crossbar with the CMOS stack is not required for high fabrication yield.8

Figure 3. (a) CMOS/molecular hybrid (CMOL) technology connects a nanolayer to a semiconductor substrate with interface pins. (b) Rotating the nanowire layer by a specific angle (α) makes each nanowire accessible to the semiconductor-transistor subsystem.

According to recent calculations, CMOL circuits with crosspoint latching switches could be used in virtually all areas of information processing and storage. For example, they might enable terabit-scale resistive memories with sub-100ns access time.7 Reconfigurable CMOL logic circuits might provide function density that is at least two orders of magnitude higher than CMOS devices fabricated with the same design rules and at manageable power dissipation.8 In the long term, CMOL technology might be applied to mixed-signal neuromorphic networks, or CrossNets, with the objective of becoming the first hardware capable of challenging the human cerebral cortex in density and far exceeding it in speed, at comparable component functionality.9 Most important, these circuits might function with a large fraction—greater than 10%—of bad nanodevices,7–9 which could be expected in the first stage of CMOL technology development.

Just a year ago, these exciting prospects seemingly hinged on developing radically new molecular technology to implement reproducible crosspoint latching switches, which looked a decade or more away. Nonetheless, several groups have shown devices with this functionality, using layers of various organic and inorganic materials.8 Especially impressive is the excellent reproducibility of the copper oxide latching switches that Spansion—the maker of flash-memory chips—has demonstrated, as shown in Figure 1(b).5 Although maintaining reproducibility during deep scaling of these devices could still require substantial work, the first practical CMOL circuits are nearing reality.

Konstantin Likharev
Stony Brook University
Stony Brook, NY
Konstantin Likharev received the candidate (PhD) degree in physics from Lomonosov Moscow State University, Russia, in 1969. He worked at that university until 2001, and then accepted a professorship at Stony Brook University. Currently, his main research interest is nanoelectronics, from materials and devices to circuit architectures and system applications.

1. International Technology Roadmap for Semiconductors, 2005 Edition. Available online at http://public.itrs.net/
2. K. K. Likharev, Electronics below 10nm,
Nano and Giga Challenges in Microelectronics,
pp. 27-68, Elsevier: Amsterdam, 2003.