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Outlook for SFIL-nanoimprint lithography
The step-and-flash imprint lithography method of nanoimprinting has potential advantages in cost and resolution. Its first commercial appearance is likely to be in non-semiconductor applications.
8 August 2006, SPIE Newsroom. DOI: 10.1117/2.1200607.0313
Nanoimprint lithography has been generating increasing interest over the last several years. Indeed, there seems to be an ever expanding number of potential nanoimprint applications and variations on the basic nanoimprint lithography concept.1 The different nanoimprint variants each have advantages and disadvantages for specific end-use applications, and overall winners and losers remain to be sorted. The University of Texas (UT)-Austin developed its version of nanoimprint, step-and-flash imprint lithography (SFIL), in 1998.2 The SFIL method is distinguished from the original version of nanoimprint lithography by being a UV-assisted nanoimprint technique that molds photocurable liquids in a step-and-repeat, die-by-die fashion rather than heat-assisted molding of full, polymer-coated wafers. SFIL was specifically targeted from the beginning for applications in semiconductor manufacturing. In these applications, SFIL has the advantage of being a room-temperature, low-imprint force method. Thus, it is feasible that SFIL can achieve the fine alignment and overlay control necessary for multilevel semiconductor device fabrication. In 2001, the SFIL concept was licensed for commercial development to Molecular Imprints, Inc. (MII), a company founded to develop SFIL-capable tools and related processes.
While it may initially have targeted semiconductor applications, the SFIL process is now being explored for manufacturing emerging technologies, such as photonic crystals and micro/nano-optical components—see Figure 1(a)—and nanopatterned magnetic media future hard disk drives. Progress in these new areas has been such that SFIL is likely to find its first commercial manufacturing application in one of these emerging technologies well before it would be required for high-volume, sub-50nm semiconductor lithography. A notable feature of nanoimprint technologies is their relatively low cost, which allows researchers to explore applications of nanopatterning that would never be economically feasible given the extraordinary cost associated with extreme ultraviolet (EUV) lithography or even current-generation 193nm steppers.
Figure 1. SFIL imprint results are shown for (a) close-packed microlenses, 2-micron squares; (b) 45nm-node logic chip patterns containing 30nm lines and spaces; (c) 32nm-node memory chip contacts, 41nm half-pitch spacing; and (d) cross-section, multitier imprinted insulator with 100nm-diameter via. Images 1(a–c) courtesy of Molecular Imprints, Inc.
In the eight years since initial development at UT-Austin, SFIL tools have grown very sophisticated. The original UT tool had zero overlay/alignment capability, handled only manually loaded 125mm wafers, and required several minutes to perform a single imprint. Now MII's most recent tool can achieve sub-10nm, 3σ alignment. The latest-generation SFIL tool has a throughput approaching five 200mm wafers per hour. Of course, individual tools cost much less than photosteppers, and throughput is improving with each tool generation. But in many emerging applications photostepper-like throughput may not be required.
SFIL has demonstrated outstanding resolution, with sub-50nm features routinely being imprinted: see Figure 1(b) and (c).3 SFIL's resolution is currently controlled by the resolution of the 1 × template/mold fabrication process. Features down to 20nm have been successfully replicated, and unintentional template artifacts at sizes down to 5nm and below also replicate. It is a tremendous advantage for SFIL and other nanoimprint methods that they copy the mold in such exacting detail with very high resolution, but the flipside of this is that the mold must be of very high quality. Any defects or imperfections in the mold are replicated in every imprint. The task of making templates, and the concomitant necessity of inspecting them, is extremely challenging and requires infrastructure development that is only slowly taking place. A NIST Advanced Technology Program–supported joint venture has been formed to help develop the infrastructure necessary for using SFIL on contact levels for sub-50nm nodes. But progress in template fabrication and inspection has been slow and is still underfunded. The technological challenges associated with production of 1 × masks may require a larger effort from the broader nanoimprint community. Perhaps an industrial consortium effort along the lines of the EUV mask programs at Sematech or IMEC will be necessary.
While implementing SFIL for high-volume manufacturing of the gate or contact level of semiconductors is not feasible in the near term, SFIL is one of the few methods currently available for low-volume prototyping at the 32nm node. Another application of SFIL that is drawing interest from the semiconductor community is the direct, simultaneous imprinting of multiple device levels using multitier templates: see Figure 1(d).4,5 SFIL can print both a wiring and via level into a low-k dielectric material in a single imprint lithography step and thus reduce the number of steps associated with back-end-of-line (BEOL) processing by a factor of 2 or more. UT-Austin has been developing this process with Sematech, ATDF, Applied Materials, and IBM. This process could be the first SFIL semiconductor-related manufacturing implementation, one in which lower cost rather than high resolution is the driving force.
The semiconductor business has very exacting requirements and a deeply entrenched bias in favor of photolithographic techniques. This preference makes it difficult for some to seriously consider any non-photo next-generation lithography method. However, the potential advantages of SFIL in cost and resolution are significant. Also, new markets for nanopatterning are rapidly emerging, and many non-semiconductor applications will require very high resolution patterning that is essentially only available from nanoimprint as few of these new industries will be able to justify spending $50 million to $100 million for a single advanced photolithography or EUV patterning tool. We believe that SFIL has a future in semiconductor device manufacturing. But it is increasingly likely that the first commercial realization of the technology will be in non-semicon ductor applications. These other markets will help stimulate the development of infrastructure and advance nanoimprint to the point where, should photolithography or EUV become either physically impossible or economically unfeasible for semiconductor device fabrication, nanoimprint/SFIL will be ready to fill the void.
C. Grant Willson, Michael D. Stewart
Dept. Chemical Engineering, University of Texas at Austin
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Vol: 105, no. 4, pp. 1171-1196, 2005.
2. M. Colburn, S. Johnson, M. Stewart, S. Damle, T. C. Bailey, B. Choi, M. Wedlake, T. Michaelson, S. V. Sreenivasan, J. Ekerdt, C. G. Willson, Step and flash imprint lithography: a new approach to high-resolution patterning,
Vol: 3676, pp. 379-389, 1999.
3. G. M. Schmid, D. J. Resnick, E. D. Thompson, L. J. Myron, D. L. Olynick, J. A. Liddle, G. A. C. Jones, W. Dauksher, N. Le, Fabrication of imprint templates for semiconductor lithography at the 32nm node,
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4. M. D. Stewart, J. T. Wetzeland, G. M. Schmid, F. Palmieri, E. Thompson, E. K. Kim, D. Wang, K. Sotodeh, K. Jen, S. C. Johnson, J. Hao, M. D. Dickey, Y. Nishimura, R. M. Laine, D. J. Resnick, C. G. Willson, Direct imprinting of dielectric materials for dual damascene processing,
Vol: 5751, pp. 210-218, 2005.
5. F. Palmieri, M. D. Stewart, J. Wetzel, J. Hao, Y. Nishimura, K. Jen, C. Flannery, B. Li, H.-L. Chao, S. Young, W. C. Kim, P. L. Ho, C. G. Willson, Multi-level step and flash imprint lithography for direct patterning of dielectrics,
Vol: 6151, pp. 61510J/1-61510J/9, 2006.