SPIE Startup Challenge 2015 Founding Partner - JENOPTIK Get updates from SPIE Newsroom
  • Newsroom Home
  • Astronomy
  • Biomedical Optics & Medical Imaging
  • Defense & Security
  • Electronic Imaging & Signal Processing
  • Illumination & Displays
  • Lasers & Sources
  • Micro/Nano Lithography
  • Nanotechnology
  • Optical Design & Engineering
  • Optoelectronics & Communications
  • Remote Sensing
  • Sensing & Measurement
  • Solar & Alternative Energy
  • Sign up for Newsroom E-Alerts
  • Information for:
    Advertisers
SPIE Photonics West 2017 | Register Today

SPIE Defense + Commercial Sensing 2017 | Register Today

2017 SPIE Optics + Photonics | Call for Papers

Get Down (loaded) - SPIE Journals OPEN ACCESS

SPIE PRESS




Print PageEmail PageView PDF

Optical Design & Engineering

A genuine design manufacturability checker for integrated circuit designers

A full-chip design-for-manufacturability solution has been developed that enables integrated circuit designers to detect printability hotspots quickly, improve manufacturability, and maximize process utilization.
2 June 2006, SPIE Newsroom. DOI: 10.1117/2.1200604.0221

Until recently, integrated circuit design was based on the following contract between design and manufacturing: designs are to follow a set of manufacturing-driven constraints (commonly known as ‘design rules’), and manufacturing is to meet the performance and yield targets in producing the specified design. This arrangement worked for many years until the designs of sub-100nm nodes came along, when the optical proximity effects started to affect systematic and parametric yields severely, despite ever-improving resolution enhancement technique (RET) methodologies.1 As a result, design rules were not manufacturable, and several design techniques—known collectively as design for manufacturing (DFM)—were deployed to attempt to restore the contract.

DFM issues

Most DFM solutions are still centered on evolutionary rule-based solutions that no longer capture the complexity of all manufacturing processes.2 For sub-100nm process technologies, designers need to check the manufacturability of their designs by anticipating lithography effects—including RET transformations—and adjusting the layout to accommodate for these effects.3–5

To maximize the yield and the process utilization below 100nm, designers need DFM solutions that predict printability hotspots from the design database, handle full-chip analysis, achieve run times that are considerably faster than current RET tools for full-chip analysis, easily integrate into design flows, and not require designers to have RET expertise or overwhelm them with unnecessary manufacturing information. In addition, the DFM solutions should accurately model all steps of the manufacturing process, be available as early as possible in the flow, be easy to maintain and synchronize to the process (i.e., be decoupled from the manufacturing engine and recipe), and protect the manufacturers' intellectual property.

A common proposition for design engineers in predicting shape variation is to move the entire set of processes used in manufacturing into the hands of the designer. However, this approach has several major practicality issues that make it unfeasible, even as a ‘service’. These issues include the associated cost of replicating the flow on the designer's desktop, the runtime and data-volume explosion, and the difficulty of trying to ensure that manufacturing changes—such as in RET and Optical Proximity Correction (OPC)—are reflected in the design space. Further, designers may not have sound lithographic judgement based on RET/OPC information and there is currently no way to tie OPC tools to those for electronic design automation (EDA). Further, addressing these issues would make it still more difficult to keep recipes and lithographic settings confidential, especially when working with a foundry.

In short, the current DFM solutions do not meet the sub-100nm DFM requirement, whether based on design rules or attempts to have designers use OPC tools. A genuine DFM solution will have to be provided through new, disruptive modeling technology, rather than evolutionary stretching of old technologies to accurately predict the design's sensitivity to shape variations throughout the design process.

Model-based design manufacturability checker

The first step to solving the DFM problem is to capture the entire manufacturing flow with a fast, accurate and secure model that predicts the behavior of the manufacturing flow without presenting all the details. Designers need to apply a Design Manufacturability Check (DMC) model that will find problems based on their specific target fab. At 90nm and below, variability is inherent to fabrication and severely affects the performance of the design.6 Thus, a model that very rapidly predicts Critical Dimension (CD) variation on chip—without dealing with the clutter of the manufacturing process and RET flow—would provide design and manufacturing teams with invaluable early insights and allow designers to avoid these problems.

The Clear Shape model characterizes process performance and predicts the final results without having to run the RET flow. Unlike a traditional lithography simulation model that captures only the behavior of the lithography system, models the entire manufacturing process, including the retargeting, assist-feature, phase-shift mask (PSM), OPC and lithography effects (see Figure 1).

Figure 1. Clear Shape models the entire manufacturing process.
 

The Clear Shape solution consists of a set of tools that are fast enough to operate on the entire chip in hours instead of days (as with current DFM tools based on OPC engines). Figure 2 shows the prediction accuracy of the model on a 65nm metal 2 layout. Note the excellent correlation of post-OPC contours and Clear Shape prediction, even in the presence of non-linear effects such as retargeting.

Figure 2. The Clear Shape model shows excellent correlation with post-OPC contours on a 65nm Metal 2 layout.

While successful OPC at nominal conditions does not guarantee that the design is immune to process variations, Figure 3(a) shows the contours and how they conform very well with the drawn shapes, especially in one-dimensional regions. Although rounding effects can be seen on two-dimensional structures, the patterns are very solid at nominal condition from the printability point of view.

Analyzing the integrated circuit at different defocus conditions detected a conflicting short and pinch off-target: see Figure 3(b). These are likely secondary impacts from the OPC effects related to the high two-dimensionality of the local corner. However, the slight difference in design produced opposite effects (short versus pinch) in the final off-target results. While it is unlikely that a design rule could be written to simultaneously solve both of these problems, using the Clear Shape model to simulate directly from the drawn layout predicts both short and pinch hotspots at different process conditions. That enables the designer to address the issue before tape-out. For example, Figure 4 shows the contour prediction at different process points of a 65nm poly gate. Here, no catastrophic pinching or bridging is detected, but there are enough variations on the timing-sensitive gate to create a potential parametric failure.

Figure 3. (a) The contours of a 65nm Metal 1 layout conform to drawn shapes at nominal conditions. (b) Detection of a hotspot at defocus conditions.
 
Figure 4. Contour predictions of 65nm poly gate show no catastrophic pinching or bridging, with detail at right.
 
Conclusion

Evolutionary rule-based DFM checker tools are insufficient to produce all manufacturable designs. The Clear Shape solution to this problem is based on a technology that models the entire process flow. It provides fast, accurate, full-chip and manufacturability check well beyond traditional design rule checking. In addition, it is much faster than other proposed solutions based on OPC and lithographic simulation. This methodology reduces cycle time through manufacturing, improves yield, produces robust and high-yield designs across the process window, and widens that window.


Author
Philippe Hurat
Clear Shape
Sunnyvale, CA
Philippe Hurat has over 15 years of experience in the semiconductor and EDA industries in a broad range of technical and marketing roles. Before joining Clear Shape, he held key positions at Synopsys where he was responsible for marketing the DFM and TCAD product lines. Prior to that, he held various technical marketing, strategic marketing, product marketing and applications engineering positions at Numerical Technologies, Cadabra Design Automation, and Compass Design Automation. In addition, he has authored or co-authored numerous technical papers and patents related to design for manufacturing and physical design optimization.