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Micro/Nano Lithography

Building better micromirror arrays for laser mask writers

A layer-transfer process can be used to make the very-flat silicon micromirror arrays that may be vital to producing masks for future lithography and direct-writing systems.
28 April 2006, SPIE Newsroom. DOI: 10.1117/2.1200603.0146

Making the masks necessary to perform lithography on semiconductor wafers with minimum feature sizes of 65nm or less is a slow and expensive process. Spatial light modulators (SLMs) are used in commercial deep-ultraviolet (DUV) laser-pattern generators to meet the requirements of such processes.1 These systems can generate blank line widths at the mask of 260nm, with an overall critical-dimension uniformity of 7nm (3σ) and a short write time.1 Figure 1 shows even smaller patterns: 150nm dense chrome lines.

Figure 1. Shown are 150nm dense patterns (chrome mask).

The performance of such generators is enabled by various features of the SLM. Each mirror can be deflected to various angles, rather than simply being in one of two positions, with a repetition accuracy of 1nm. The mirrors are very flat, with a peak-to-peak planarity of a few nanometers. The chip bearing the mirror array is very flat too, so the mirrors are well aligned.2 Also, the mirrors move fast enough to sustain a frame rate of 2kHz.

Fabrication of the SLM chip starts with a CMOS (complimentary metal-oxide semiconductor) backplane that has been planarized using chemical-mechanical polishing to yield a suitably flat surface. The mirror array is built using a micro-electromechanical systems (MEMS) process that uses a 450nm-thick layer of an aluminium alloy sputtered onto a planarized polyimide layer. This layer is removed in an oxygen plasma once the metal has been patterned.

The mirror technology has already been optimized for its optical, mechanical, and electromechanical properties,3 and is now in small-volume production at Fraunhofer IPMS. We are now developing the technology to support the future requirements of laser mask-writing technology and similar applications, such as printed-circuit-board manufacturing. We're also investigating novel hinge materials to improve deflection accuracy and stability—trying to achieve high-precision static deflections—and to increase the reflectivity of the mirror to reduce the laser-induced damage caused by photon absorption. This is important for applications requiring high laser intensity and/or very high-energy photons. Here we describe our work on the hinge: our work on mirror coatings is covered in recent papers.4,5

Integrating MEMS technology with CMOS processes restricts process options, such as temperature regimes, and material choices. One promising approach to improving the mechanical properties of the hinges is to use mono-crystalline silicon. This has high elasticity offers a high surface quality when polished, and can be used to make highly planar mirrors because of its lack of stress gradients. Our approach to using silicon as the mirror material was based on a layer-transfer technology. We chose to glue a silicon-on-insulator (SOI) donor wafer to the CMOS backplane at low temperature.

The key process steps were developed using a wafer with a passive array of electrodes. The surface materials and topology were kept similar to a corresponding CMOS wafer. We started with the wafer containing the electrode array, and then made the mirror posts that determine the gap between the electrodes and the silicon mirror after wafer bonding. Next the wafer was coated with a resist layer and patterned so that thin stripes remained on the electrodes while any resist on top of the mirror posts was removed.

In the next step, an unpatterned 300nm-thick SOI wafer is bonded to the mirror posts on the electrode wafer using a thermo-compression process at 270°C. The way the resist reflowed at 250°C ensured good contact and a uniform bonding. After this, the handling layer of the SOI wafer and its buried-oxide layer were removed. Holes were then etched into the thin silicon layer above the mirror posts, aluminium deposited to form plugs—ensuring both electrical and mechanical contact—and, finally, the 300nm-thick SOI layer patterned and resist removed in an oxygen plasma. Figure 2 shows an SEM image of the resultant array of 240 × 281 silicon micromirrors, and the aluminium plug.

Figure 2. Array of silicon micromirrors, with inset detail of the post.

The mirror array has a surface planarity of 0.8 ± 0.1nm, making it suitable for DUV operation. A deflection of 48nm, sufficient to achieve a black pixel with 193nm illumination, can be achieved with an addressing voltage of 15V. Figure 2 shows that static deflection for more than an hour did not reveal any measurable drift or imprinting.

We've shown that we can use a layer-transfer process to make silicon micromirror arrays, and that it is compatible with CMOS substrates. The mirrors are very flat and do not show any drift or imprinting upon static deflection. This work paves the way for the development of large-scale micromirror arrays for high-quality laser-mask writing, direct writing, and other applications, such as printed-circuit-board manufacturing.

Figure 3. Static deflection for more than one hour does not show any drift or imprinting.

Harald Schenk, Michael Wagner, and Thor Bakke 
Fraunhofer IPMS
Dr. Harald Schenk is deputy director of the Fraunhofer Institute for Photonic Microsystems. He has more than eight years' experience in developing micromirror technology and micromirror arrays. He is also a member of the Program Committee for the MOEMS Display and Imaging conference and author/co-author of more than 50 papers.