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SEMATECH pushes extreme UV lithography forward
The SEMATECH EUV program is tackling the roadblocks to commercialization, but there are still several key gaps to fill.
10 April 2006, SPIE Newsroom. DOI: 10.1117/2.1200602.0079
Before extreme ultraviolet lithography (EUVL) can be used for high-volume manufacturing (HVM) of silicon integrated circuits built with feature sizes of 45nm and 32nm, critical issues must be resolved. At SEMATECH we are trying to provide industry with the infrastructure needed for commercialization: this includes developing mask-making technology, long-life high-brightness EUV sources, and EUV resists.1 The components that need to be in place for EUVL to succeed are shown in Figure 1. First is a light source that produces 13.5nm-wavelength radiation: the light propagates through a reflective projection-optics system with a 4× reduction factor,2–5 used to project circuit patterns from a reflective master mask onto EUV resist-coated wafers. Here we look at the latest developments in key areas that are critical to the development of a full production system of this kind.6
Figure 1. A schematic of the main components of an EUV lithography system. Click on image to enlarge.
EUV masks need to be defect-free throughout their useful lifetime. They are made with low thermal expansion (LTEM) substrates7 coated with layers of molybdenum and silicon to form a EUV Bragg reflector, after which a defect-free absorber is added to produce the blank mask.8 The desired circuit layout is transferred by etching away the absorber in selected areas, after which the mask can be used for imaging. Blank masks for HVM have to be defect-free within a quality area of 142×142mm. To achieve a 70% yield of defect-free mask blanks, the average density of defects larger than 25nm must be less than 0.003defects/cm2. For pilot manufacturing, an intermediate goal must be met by the end of 2007: 0.01defects/cm2 with 40nm defects.
Over the last two years, progress has been made at SEMATECH's Mask Blank Development Center (MBDC) in Albany, NY, in developing a defect-free Mo/Si multilayer deposition technology (see Figure 2). The number of defects added by the multilayer deposition process has been reduced by two orders of magnitude, for a total defect count as low as 18 for defects over 70nm.3 The development of these processes means the majority of defects now come from the substrate, rather than being added during the multilayer deposition. These substrate defects—dominated by pits and scratches—are the most critical to reduce.
Figure 2. SEMATECH's progress in reducing defects in mask blanks.
Minimizing the number of sub-100nm particles on the substrate requires a thorough analysis of their chemical composition, as this helps identify their source. This analysis is also critical for choosing the right cleaning and repair techniques. Significant progress has been made in this area and recent blanks show no particles larger than 43nm after substrate cleaning.3
Another issue is transportation. Conventional masks are protected during handling and shipping with a thin membrane called a pellicle that is transparent to the imaging light. This approach cannot be used for EUV as there is no transparent material available at this wavelength.To get around this problem a ‘pseudo pellicle’, removed only for inspection and imaging, was proposed and implemented.2 SEMATECH then set up an automated testing capability and demonstrated that less than 0.20 particles were added in a complete handling cycle for particles measuring 54–90nm in size.3 In addition to demonstrating the utility of the pseudo-pellicle idea, the testing facility is proving valuable to industry in its own right.
To ensure the masks are defect-free, they need to be checked. However, it is not yet clear whether the EUV mask blanks need to be inspected for printable defects at the EUV wavelength—using a technique called actinic inspection—or whether current visible inspection tools are sufficient. To help answer this question, SEMATECH developed an actinic defect-inspection tool capability at the Advanced Light Source (ALS) laboratory in Berkeley. The tool operates in two ways: in defect-scanning mode, it uses dark- and bright-field signals to locate defects and to correlate them with defects found using visible inspection tools; in microscope mode, defects down to ∼ 70nm (corresponding to ∼ 17nm at the wafer level) can be reviewed.6
EUV light is emitted by a hot plasma of materials such as Xe, Sn, and Li,5 generated by an electrical discharge or by laser heating. Discharge-produced plasma (DPP) or laser-produced plasma (LPP) source candidates for HVM lithography need to meet demanding EUV power and cost of ownership (COO) requirements. Progress has been made in the EUV power of DPP sources (see Figure 3), which is now close to 50% of the HVM power requirement of 115W at the intermediate focus (IF).
The average peak power of commercial EUV sources at their intermediate focus.9
However, continuous high-power operation needs to be demonstrated with more stable sources and longer lifetimes. Source collectors (the mirrors that collect the produced EUV light) do not currently last very long, and the collectors need to be protected from high-energy ions without reducing EUV power at the intermediate focus. The same is true when filtering non-EUV radiation, (i.e., out-of-band radiation).
There are other issues too. As the source power increases, efficient cooling of the source collectors becomes critical. Also, the industry needs to understand how the source target materials, such as Sn and Li, can be handled safely, reliably, and cost-effectively in a manufacturing environment.
These challenges are far from trivial. For one type of source to succeed, the industry needs to focus on the most promising solution. SEMATECH's EUV program is providing understanding of source limitations and high-power source feasibility combined with candid assessments of the industry status and outlook.10 In addition, we continue to run a benchmarking program for different source technologies that enables the industry to compare performance results from different sources using standardized metrology equipment and methods.
On top of all this, the operational lifetime of the EUV optical system must be greater than 5 years (or 30,000 light-on hours). The optics must also last this long. The optical system can currently run for several hundred hours, close to the 1,000-light-on-hour specification for the first generation of tools. SEMATECH's EUV program has recognized the importance of an interdisciplinary network among surface scientists, optics experts, and optics lifetime testing facilities to address the problem11, but it has taken the industry some time to realize that it could not engineer its way out of it. A successful solution will require fundamental understanding of thin film and interface properties on the nanoscale level, and of photon- and electron-induced processes on the optical surfaces in question.
The primary challenge for EUV resists is that they must simultaneously meet the specifications for resolution, line-edge roughness (LER), and speed.1 SEMATECH has enabled early access to small-field exposure systems—Micro Exposure Tools (MET)—that are critical for resist development. The program now has two such tools. The first is a synchrotron-based MET at the ALS in Berkeley with a variable illumination capability and an optical resolution down to 12–15nm. In addition, since September 2005, a MET tool with a DPP source at the EUV Resist Test Center (RTC) in Albany has provided an integrated EUV resist-evaluation environment. The resolution of these METs is still significantly better than the best-resolving EUV resist available. In fact, resist development is the one EUV technology component that most needs a significantly-increased development effort by suppliers to extend current chemically-amplified resists (CARs), and by universities and research institutions to develop new non-CAR platforms.
The SEMATECH EUV program is a key enabler of EUV infrastructure development. It has stimulated the development of defect-free mask blanks and the testing of resist materials. However, development is still needed: particularly in EUV sources and resists.
The work in this article is the accomplishment of many people, including SEMATECH employees and assignees; employees of the SEMATECH member companies; and researchers at the companies, research institutions, and universities with which SEMATECH is collaborating.
Lithography Department, SEMATECH
Infineon Technologies North America
San Jose, CA
Stefan Wurm is the program manager for EUV Lithography Strategy at SEMATECH. He is an Infineon assignee and has been at SEMATECH since September 2003. He joined Infineon in 1996 and has held several positions in technology development. He came to SEMATECH from a three-year assignment as Infineon EUVL project manager at the EUV LLC in Livermore, CA. He received his doctorate in physics from the Technical University in Munich, Germany.
Lithography Department, SEMATECH Freescale Semicondutors
Kevin Kemp is the Director of the Lithography Division at SEMATECH. He is a Freescale assignee, and has been at SEMATECH since April 2002. He joined Freescale in 1989 and has held positions in lithography research and development and engineering management. He also spent four years as engineering manager with FSI International's Microlithography division. He has a PhD in electrical engineering from Clemson University, and bachelors and masters degrees from the University of Natal in Durban, South Africa.
International Technology Roadmap for Semiconductors,
3rd International Extreme Ultra-Violet Lithography (EUVL) Symposium,
Miyazaki/Japan, Nov. 2-4 2004. http://www.sematech.org/meetings/archives.htm
4th International Extreme Ultra-Violet Lithography (EUVL) Symposium,
San Diego, Nov. 7-9 2005.
4. S. Wurm, C. W. Gwyn, K. Suzuki, EUV Lithography,
ch. 8, CRC Press, Boca Raton, FL, (K. Suzuki, ed.), 2nd ed., 2005.
5. V. Bakshi,
EUV Sources for Lithography,
, SPIE Press, Bellingham, WA, 2006.
6. S. Wurm, Overview of SEMATECH's EUV Program,
Proc. SPIE 5835,
7. SEMI P37-1102,
Specification for Extreme Ultraviolet Lithography Mask Substrates,
Semiconductor Equipment and Materials International, San Jose, CA, 2002.
8. SEMI P38-1103,
Specification for Absorbing Film Stacks and Multilayers on Extreme Ultraviolet Lithography Mask Blanks,
Semiconductor Equipment and Materials International, San Jose, CA, 2003.