 Astronomy
 Biomedical Optics & Medical Imaging
 Defense & Security
 Electronic Imaging & Signal Processing
 Illumination & Displays
 Lasers & Sources
 Micro/Nano Lithography
 Nanotechnology
 Optical Design & Engineering
 Optoelectronics & Communications
 Remote Sensing
 Sensing & Measurement
 Solar & Alternative Energy
 Sign up for Newsroom EAlerts
 Information for:
Advertisers




Micro/Nano Lithography
Optimizing electron beam lithography in the nanometer range
Vladimir Zlobin
A mathematical model for electron beam nanolithography allows the exposure time of nanostructure arrays to be predicted for more costeffective manufacturing.
13 April 2006, SPIE Newsroom. DOI: 10.1117/2.1200602.0069
The constant increase in component density in silicon chips has been a steady trend in microelectronics over the last 50 years. Gordon Moore predicted in 1965 that the number of components per chip would double every year.^{1} Though the formulation of the Moore's law has since been corrected,^{2} the tendency for exponential increase of component density in the chip remains. The driving force behind this trend has been the improvement in the basic technical characteristics and economics of microelectronic devices through the reduction of their feature sizes. Vast intellectual and material resources are focussed on increasing the resolution of lithography as the cornerstone technology of modern electronics, optoelectronics, and micromechanics. New technological developments in the transition to nanoscale devices have advanced these efforts even further.
Both electronbeam lithography with Gaussian sharpfocused beams and projection electronlithography systems with a resolution of a few nanometers are suitable for creating nanoscale devices. The first may be used for direct writing and fabrication of master masks, however the scan speed decreases dramatically with beam diameter. Since increasing the resolution and the throughput are important problems in electronbeam nanolithography, we have developed a mathematical model of the electronbeamlithography processing of nanostructures to solve them. The model takes into account electron diffraction, the aberration of the lenses, and electronresist interaction.^{3} It also allows the prediction of the exposure time of nanostructure arrays, and the optimization of the minimum feature size versus the speed of exposure process.
The theoretical limit of the resolution of an electrooptical system is defined by the diffraction of the electron, having wavelength λ [nm]=1,2U^{1/2}_{0}[V], and the spherical and chromatic aberration of the electron lenses, mainly the objective. For a system with a Gaussian beam, the beam diameter d is defined by:^{4}
where I is the beam current, B is the brightness of the electron source, α is the convergence halfangle of the electron beam, C_{c} and C_{s} are the chromatic and spherical aberration coefficients of the final lens, and E_{0} and ΔE are the average energy and the energy spread of the electrons in the beam.
As shown in Figure 1, the influence of chromatic aberration prevails for a highbrightness electron gun with a point source when (i/B) << (1.22λ)^{2} , as in modern systems with fieldemission guns. Taking into account only diffraction and chromatic aberration, the minimum beam size and the dependence of a beam current on its diameter may be deduced from (Equation 1):
Figure 1. Diameter of the electronbeam lithographic tools as a function of beamconvergence half angle. 1: Wide source. 2: Point source. E_{0} = 50 keV, ΔE = 1.5 eV, C_{c} = 40 mm, C_{s} = 60 mm.
A few possibilities exist for increasing the resolution and beam current: increasing the beam energy and the brightness of the electron gun, reducing the aberrations in the lenses and reducing the energy spread of electrons in the beam. The designers of electron beam systems use all these techniques.
In recent years the accelerating voltages have increased, from 20–25 to 50–100kV through the transition to thermal field ZrO/W cathodes. This has raised the brightness of the electron guns by a factor of a hundred. In addition, this has reduced the beam diameter to 4 – 5nm and increased the current density to 2000–4000 A/sm^{2}, as\ demonstrated by Gaussian beam and vector scanninglithography tools such as Jeol's JBX9300 and Leica's VB6 UHR.
To minimize the cost of manufacturing one chip with evermoreexpensive higherresolution equipment, the productivity of the tool has to increase, so throughput is the second basic parameter that has to be optimized in lithography tools. The minimum exposure time t_{min} of a layout in the electron lithography systems of any type is determined by simple expression:
where S is exposure area, and D and I are the exposure dose density and beam current respectively. For a point source, the maximum beam current is proportional to the fourth power of its diameter d (3). This gives the dependence of exposure time on the beam diameter as:
However the dose increases with the reducing feature size as d^{26}, so the reduction of a feature size by an order of magnitude will increase the exposure time by 10^{6}, all other factors being equal. This relation (Equation 5) is the most serious obstacle to the use of lithography tools with a scanning beam in the nanometer range. The alternative is to move to projection electron lithography, which allows the simultaneous exposure of elements over a large area with a high beam current.
Electron lithography is a well established technology allowing resolutions below 20nm, but the productivity of tools with a sharply focused beam quickly falls with the reduction in the beam diameter. Nevertheless, it is a unique system for manufacturing master masks for electron, optical, imprint, and xray nanolithography, and also for direct lithography. This mathematical model allows the throughput to be balanced with the beam diameter to achieve the most cost effective manufacturing process.
Author
Vladimir Zlobin
AllRussian Electrotechnical Institute
Moscow
Russia
Vladimir Zlobin graduated from the Moscow State University Physics Department in 1971, has a PhD in physical electronics, and now is the head of electron microscopy and electron beam lithography group at the AllRussian Electrotechnical Institute. His research experience includes electronbeam testing and lithography for integral semiconductor devices, which he has described in over 80 scientific papers. Dr Zlobin is an SPIE member, and has written three papers for SPIE conferences.


