This PDF file contains the front matter associated with SPIE Proceedings Volume 10584, including the Title Page, Copyright information, Table of Contents, and Conference Committee listing.

The progression of projection printing systems is shown and discussed. We first showed the path of improvement of resolution and depth of focus through NA increase, wavelength and k1 reductions through resolution enhancement techniques. Lens imaging lens went through all-reflective, to dioptric, catadioptric, then back to all reflective systems. Systems of single optical axis moved to multiple optical axes, then single axis, and is coming back to multiple axes. Full-wafer field systems progressed to step-and-repeat systems, then stayed at step-and-scan. 1X systems gave way to reduction systems. Pellicleless systems improved to pellicle-essential systems and possibly back to pellicleless systems. We will pick the notable pacesetters in this long list of innovations to guide us into innovations in the future to sustain the growth of the industry. The lesson learned were applied to EUV lithography and nanoimprint lithography. Two non-resolution-centric systems are shown to show that there are other opportunities in lithography than just stubbornly pursuing Moore’s law of scaling.

As the pitch approaches the 10nm node, in order to meet current and future patterning challenges, high resolution techniques are required, complementary to extreme ultraviolet lithography (EUVL) for high volume manufacturing of nanodevices. These complementary techniques should have the following specifications: 1) High patterning resolution, below 10 nm; 2) capability of patterning in 3D; 3) sufficient wafer-scale throughput; 4) the capability of closed loop metrology and 5) the capability of measuring nondestructively through layers, for alignment and overlay applications.

Scanning probe microscopy (SPM) has shown a great degree of nano-scale control, and a great potential to address the challenges found in metrology. There has been a broad development of SPM-based methods for patterning and metrology purposes although its exploitation for technological applications is limited due to the modest throughput of scanning probe based techniques. In this article we present experimental results that include the proof-of-principle of using SSURFM to locate existing buried nanopatterns (lines of 50 nm) and subsequently using our patterning technology to manufacture nanocontact holes aligned to the existing buried lines. In combination with the high throughput parallel scanning probe, this example demonstrates the great potential and the suitability of the group of technologies developed at TNO (consisting of the patterning and the subsurface nanoimaging) for alignment and overlay, especially through opaque layers.

The search of novel tools controlling the physical and chemical properties of matter at the nanoscale is crucial for developing next-generation integrated systems, with applications ranging from computing to medicine. Here, we show that thermal scanning probe lithography (t-SPL) can be a flexible tool for manipulating with nanoscale precision the surface properties of a wide range of specifically designed systems. In particular, we show that via t-SPL, we pattern nanoscale chemical patterns on polymeric substrates, which are then used to specifically bind extracellular matrix (ECM) proteins to the polymer surface. We demonstrate that the concentration of immobilized proteins can be controlled by varying the tip temperature, so that nanoscale protein gradients can be created. On a different system, we show that, by performing t-SPL on a thin film magnetic multilayer, in an external magnetic field, we are able to write reversibly magnetic patterns with arbitrarily oriented magnetization and tunable magnetic anisotropy. This demonstrates that t-SPL represents a novel, straightforward and extremely versatile method for the nanoscale engineering of the physicalchemical properties in a wide variety of materials.

Cost-effective generation of single-digit nano-lithographic features could be the way by which novel nanoelectronic devices, as single electron transistors combined with sophisticated CMOS integrated circuits, can be obtained. The capabilities of Field-Emission Scanning Probe Lithography (FE-SPL) and reactive ion etching (RIE) at cryogenic temperature open up a route to overcome the fundamental size limitations in nanofabrication. FE-SPL employs Fowler-Nordheim electron emission from the tip of a scanning probe in ambient conditions. The energy of the emitted electrons (<100 eV) is close to the lithographically relevant chemical excitations of the resist, thus strongly reducing proximity effects. The use of active, i.e. self-sensing and self-actuated, cantilevers as probes for FE-SPL leads to several promising performance benefits. These include: (1) Closed-loop lithography including pre-imaging, overlay alignment, exposure, and post-imaging for feature inspection; (2) Sub-5-nm lithographic resolution with sub-nm line edge roughness; (3) High overlay alignment accuracy; (4) Relatively low costs of ownership, since no vacuum is needed, and ease-of-use. Thus, FE-SPL is a promising tool for rapid nanoscale prototyping and fabrication of high resolution nanoimprint lithography templates. To demonstrate its capabilities we applied FE-SPL and RIE to fabricate single electron transistors (SET) targeted to operate at room temperature. Electrical characterization of these SET confirmed that the smallest functional structures had a diameter of only 1.8 nanometers. Devices at single digit nano-dimensions contain only a few dopant atoms and thus, these might be used to store and process quantum information by employing the states of individual atoms.

Multicolor photolithography using visible light holds the promise of achieving wafer-scale patterning at pitches on the 10 nm scale. Although substantial progress has been made on multicolor techniques, a number of challenges remain to be met before the ultimate resolution of these methods can be reached. These challenges include the development of improved materials, creation of high-quality thin films, transitioning to exposure schemes that rely completely on linear absorption, scaling up to large-area patterning, and developing methods for effective pattern transfer. This paper discusses the state of the art in multicolor photolithography, presents some of the most recent advances in this field, and examines the prospects moving forward.

Over the past few decades, the semiconductor industry has been employing size shrinkage as the most efficient method to reduce production cost in order to fit more and more transistors on one unit area. Each size shrinkage has been categorized as either node or generation by the theoretical gate length of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). In the advanced node, such as the sub-10nm node, size shrinkage is not applicable due to the physics limitation of 193nm immersion lithography. Therefore, alternative methods, extreme ultra violet lithography (EUV) and multi-patterning solutions based on 193nm immersion lithography, are attracting significant attentions in research and development across the industry. Among the various patterning techniques, the front-runner is self-aligned multiple patterning (SAMP). This technique uses the sidewall spacer formation as a transferable pattern and achieve pitch halving purpose. By repeating this technique, the pitch halving can be executed countless times, theoretically; this gives this technique an advantage over other techniques. However, due to the device design and sidewall formation in both sides, an additional line cut step is required to be performed to fulfill the requirements of isolation and N/P boundaries. The most challenging pattern in the line cut step is the single line cut without defect formation.

Patterning of the resist features down to 10 nm node is crucial for futuristic integrated circuits (ICs) technology advancements. In this regard, we design and developed a novel hybrid non-chemically amplified resist (n-CAR) i.e. MAPDST-co-ADSM (where MAPDST = (4-(methacryloyloxy)phenyl) dimethylsulfonium trifluoromethanesulfonate and ADSM = (acetyldibutylstannyl methacrylate)) for high-resolution Helium Ion (He⁺) Beam Lithography (HIBL) studies. The developed resist exhibits the high sensitivity toward Helium ion radiation and patterned sub-15 nm features at the dose ∼50 μC/cm² onto negative tone resist formulation. In order to recognize the critical dimension (CD), the resist thin films were analyzed for single pixel exposure dose analysis at He⁺ exposure dose ranging from ∼30 pC/cm to ∼100 pC/cm. These investigations apparently reveal that 10 nm single pixel line features of the MAPDST-co-ADSM resist is patterned with the dose ∼50.48 pC/cm. The improved patterning resolution of the resist down to 10 nm is due to the inclusion of hybrid tin sensitizer in the resist structures. The MAPDST-co-ADSM showed coherent line edge roughness (LER) and line width roughness (LWR) values for 15 nm lines features as ∼1.67±0.27 nm and ∼2.20 nm respectively.

Monte Carlo-based simulation technique is a standard method for statistical analysis and modelling of stochastic processes; such as noise in circuits, carrier transport and study of ion implantation/interaction/trajectory on materials for integrated circuits. Thus Monte Carlo ion trajectory simulation for MAPDST-co-ADSM resist formulation showed that the negligible (∼0.5%) target damage and recoil generation (atom displacement) of total energy delivered to the system (MAPDST-co-ADSM/Si) in novel HIBL exposure due to much larger stopping power of He⁺ ion and low proximity effect.

Directed Self Assembly (DSA) of block-copolymers (BCPs) is considered as a cost-effective solution to extend the performances of conventional lithography. In this work, we propose a smart surface modification technique to precisely control the surface affinity of guiding template used in the DSA graphoepitaxy process flows. The presented method consists in the UV irradiation of copolymers brushes in order to locally tune their surface affinity. By this way, we are able to differentiate the surface affinities of guide sidewalls (PMMA-attractive) and guide bottom (non-preferential affinity). A complete DSA-module is demonstrated and implemented on a 300mm integration flow dedicated to the creation of silicon nanowires-like transistor.

CH (Contact hole) patterning by DSA (Directed Self-Assembly) of BCP (Block Copolymer) is still attracting interest from the semiconductor industry for its CH repair and pitch multiplication advantages in sub-7nm nodes. For several years, extensive studies on DSA CH patterning have been carried out and significant achievements have been reported in materials and process optimization, CMOS integration and design compatibility and advanced characterization [1-4]. According to these studies, if a common agreement was clearly made for the use of PS-b-PMMA material as a potential candidate for DSA CH patterning integration in advanced nodes, the associated guiding template material was not yet selected and is still under investigation. Whereas the most reported guiding template materials for DSA PS-b-PMMA CH patterning are organic-based (resist or organic hard mask), we propose in this work to investigate a DSA process based on inorganic template material (silicon oxide based). Indeed, this latter offers some advantages over organic template: better surface affinity control, higher thermal stability during BCP self-assembly annealing, easier 3D-morphology imaging of DSA patterns and the possibility of wafer rework after the DSA step. The inorganic template based DSA process was first optimized using the planarization approach [5]. We demonstrated that the silicon oxide thickness should be properly adjusted to allow a good control of the BCP thickness over different guiding template densities. Afterwards, we compared the DSA performances (critical dimension: CD; CD uniformity: CDU, contact misalignment and defectivity) between both inorganic and organic template approaches. Equivalent results were obtained as shown in Figure 1. Finally, we demonstrated that inorganic template allows the rework of DSA wafers: similar CD and CDU for both guiding and DSA patterns were obtained after 3 cycles of rework (Figure 2).

Since the 1960's, e-beam direct write has been left standing at the altar of new nodes, hoping to cross the threshold into the fab... And it's not because optical is for fab lithographers what an Alfa Romeo was for The Graduate.* It has to do with the economics of Moore's Law and what it takes for novel patterning technologies to meet its criteria. The barriers to e-beam making it into the fab have been a complex interplay of economics, technology, and the social psychology of the fab. This keynote dovetails the author’s plenary talk, showing why this is the case. So, what’s kept e-beam in play over the decades? As Frank Abboud pointed out so well in his 2018 plenary, investments in e-beam for direct-write have had the side benefit of making feasible the mask making technology needed for optical. So, the same question stays in play: Will e-beam cross the threshold to the fab after all these years? After all, that Alfa Romeo has grown to be very expensive over the years. The presentation will address these questions and conclude with an assessment of the economics needed to take Novel Patterning Technologies across the threshold to become new production realities.

* The title is an homage to the 1966 movie The Graduate

Mapper has installed its first product, the FLX–1200, at CEA-Leti in Grenoble (France). This is a maskless lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. The FLX-1200, containing 65,000 parallel electron beams in a 13mm x 2mm electron optics slit, is capable of patterning any resolution and any different type of structure all the way down to 28 nm node patterns. As of August 2017 the FLX-1200 has a fully operational electron optics column, including a 65,000 beam blanker. In this paper the latest technical achievements of the FLX-1200 have been described: beam current is at 80% of FLX-1300 target (85 minutes per wafer). For 42nm hp dense lines a CDu of 8nm 3σ and a LWR of 5nm 3σ has been demonstrated. The stitching error is 12nm μ+3σ and regarding overlay a 15nm capability demonstrated, provided matching strategy is implemented and the mirror map is calibrated.

Multi-beam mask writer MBM-1000 is developed for N5 semiconductor production. It is designed to accomplish high resolution with 10-nm beam and high throughput with 300-Gbps blanking aperture array (BAA) and inline real-time data path. It has better beam resolution than EBM-9500 and has higher throughput at shot count more than 500 Gshot/pass. To further improve patterning resolution, pixel level dose correction (PLDC) is implemented to MBM-1000. It performs dose contrast enhancement by dose modulation pixel by pixel. Correction efficiency of PLDC is evaluated for linearity correction by simulation with threshold dose model. It is concluded that PLDC corrects linearity efficiently even without extra dose modulation, and improves dose margin with additional dose modulation of 140%.

Directed self-assembly (DSA) of block co-polymers (BCPs) is a next-generation lithography technique that shows promise for extending Moore’s Law into the 10 nm regime and below. The minimum size of the features that can be produced by BCPs is controlled by the interaction parameter (chi) and the degree of polymerization (N). We have developed silicon containing BCPs for sub-20 nm line-and-space lithography. These BCPs were synthesized by living anionic polymerization, thermally annealed in thin films between neutral layers to generate the requisite perpendicular orientation [1, 2]. The silicon-containing blocks provide excellent development contrast under both oxidizing and reducing reactive ion etching (RIE) conditions. The developed patterns work well as masks for transfer of the developed patterns into useful substrate materials [3]. Through optimizing the design of the block copolymers and the “hybrid” DSA process [1], we have now obtained 10 nm full pitch gratings. Recently we have studied silicon containing BCPs that incorporate a poly(2-vinylpyridine) block as a path to achieving still higher chi. For example, we have synthesized poly(4-pentamethyldisilylstyrene-block-2-vinylpyridine) (PDSS-b-P2VP) and found that this material has a chi parameter that is significantly higher than that of the BCP used for 10 nm lithography, meaning that even smaller feature sizes should be possible. Neutral top coats and cross-linked surface treatment layers were identified for PDSS-b-P2VP using the island and hole techniques that have been described previously [5]. We have succeeded in demonstrating 8 nm full pitch finger print patterns that are oriented perpendicular to the substrate. These are the smallest patterns we have managed to obtain in our system to date. 1. Blachut, G., et al. Chem. Mater (2016), 28 (24), 8951-8961. 2. Bates C. M., et al. Science (2012), 338 (6108), 775. 3. Azarnouchea, L., et al. J. Vac. Sci. Technol. B (2016) 34 (6), 061602/1-061602/10. 4. Lane A. P., et al. ACS Nano (2017), 11 (8), 7656-7665. 5. Maher, M. J., et al. Chemistry of Materials (2014), 26 (3), 1471-1479.

Acquiring three-dimensional information becomes increasingly important for the development of block copolymer (BCP) directed self-assembly (DSA) lithography, as 2D imaging is no longer sufficient to describe the 3D nature of DSA morphology and probe hidden structures under the surface. In this study, using post-DSA membrane fabrication technique and STEM (scanning transmission electron microscopy) tomography we were able to characterize the 3D structures of BCP in graphoepitaxial DSA hole shrink process. Different DSA structures of singlets formed in templated holes with different surface chemistry and geometry were successfully captured and their 3D shapes were reconstructed from tomography data. The results reveal that strong PS-preferential sidewalls are necessary to create vertical DSA cylinders and that template size outside of process window could result in defective DSA results in three dimensions. Our study as well as the established 3D metrology would greatly help to develop a fundamental understanding of the key DSA factors for optimization of the graphoepitaxial hole shrink process.

The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). The combined effect of LCDU and centroid jittering will be discussed and compared to a hole shrink process using atomic layer deposition and spacer formation. The learning from this case study can provide perspectives that may not have been investigated thoroughly in the past. By including more important elements during DSA process development, such as metal cut, the DSA maturit y can be further advanced and move DSA closer to HVM adoption.

Directed self-assembly (DSA) is one of the candidates for next generation lithography. Over the past years, many papers and presentation have been reported regarding DSA, and Tokyo Electron Limited (TEL is a registered trademark or a trademark of Tokyo Electron Limited in Japan and /or other countries.) also has presented the evaluation results and the advantages of each^1-6. Especially, the chemo-epitaxy process has advantages for the sub 20nm line & space patterns to apply to DRAM active area, Logic fin and narrow metal patterns. One of the biggest advantages of DSA lines is that the pattern pitch is decided by the specific factors of the block copolymer, and it achieves the small pitch walking as a consequence. On the other hand, the chemo-epitaxy process can be applied to the hexagonal close-packed arrangement holes⁶. Those holes are expected to be the patterns for DRAM storage.

In this report, we present the latest results regarding the defect reduction and LER improvement work regarding chemoepitaxy line & space pattern. In addition, we update the evaluation results regarding chemo-epitaxy hole pattern.

In recent years, Directed-Self Assembly (DSA) of block copolymers (BCPs) has gained relevance as a promising ‘bottomup’ technique to produce nano-lithographic patterns. To make DSA a reliable and robust technique, much of the research is focused on reducing defectivity and mitigating Line Edge Roughness (LER) and Line Width Roughness (LWR) of the pre-and post-etched polymer blocks. High roughness values often inhibit the smooth functioning of the transistors by constraining the electron flow through the spaced channels. It is thus crucial to develop novel modeling and simulations techniques for DSA to harness the full potential of this technique and thus meet the ITRS roadmap LER standards. In our recent work, we have outlined our CGMD framework and the subsequent etching methodology used to produce line space patterns created by lamellae forming polystyrene-block-polymethyl methacrylate (PS-b-PMMA) with periods of about 28 nm, on a patterned Liu-Nealey (LiNe) flow substrate. In this paper, we present a comparative study of the experimental LER / LWR calculations with our coarse-grained molecular dynamics (CGMD) simulation results. We employ highly parallelized supercomputing resources on a full-scale system with a detailed topographical substrate and exact matching of the BCP molecular weight. The simulations offer us a 3-D profile of the BCP domains and the subsequent resist pattern formed after etching, thus providing us with roughness estimates across the film thickness for three process stages: anneal, pre-etch and post-etch. Additionally, we also evaluate the edge morphology in the Fourier domain by generating power spectral density curves.

Material challenges for DSA Directed Self-Assembly (DSA) of block copolymers are accompanied by processing automation and throughput complexity for successful implementation into manufacturing. Our goal was to address the ability of this complementary lithography technique to offer streamlining with respect to thermal anneal time, lowering it from hours to minutes. In addition, the standard high temperature anneal at 250-270˚C was decreased to 160-180˚C with low levels of defects measured. This DSA requirement designed to shift to low temperatures for thermal annealing is primarily due to low Tg monomers incorporated into the copolymer blocks. Chemoepitaxy DSA processes can be simplified significantly with more potential as a result of lower Tg. 193i nm lithography continues to be utilized for creating guiding patterns that provide the ability to achieve pattern density multiplication and defect rectification. In parallel, we are providing additional chemistry enhancement techniques for feature sizes <10 nm by improving wet etch pattern transfer capability specifically targeted to mitigate pattern collapse. Dry etch process steps for removal of one block, followed by pattern transfer into hard mask layers are enhanced with the incorporation of monomers into the PS block of the high chi BCP with the intent to minimize issues due to low selectivity values. Etch selectivity has been increased from 3:1 to 6:1 with customizing the copolymer blocks. Due to the fact that the practical application of high chi DSA continues to face technical and material challenges in comparison to standard PS-b-PMMA process steps, BSI achieved low temperature and short time block copolymer annealing with the innovation of material enhancement chemistry. Specially designed materials have been developed to improve material robustness for pattern fidelity after etching multi-stack spin on layers for DSA requirements. We have enabled the extension of the functionality and capability of our block copolymer (BCP) materials in order to easily transfer a DSA flow into manufacturing in addition to no need for top-coat or solvent annealing to get perpendicular orientation as we reported before1.

Nanoimprint lithography, NIL, is gathering much attention as one of the most promising candidates for the next generation lithography for semiconductor. The advantages of NIL are simpler exposure system with no coat/dev track, single process step without SADP/SAQP, less design rule restriction, lower cost-of-ownership, compared with other lithography technologies. NIL working templates are made by the replication of the EB written high quality master templates. Fabrication of high resolution master templates is one of the key items. Since NIL is 1:1 pattern transfer process, master templates have to have 4 times higher resolution compared with conventional photomasks. Another key is to maintain the quality of the master templates in replication process. NIL process is applied for the template replication and this imprint process determines most of the performance of the replicated templates. Application of multi-beam mask writer, MBMW, to the NIL master template fabrication is very attractive. For a fine feature master template such as 1z nm node, shot count for writing with single beam tool will drastically increase and the writing time is estimated more than days. On the other hand, because of the parallel exposure principle, MBMW can write a master in a certain time for any feature size. In addition, MBMW is suitable for high resolution low sensitivity EB resist, which is evitable for fine feature master fabrication. We applied MBMW for the fabrication of full-field master of 1z nm node. In this presentation, we will be discussing master template fabrication process with MBMW and the performance of the template. We will also discuss the replication process with a high resolution master.

Nanoimprint lithography manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of widediameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity.

In this paper, we review the progress and status of the FPA-1100NR2 mask replication system and also discuss the methods used on wafer imprint systems to extend the life of a replica mask. Criteria that are crucial to the success of a replication platform include image placement (IP) accuracy and critical dimension uniformity (CDU). Data is presented on both of these subjects. With respect to image placement, an IP accuracy (after removing correctables) of 0.8nm in X, 1.0nm in Y has been demonstrated. Particle adders were studied by cycling the tool for more than 16000 times and measuring particle adders. Additionally, new methods, including on-tool wafer inspection and in-situ mask cleaning are being studied to further extend the replica mask life.

Technologies for pattern fabrication using imprint process are being developed for various devices. Nanoimpirnt lithography (NIL) is an attractive and promising candidate for its pattern fidelity toward finer device fabrication without using double patterning. Layout and process dependent hotspots become a significant issue for application in smaller pattern size device and, design for manufacturing (DFM) flow comprising imprint process has to be prepared. Focusing on resist drop arrangement method as a process margin expansion knob, simulated non-fill defect is compared with experimental result. Finally, drop arrangement-related hot-spot extraction/modification flow utilizing total NIL simulation is proposed.

Imprint lithography is a promising technology for replication of nano-scale features. For semiconductor device applications, Canon deposits a low viscosity resist on a field by field basis using jetting technology. A patterned mask is lowered into the resist fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are two critical components to meeting throughput requirements for imprint lithography. The first component uses a similar approach to what is already done for many deposition and etch processes. Imprint stations can be clustered to enhance throughput. The FPA-1200NZ2C is a four station cluster system designed for high volume manufacturing. The second component is resist fill. For a single station, throughput includes overhead, resist dispense, resist fill time, exposure and separation. Resist exposure time and mask/wafer separation are well understood processing steps with typical durations on the order of 0.10 to 0.20 seconds. To achieve a total process throughput of 20 wafers per hour (wph) for a single station (or 80 wph for a four station NZ2C system), it is necessary to complete the fluid fill step in 1.1 seconds. There are several parameters that can impact resist filling. Key parameters include resist drop volume (smaller is better), system controls (which can impact spreading after jetting), Design for Imprint or DFI (to accelerate drop merging) and material engineering (to promote drop spreading after dispense). In addition, it is mandatory to maintain fast filling, even for edge field imprinting. In this paper, we address the improvements made in DFI and material engineering. By optimizing the drop pattern layout and introducing a two component resist system that enhances resist spreading, throughputs of 80 wafers per hour or more are achieved.

In order to significantly reduce investment cost in lithography, nano imprint lithography (NIL) technology has aggressively been developed. Over the past few years, Toshiba, with the support of Canon and DNP, has developed NIL technology for the application of advanced memory devices and succeeded in yielding working devices at dimensions less than sub 20nm and beyond.

A production tool in a mask house for template and NZ2 in Si fab were installed and ready for production. The pattern shrinkage for memory has just restarted for new memory such as storage class memory called SCM. The SADP and SAQP ArF multi-patterning with a spacer process may not be applied to the next-generation memory process due to thermal problems in semiconductor materials. Low-cost single exposure with NIL will be an ideal process. All exposure tools should be considered for extendability across different device nodes as an economical strategy.

The next application of NIL will be extend from contact hole and dense pattern without multi patterning to 3D pattering such like damascene process and to outside of semiconductor devices. In this paper, the status of the nano imprint lithography for high volume manufacturing is discussed, along with key challenges that must be addressed. Moreover, proprietary technology of NIL such as 3D and wide field patterning is discussed.

Nanoimprint lithography manufacturing equipment utilizes a patterning technology that involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity.

In this paper, we review the advancements in the wafer imprinting system. To address high volume manufacturing concerns, an FPA-1200NZ2C four-station cluster tool is used in order to meet throughput and cost of ownership requirements (CoO). Throughputs of up to 90 wafers per hour were achieved by applying a multi-field dispense method. Mask like of up to 81 lots, using a contact test mask were demonstrated. The status of the tool overlay is discussed. Application of a High Order Distortion Correction (HODC) system to the existing magnification actuator has enabled correction of high order distortion terms up to K30. A mix and match overlay of 3.4 nm has been demonstrated and a single machine overlay across the wafer was 2.5nm.

A low cost alternative lithographic technology is desired to cope with the challenges in decreasing feature size of semiconductor devices. Nano-imprint lithography (NIL) is one of the viable candidates.^[1][2][3] NIL has been a promising solution to overcome the cost issue associated with expensive process and tool of multi patterning and EUVL. NIL is a simple technology and is capable of forming critical patterns easily. On the other hand, the critical issues of NIL are defectivity, overlay, and throughput. In order to introduce NIL into the High Volume Manufacturing (HVM), it is necessary to overcome these three challenges simultaneously.^[4]-[10] In our previous study, we have reported improvement in NIL overlay, defectivity and throughput by the optimization of resist process on a pilot line tool, FPA-1200 NZ2C. In this study, we report recent evaluation of the NIL performance to judge its applicability in semiconductor device HVM. We have described that the NIL is getting closer to the target of HVM for 2x nm half pitch.^[8]Defectivity level below 1pcs/cm2 has been achieved for the 2x nm half pitch L/S. The overlay accuracy of the test device is being improved down to 6nm or lower by introducing high order distortion correction.

Field-effect gating with solid dielectrics is the basis for modern electronics. Electrolyte gating, however, offers far higher polarizations. Indeed, electrolyte gating has been a breakthrough to electrically induce numerous phase transitions in solids [1,2,3]. These experiments are all done by dripping mm-size drops of the electrolytes onto the active sample. Compared to integrated circuit technology this approach seems “stone-age” to us. These drops are open to the environment, and allow only for limited purity and reproducibility. Heterostructure electronic circuits have, up to now, been comprised of solid materials only. We have opened this materials space to also include liquids. We demonstrate integrated liquid capacitors and integrated liquid field effect devices which are of equal quality or even outperform standard, bulk devices. This work will accelerate discoveries based on electrolyte gating by providing a new platform, and opens a new area to exploit liquid/solid interfaces in integrated functional devices with technological promise.

This paper address how additive manufacturing will revolutionize production and manufacturing industries, and ultimately determine the scope of what is possible to create. Due to its versatility, additive manufacturing will allow more efficient and cost-effective means of production, prototyping, and innovation. Additive manufacturing can create new parts and devices opening up new channels of change in emerging industries, such as microfluidics, medical, and dental. This evolution is equally as critical to private and public entities who desire a competitive edge over the manufacturing market, on both a national and global scale.

Digital Light Projection (DLP) technology, kinetic absorption framework, and software algorithms constituted our basis for the engineering and design aspect of a custom method of additive manufacturing capable of meeting the demands of mass production. With the barriers mentioned above in mind, this device was built to compensate in accuracy, precision (>1 micron) and speed in the resolution of all areas of X, Y, Z orientations, coupled with a large build volume. Strategic algorithms were inserted into object fabrication to achieve parts with a superior surface finish and dimensional accuracy at rapid speeds (<5 mins per 50mm). For validation, we contrasted surface finish against other additive manufacturing solutions available on the market, using the same STL file.

We compared the printed parts under a microscope and identified statistically significant differences (p>0.001) between the finished products. Our method proved superior regarding dimensional accuracy and surface finish. The technology and methods applied in this paper are a step toward key gains in manufacturing-decreased production time, more efficient use of materials and personnel, and cost efficiency. As additive manufacturing evolves, it continues to shape the way humankind thinks about production, creation, and manufacturing while simultaneously expanding research opportunities in ways never before possible.

Soft-lithography and nanoimprinting lithography have been critical in manufacturing 3D features with sub-20 nm resolution onto polymeric materials. However, methods for transferring 3D polymeric patterns (i.e. template) into silicon have relied upon the etch selectivity of the mask pattern during reactive ion etching, which in turn limits aspect-ratio, introduces shape distortions and introduces surface roughness via scalloping effects.

To tackle this problem, this paper demonstrates an electrochemical nanoimprinting process for single-crystal semiconductors for directly etching 3D features into silicon wafers without the need for templates or lithographical steps. It is shown that stamps made of porous catalysts used in the imprinting process allows for better morphology control of the imprinted silicon which is attributed to increased pathways for diffusion of chemical species during imprinting. This process delivers low-defect density, and large-area patterning (>1 cm²) in a single imprinting operation. Further, it outperforms the resolution and scalability of leading serial (e.g. FIB, electron beam) and parallel (e.g. gray-scale lithography) methods altogether, allowing for fast replication of patterns onto hard materials from a soft or polymeric mold. This technique bypasses the need for dry etching and is potentially compatible with roll-to-roll platforms, amorphous and poly silicon and III-V semiconductors. In turn, it may pave the way for mold replication onto hard molds and the manufacturing of complex objects for infrared optics.

We will introduce SCIL as a full-wafer soft-stamp base nanoimprint technique with the advantages of being able to replicate sub-10nm features and perform overlay alignment with sub-micron precision over 200mm wafers. The combination of PDMS based soft stamps and an inorganic crosslinking imprint resist leads to a very long stamp lifetime of over 700 imprints, as demonstrated in the AutoSCIL 200 high volume production tool. Initial applications for wafer based NIL mainly required only a single, first mask, patterning step. For optical applications high refractive index material which can be directly patterned with high fidelity and low shrinkage are desired and initial results of inorganic resists that reach a refractive index of n=1.8 are demonstrated. As NIL and the applications develop, overlay alignment is the next step. Here we will discuss the developments ongoing to integrate wafer scale overlay alignment in the AutoSCIL production platform and which would achieve ~1 micrometer overlay alignment over 200mm wafers. Two applications that make use of the ability of NIL to replicate large area nano-patterns (X-ray mirrors) and the combination of micro- and sub-20nm patterns in one layer / pattern (cell proliferation templates) are discussed.

The maskless electron beam lithography system, based on massively parallel electron-beam writing strategy has the ability for low-cost production of truly unique individual chips in volume manufacturing, compatible with optical systems. Mapper Lithography has introduced the FLX-1200 platform installed at CEA-Leti. This paper will present fully process-integration stepwise developments to be compliant with the single via layer demanding targets based on dual damascene process:

The lithographic performances and etch transfer optimization were firstly evaluated on a layer stack representative of N40 CMOS technology by developing step-by-step approach:

- 1/ Trilayer lithography of via layer and partial etch into low-k development with VSB 50kV

- 2/ Litho/etch process of product wafer with VSB 50keV

- 3/ Trilayer lithography of via pattern and etch into low-k for FLX-1200 multi-beam 5kV

- 4/ last litho of via pattern on product wafer using FLX (no etch yet). In addition, the overlay and CDU capability of FLX-1200 are assessed for via 3, and the alignment to product wafer is tested.

Via patterning integration showing the up-to-date achievements is mature enough to start first customer demos for security application.

Nanoimprint lithography (NIL) is one of the most promising technology platforms for replication of nanometer and micrometer scale 3D topographies with extremely high resolution and throughput, as needed for e.g. photonic or optical applications. One of the remaining challenges of 3D NIL, however, is the fabrication of high quality 3D master originals – the initial patterns that are replicated multiple times in the NIL process. Here, we demonstrate a joint solution for 3D NIL where NanoFrazor thermal scanning probe lithography (t-SPL) is used to pattern the master templates with singlenanometer accurate 3D topographies. 3D topographies from polymer resist master templates are replicated using a HERCULES NIL system with SmartNIL technology. Furthermore, 3D patterns are transferred from the resist into a silicon substrate via reactive ion etching (RIE) and the resulting silicon master template is used for producing polymeric working stamps into OrmoStamp and, finally, replicas into optical grade OrmoClearFX material. Both replication strategies result in very high-quality replicas of the original patterns.

Novel wafer stepper by using contact or proximity printing was developed. The ultraviolet region starts right after the violet end of the rainbow. In scientific terms, UV radiation is electromagnetic radiation just like visible light, radar signals and radio broadcast signals. Ultraviolet radiation can be broken down into three bands: UVA, UVB, and UVC. Projection wafer stepper needs use single wavelength as light sources, such as: g-line, i-line, KrF and ArF. The broadband wavelengths of the UVA, UVB and UVC regions: UVA 400 nm - 315 nm, UVB 315 nm - 280 nm, UVC 280 nm - 100 nm can be used for contact or proximity exposure. Wafer stepper without using projection lens, system reliability and manufacturing cost of wafer stepper can be improved by using contact/ proximity method. This novel contact/ proximity wafer stepper can be used for 3DIC, MEMS and bio-chip lithography application by using thin and thick resist.

Green ethanol-developable electron beam lithography processes has great potential for reducing toxicity and future production of micro electro mechanical systems (MEMS), imprint molds, and biosensors where continued success ultimately requires improvements in existing electron beam lithography processes. This study presents progress in the development of a new positive tone biomass-based resist material with high hydrophilicity from the viewpoint of utilization of agricultural resources and advanced use of biomass for improving resolution on hardmask middlelayer. The ethanol-developable images of 70 nm line patterns were provided by the green ethanol-developable processes, instead of the common developable processes of tetramethylammonium hydroxide and organic solvents whose ecotoxicity is described by The Globally Harmonized System of Classification and Labelling of Chemicals, GHS.

We have been trying to improve nanoimprint lithography performance through modification of template materials. We have reported a biomass based template with gas permeability which decreases transcriptional defects on template materials caused by involved solvents and cracked gasses generated from imprinted materials. (SPIE2016 and 2017) The line patterning results using the biomass based gas permeable template were better to reduce the line pattern failure as compared with that of quartz based template as the standard reference. In this study, we will report a mechanical property improvement of the template by blending cellulose nanofiber (CNF) to the biomass template. The blended template showed improved gas transmission coefficient and mechanical properties than non-blended template. The proposed nanoimprint lithography using biomass based template with gas permeable and gaseous adsorption is one of the most promising processes ready to use for mass-production of nanoscale devices.

Nanoimprint lithography is applied to manufacturing of cell culture dish and biosensor. The outgas released from the material often causes defects on patterns. Gas permeable templates were derived from cellulose for ultraviolet nanoimprint lithography process. The templates were made of thermoset cellulose of acrylic group and methacrylic group. The light transmission rate of the thermoset cellulose film and mechanical properties and pattern structure of the gas permeable template were measured. The template with acrylic group baked at 80 °C for 10 min. showed superior mechanical properties. This suggests the template had a large number of crosslinked points. After pattern transfer from quartz template, structures of the holes, the pillars, and the lines and spaces on the gas permeable template were observed.

The demand to create ever finer features at ever tighter pitches has fueled the drive towards lithographic methods that use radiation with the shortest possible wavelength. This approach, however, faces a considerable number of technological challenges that need to be addressed. An alternative, cost-effective approach is multicolor lithography. Inspired by the technology for superresolution in optical microscopy, multicolor visible light approaches led to achieving features down to λ/20 using 3-D multiphoton absorption polymerization (MAP). Although these original efforts in the field involved the use of two colors of light, it has become apparent that 3-color approaches will be required to address the need to pack features together tightly. In this work, we present some of the latest progress in the benchmarking and development of three-color photoresist materials, and demonstrate how the addition of a third color in the exposure scheme can lead to substantial improvements in resolution.

Three-color lithography (3CL) can produce high-resolution features using visible light. This technique uses one beam to pre-activate a photoresist, a second beam to deactivate it, and a third beam to activate the pre-activated regions that have not been deactivated. The deactivation beam is used to trim features, allowing for improved feature size and resolution. Although this 3CL was pioneered with 2-photon excitation, the ultimate goal is to use thin films with linear excitation, such that it is compatible with industrial requirements. We will discuss the first thin-film 3CL studies, which are a promising step towards large-area patterning.

A three-color lithographic (3CL) scheme has been developed to achieve high resolution through the use of visible and near IR wavelengths. The intrinsic kinetic properties of 3CL materials are used to optimize the efficiency of deactivation, a crucial step in overcoming background buildup in multipatterning using this technique. To study materials of interest for 3CL, we have developed an in situ technique to monitor exposure and deactivation. A two-beam interference pattern is polymerized on a photoresist and the diffraction of a continuous-wave probe laser is measured in order to identify the polymerization and deactivation thresholds. Here we present preliminary results on the time dependence of the deactivation efficiency of 3CL materials and in situ detection of polymerization thresholds. This is a study of the kinetics for polymerization of 3CL materials to optimize the 3CL scheme to achieve the highest resolution and elucidate its mechanism.

The importance of multi-layer process with spin-on hard masks increases for various processes on the next generation of logic and memory devices. The tri-layer process with spin-on glass (SOG) and spin-on carbon (SOC) is mainly used for ArFi multi-patterning lithography process, in order to provide wide process window by suppressing substrate reflectivity as well as etch-transfer fine pattern to substrate by enhancement of etch selectivity. However, conventional tri-layer process in advanced node device has the critical issue on substrate damage in SOG removal process because of vulnerability of topography wafers which contain smaller pattern features and thinner ALD/CVD films. In order to solve this problem, we developed novel SOG removal process with unique SOG/SOC materials for substrate damage mitigation. We will report Thin SOG Process for substrate damage-less SOG removal process.

This work presents a model-based proximity effect correction method and investigates its potential for helium ion beam lithography (HIBL). This method iteratively modulates the shape of pattern by a feedback compensation mechanism until the simulated patterning fidelity satisfied specific constraints. A point spread function is utilized to account for all phenomena involved during the scattering events of incident ion beam particle in the resist. Patterning prediction for subsequent correction process is derived from the energy intensity distribution, as a result of convolution between the point spread function and the pattern, with an adequate threshold. The performance of this method for HIBL is examined through several designed patterns from 15- to 5-nm HP under certain process parameters, including acceleration voltage, resist thickness and sensitivity. Preliminary results show its effectiveness on improving the patterning fidelity of HIBL.

Nanoimprint lithography (NIL) is regarded as one of the candidates for next generation lithography toward singlenanometer manufacturing. Among the wide variety of imprint methods, Jet and Flash Imprint Lithography (J-FIL) process is the most suitable for IC manufacturing for which high productivity and high precision is required. Unlike spin-coating-based NIL process J-FIL process has some capabilities to solve the issue by controlling local resist volume based on pattern design of the patterned mask (template). In order to improve NIL process, in this paper we focus on understanding the occurrence of non-filling defects during resist filling into the template features, and propose the new optimization concept of drop amount and drop arrangement for fast filling and defect reduction.

As semiconductor features shrink in dimension and pitch, the excessive control of critical-dimension uniformity (CDU) and pattern fidelity is essential for mask manufacturing using electron-beam lithography. Requirements of the electronbeam shot quality affected by shot unsteadiness become more important than before for the advanced mask patterning. Imperfect electron optical system, an inaccurate beam deflector, and imprecise mask stage control are mainly related to the shot unsteadiness including positioning and dose perturbations. This work extensively investigates impacts of variable shaped beam dose and positioning perturbations on local CDU using Monte Carlo simulation for various mask contrast enhancement approaches. In addition, the relationship between the mask lithographic performance and the shot count number correlated with mask writing time is intensively studied.

Nanoimprint lithography (NIL) is a candidate of alternative lithographic technology for memory devices. We are developing NIL technology and challenging critical issues such as defectivity, overlay, and throughput . NIL material is a key factor to support the robust patterning process. Especially, resist material can play an important role in addressing the issue of the total throughput performance. The aim of this research is to clarify key factors of resist property which can reduce resist filling time and template separation time . The liquid resist is filled in the relief patterns on a quartz template surface and subsequently cured under UV radiation. The filling time is a bottleneck of NILthroughput. We have clarified that the air trapping in the liquid resist is critical. Based on theoretical study, we have identified key factors of NIL-resist property. These results have provided a deeper insight into resist material for high throughput NIL.

Sub-10 nanometer lithography is opening a new area for beyond-CMOS devices. Regarding to single nano-digit manufacturing we have established a new maskless patterning scheme by using field-emission, current controlled Scanning Probe Lithography (cc-SPL) in order to create optical nanodevices in thin silicon-on-insulator (SOI) substrates. This work aims to manufacture split ring resonators into calixarene resist by using SPL, while plasma etching at cryogenic temperatures is applied for an efficient pattern transfer into the underlying Si layer. Such electromagnetic resonators take the form of a ring with a narrow gap, whose 2D array was the first left-handed material tailored to demonstrate the so-called left-hand behavior of the wave propagation. It is shown that the resonance frequency can be tuned with the feature size of the resonator, and the resonance frequency can be shifted further into near infrared or even visible light regions.

Block copolymers (BCPs) can phase separate to form periodic structures with small spacings on the order of the polymer molecular size, thus making BCPs an attractive potential method for extending the resolution limits of optical lithography through various pitch subdivision techniques. In order to direct the self-assembly of BCP thin films, methods such as chemoepitaxy are employed which use the contrast between a chemically preferential pinning stripe and a more neutral background region to guide the phase separated features. Homopolymer is a known blending agent for BCPs that allows for the periodic spacing of their features (pitch, Lo) to be adjusted based on the concentration of homopolymer. This allows for less stringent tolerances on the molecular weight of the BCP in order to achieve a particular Lo. Addition of homopolymer is a relatively simple and potentially attractive method, but such blending may also a effect the resulting line edge and/or line width roughness in the DSA patterns. In this work, detailed molecular dynamics simulations of block copolymer directed self-assembly have been used to show how such behaviors and process performance factors are a effected by the symmetric addition of homopolymers (A and B) to a thin film lamellae forming BCP (A-b-B).