The VERITAS 2.3 readout ASIC for the ATHENA Wide Field Imager

This paper presents an overview of the design and development of VERITAS 2.3, an evolutionary step of the VERITAS (VErsatile Readout based on Integrated Trapezoidal Analog Shapers) readout integrated circuit (ROIC) architecture designed for high-speed, low noise readout of the DEPFET detectors in the Wide Field Imager on ESA’s Athena X-ray satellite. The chip includes 64 channels, delivering a short processing time of 2.5 µs per readout while targeting a system noise of 3 e- ENC RMS, enabling nearly Fano-limited spectroscopic performance. While the new chip still uses previous versions’ proven 0.35 µm CMOS technology node, we have employed new foundry and process options for better manufacturability and improved reliability. This paper discusses several design improvements like MIM caps instead of poly caps, fully differential drivers and better ADC connectivity.