Plenty to talk about
From presentations in the conference rooms on state-of-the-art lithography processes,
to conversatons over coffee in the hallways, SPIE Advanced Lithography
offers rich opportunities for networking.
On Sunday, it's all about knowledge
Taught by recognized experts in industry and academia, course attendees spent Sunday learning current approaches in DTCO, optimization, image placement, DSA, EUV, and more.
Courses at SPIE Advanced Lithography saw an uptick in attendance this year.
Above, instructor Grant Willson (University of Texas at Austin) teaches
"Introduction to Microlithography: Theory, Materials, and Processing."
Stephen Hsu (ASML Brion) teaches
"Principles and Practical Implementation
of Multiple Patterning"
John Petersen (Consultant) teaches
"The Big Ideas in
Monday morning plenary talks drew a capacity crowd at SPIE Advanced Lithography 2017.
Are mask-makers ready for EUV?
Frank Abboud, Vice President of Technology and Manufacturing Group at Intel, and General Manager, Intel Mask Operation, was the first plenary speaker Monday morning at SPIE Advanced Lithography 2017. Abboud, who is also on the conference program committee for SPIE Photomask Technology, shared a historical perspective and recent achievements in photomask manufacturing.
With ever-smaller feature sizes being designed, from 22nm to 10nm, with features 1/10 the size of the wavelength of the exposure tool, mask makers continuously advance resolution and reduce defects. He noted that photomasks act as diffractive optical elements in the lithography process: they modify all parameters of impingent light including intensity, direction, phase, and polarization. Extreme ultraviolet (EUV) sources are, in Abboud's words, "More disruptive to the mask shop than the wafer fab. Almost every module in the mask shop is touched," including blank preparation, fiducial mark patterning, device patterning, black-border patterning, and metrology/characterization.
Looking ahead to answer the question of whether mask makers are ready for EUV, Abboud described the Intel Mask Operation approach to adopting EUV lithography through supply chain development, consortia, collaboration, co-development and internal programs.
The results include full field EUV pellicles demonstrated in 2014 and product reticles shipped in 2016. There have been continuous improvements with champion results reported as 2 defects at 38nm scale, which allows one to map the defects, move and cover the defects, and thus avoid the defects in practice. Abboud noted how electron-beam technology is being adopted in EUV mask defect repairs.
Over time, more of the photomask work is done at internal (captive) mask shops like at Intel, with VLSI predicting mask volume will decrease 10%, but cost will increase 30% over the next few years, primarily driven by the capital spending necessary to shift to EUV. However, Abboud assured the SPIE plenary audience that, "The next technology paradigm -- EUV -- will not be gated by mask."
The ROI of defect detection
The second plenary presentation was by Ben Tsai, Chief Technology Officer and Executive Vice President of Corporate Alliances at KLA-Tencor.
Tsai's presentation was titled "Inspection and Metrology to Support the Quest for Perfection: Photolithography for the Sub-10nm Nodes." Inspection and metrology can involve 1,000 process steps for an advanced graphics processing unit (GPU), with extremely high accuracy. Tsai noted that in such a process model, if each step was 99.5% perfect, less than 1% of manufactured devices would work, illustrating the importance of investment in inspection and metrology to identify and resolve essentially all defects.
Tools that help include a dual imaging mode that enables detection of yield-critical mask imperfections in two passes: first at high resolution to identify potential candidates and the second to pick up the printability of defect candidates.
The complex process of defect reduction involves materials suppliers, process tool manufacturers, and integrated circuit fabs. If 4,000 wafers are being created in 24 hours, the cost of defects is extremely high, and the ROI of finding defects fast is great.
Tsai described the process window as:
- Discover — ground truth
- Expand — root cause
- Control — monitor over time.
He compared critical design areas to inspect and how e-beam inspection may typically inspect 8 wafers in 24 hours, with only .01% of the wafer area inspected. In contrast, optical inspection can process 24 wafers in 24 hours, with 97% of the wafer area inspected, with some overlay specifications at ~2 nanometers.
Tsai noted advances in scatterometry overlay to improve robustness using optical measurements, and a tunable super-continuum laser as the illumination source that is 20nm wide, centered at the 640nm wavelength.
Tunability improves accuracy and addresses process variation across wafer. He described CD SEM as complementary CD/shape metrology technology that allows sideways angles to be measured and controlled, for which only optical methods work.
Looking toward EUV lithography inspection, he pointed out that incoming shape and stress variations including lot-to-lot, and wafer-to-wafer can be improved with feedback to producers at the prior step to adjust processes, while also feeding forward the detected errors, which is one of the ways inspection tools pay for themselves through process improvement. Watch Tsai's plenary presentation here.
Driving Moore's Law for next-gen capabilities
Nobu Koshiba, President and CEO of JSR Corp., presented the final plenary talk, on "Materials Innovation: It's No Longer About Resolution" starting with a vision of drivers for next generation computing such as artificial intelligence (AI) and the computational power required. The information explosion we have seen trending for years is continuing, with estimated data traffic in 2020 being 7× greater than 2015.
All this information is another driver for AI, as is autonomous driving, precision medicine, genomic science, and cognitive computing among the new elements of our digital society that Koshiba has studied.
As was a common theme for each of the SPIE Advanced Lithography 2017 plenary speakers, Koshiba noted that the success of EUV is core to more advanced computers. He noted how new materials and processes are being developed, for example, adding a layer of polymer between resist lines to reduce line collapse and issues associated with cleaning increasingly narrow gaps. New materials, such as SiARC, provide extreme etch resistance and selective deposition of materials (e.g., metal "A" does not deposit on oxide, then metal "B" only deposits on oxide) are some new areas that can squeeze maximum resolution lithography and chip density with lower defect contributions.
Koshiba described canonical milestones in human history, with contemporary examples being personal computers in the '80s and the internet era, and a shift in computing from tabulating, through programmable systems, and into a next inflection point, perhaps in the 2020s, which he called the cognitive systems era.
This new era includes both quantum computing (left side of brain) and neuromorphic device (right brain, parallel processes). While current CMOS logic devices fit into both aspects, the vision of cognitive computing is that AI will be transparent to users, logic and memory don't end, and we finally have the next "killer app," namely AI and data-driven society.
Achieving this vision will require new organizational approaches, and Koshiba described the unique development center created with JSR and imec, including specific focus on EUV challenges that can be addressed with tools and process know-how from both organizations.
In the end, according to Koshiba, "Commitment and forms of collaboration will drive Moore's Law to the 2nm logic node."
Honors and awards
From left, SPIE CEO Eugene Arthurs; Symposium Chair
Bruce Smith (Rochester Institute of Technology);
new SPIE Fellows James Thackarey (Dow Electronic
Materials), Mark Phillips (Intel Corp.), Qinghuang Lin
(IBM Thomas J. Watson Research Center), Yuri Granik
(Mentor Graphics), and Emily Gallagher (IMEC);
and Symposium Co-Chair Will Conley (Cymer)
Donis Flagello (Nikon Research Corp of America), second
from right, received the 2017 Frits Zernike Award in
Microlithography for work in the understanding and
improvement of image formation in lithography for
semiconductor manufacturing; with SPIE CEO Eugene
Arthurs, and Symposium Co-Chair Will Conley (Cymer)
and Chair Bruce Smith (Rochester Institute of Technology).
Metrology, Inspection, and Process Control for Microlithography conference chair Martha Sanchez (IBM Research - Almaden), and conference co-chair Vladimir Ukraintsev (Qorvo) presented the 2016 Diana Nyyssonen Memorial Award for Best Paper to Vassilios Constantoudis (National Ctr. for Scientific Research Demokritos and Nanometrisis); Hari Pathangi, and Alessandro Vaglio Pret (IMEC); Vijaya-Kumar Murugesan Kuppuswamy (National Ctr. for Scientific Research Demokritos; Roel Gronheid (IMEC); and Evangelos Gogolides (National Ctr. for Scientific Research Demokritos and Nanometrisis) for their presentation, "Challenges in LER/CDU metrology of DSA structures: pitch roughness and cross-line correlations" (9778-143)
Advances in Patterning Materials and Processes session chairs Christoph Hohle (Fraunhofer Institute for Photonic Microsystems), and Roel Gronheid (IMEC) presented three awards:
- The 2016 C. Grant Willson Best Paper Award to Dario Goldfarb, Ali Afzali, and Martin Glodde (IBM Thomas J. Watson Research Center) for "Acid generation efficiency: EUV photons versus photoelectrons" (9779-8)
- The 2016 Jeffrey Byers Memorial Best Poster Award to Shinji Kobayashi, Soichiro Okada, Satoru Shimura, and Shinobu Miyazaki (Tokyo Electron Kyushu Ltd.); Kathleen Nafus, and Carlos Fonseca (Tokyo Electron America, Inc.); and Serge Biesemans (Tokyo Electron Europe Ltd.), for "CD control based on edge placement error analysis" (9779-62).
- 2016 Hiroshi Ito Memorial Award for the Best Student Paper Award to Corinne Carpenter, Kris Delaney, and Glenn H. Fredrickson (Univ. of California, Santa Barbara) for "Directed self-assembly of diblock copolymers in mutli-VIA configurations: effect of chemopatterned substrates on defectivity" (9779-47).
SPIE Fellows gather
Newly inducted SPIE Fellow Emily Gallagher (IMEC, Belgium) presented a talk on "Assisting EUV - Implications in OPC, Masks and Imaging" at the Fellows luncheon on Monday afternoon. Gallagher was promoted to Fellow for achievements in semiconductor and photomask technology. She joins a prestigious group of nearly 70 Fellows of the Society who work in lithography.
Britt Turkot (Intel Corp.) gave the keynote presentation in the Extreme Ultraviolet (EUV) Lithography conference on Monday. The packed conference room enjoyed her presentation, "EUVL Readiness for High-Volume Manufacturing."
Happy exhibitors, happy attendees
The hall was all smiles as 50 exhibiting companies showcased their work on technologies such as immersion, EUV, imaging equipment, etch technology, IC and chip fabrication, lasers, and design and manufacturing software.
"Within the first hour and a half of the first day of (SPIE) Advanced Lithography, I had 15 good companies visit my booth," said Ron Synowicki, an applications engineer at J.A. Woollam Co., Inc. "I'm seeing former customers, current customers, and prospects. The business is coming to me!"
Stuart Koch, Vice President of Technical Products at Amuneal Manufacturing Corporation, echoed the enthusiasm. "(SPIE) Advanced Lithography is the only show we have ever done where the doors open the first day, the customers flood in, and we are busy. It is almost instantaneous."
The exhibition continues on Wednesday. View more exhibition photos in the Exhibition Photo Gallery.
A tribute to a pioneer
Semiconductor pioneer and SPIE Fellow Burn Lin (National Tsin Hua University) was honored on the 30th anniversary of the Optical Microlithography conference (10147) in recognition of his serving as the first chair of the conference in 1988, and his outstanding contributions to the lithography community.
Current conference chair Andreas Erdmann (Fraunhofer-Institut für Integrierte Systeme und Bauelementetechnologie IISB) and conference co-chair: Jongwook Kye (GLOBALFOUNDRIES Inc.) presented the award.
Lin is the founding editor-in-chief of the SPIE Journal of Microlithography, Microfabrication, and Microsystems (JM3).
Join the conversation:
SPIE Advanced Lithography symposium 2017 — day 4 (Litho Guru, 3 Mar 2017)
The week in review: manufacturing (Semiconductor Engineering, 3 Mar 2017)
Chemistry startup claims EUV resist breakthrough (Electronic Engineering Times Europe, 2 Mar 2017)
SPIE Advanced Lithography symposium 2017 — day 3 (Litho Guru, 2 Mar 2017)
ASML revs EUV engines (Electronic Engineering Times, 1 Mar 2017)
Intel: possible delay in 10-nano ramp, says BlueFin (Barron's, 1 Mar 2017)
ASML 3400B production platform for EUVL ready for shipping (CdrInf, 1 Mar 2017)
SMC joins the eBeam Initiative as EUVL and multi-beam mask writing become key themes for 2017 (Solid State Technology, 1 Mar 2017)
SPIE Advanced Lithography symposium 2017 — day 2 (Litho Guru, 1 Mar 2017)
Intel, Samsung provide EUV progress updates at SPIE (CdrInf, 28 Feb 2017)
EUV progress, hurdles cited (Electronic Engineering Times, 28 Feb 2017)
SPIE Advanced Lithography symposium 2017 — day 1 (Litho Guru, 28 Feb 2017)
IMEC presents patterning solutions for N5-equivalent metal layers (Solid State Technology, 27 Feb 2017)
EUV is NOT ready for 7nm! (Semi Wiki, 27 Feb 2017)
SPIE Advanced Lithography symposium 2017 — day 0 (Litho Guru, 27 Feb 2017)
A step closer to high-volume maufacturing including EUVL (Silicon Semiconductor, 27 Feb 2017)
SPIE Advanced Lithography symposium 2017 — a prologue (Litho Guru, 22 Feb 2017)
Areas of focus and list of challenges for EUV lithography at 7nm, 5nm, and 3nm nodes (Solid State Technology, 22 Feb 2017)
All photos © SPIE unless otherwise noted.
26 February – 2 March 2017
San Jose, California, USA