23-27 February 2014
San Jose, California, USA
Thursday 27 February
Wednesday 26 February
Tuesday 25 February
Monday 24 February
Sunday 23 February
Event photo gallery
Thursday 27 February
The place to meet the right people
With attendance up from last year, SPIE Advanced Lithography continued to fill an important role in the industry -- "a crucial place to meet the right people, especially in the conference sessions," as Paolo Petronia of Aselta Nanographics put it.
"This is where you meet your peers, everybody that matters in this business," said Roel Gronheid of IMEC.
Attendance was 2,360 for the week, conference overflow rooms were well used, receptions and hallways were busy networking locations, and buzz was strong on the exhibition floor where exhibitors reported getting good traction and making valuable connections for new business.
"The advantage of a symposium that covers nearly every aspect of nanopatterning was particularly evident for the topic of multiple patterning, which involves aspects relevant to all of the seven conferences that comprise Advanced Lithography," said symposium chair Harry Levinson of GLOBALFOUNDRIES. "What makes the meeting so vital is having many excellent lithographers in one location."
SPIE Advanced Lithography 2015 will return to the San Jose Convention Center, running 22-26 February. See you next year!
Wednesday 26 February
Advancing the industry
With another full day of talks, Wednesday's technical sessions brought forward even more information and insights on how to move the industry forward. Topics covered the full range of advanced lithography issues and offered new insights for solving challenges and gaining new capabilities.
A collaborative ecosystem
In his invited talk on "High-volume manufacturing equipment and processing for self-assembly applications," [9051-22] Mark Somervell of Tokyo Electron America spoke to his company's efforts to advance directed self-assembly (DSA) patterning into high volume manufacturing (HVM).
As Akihisa Sekiguchi of Tokyo Electron Limited (TEL) did in his plenary talk on Monday, Somervell stressed the importance of a collaborative ecosystem in bringing complicated solutions to market.
Migration into HVM is predicated upon high throughput and low defectivity in addition to demonstrations of the patterning capability required for future nodes. Somervell detailed work done as part of an IMEC program around line/space patterning in which the team was able to demonstrate control over dislocation density through varying bake temperature and duration thereby establishing the ability to open up the process window.
Subsequent work utilizing the AZ Electronic Materials chemo-epitaxy SmartTM process resulted in 18nm half-pitch structures and line edge roughness (LER) of 1.5nm, 3σ. Additional line/space work done with a grapho-epitaxy process flow and high χ (chi) materials exhibited 8nm half-pitch structures. In terms of contact patterning, improvements in hole definition and across-wafer hole pair uniformity was achieved in another set of experiments.
Somervell highlighted other aspects of the overall process flow that are maturing by showing that atmospheric control during bake is critical to the process, sharing results of simulation work that showed the impact of substrate wettability on morphology, and demonstrating a 100X improvement in defect density over the past year.
It is becoming clear that this collaborative approach is paying dividends in terms of making DSA closer to being a manufacturing reality.
Delivering the resolution
An investigation of the applicability of nanoimprint lithography (NIL) in the hard disk drive industry was the topic of Seagate's Daniel Sullivan's presentation "Hard disk drive thin-film head manufactured using nanoimprint lithography" [9049-34].
NIL can deliver the pattern resolution required for this industry and benefits from the relaxed requirements for defect density and throughput compared to those required in the semiconductor space.
Currently, the industry works with critical dimensions in the 17-36nm range, and Sullivan explained he expects to see these dimensions move to the 9-20nm range over the next five years. In addition to these requirements, the thin film head industry patterning requirements include the need to print small isolated features, handle complex 2D geometries and maintain suitable line edge roughness (LER) performance.
Working with partners at Molecular Imprints, Incorporated, Sullivan and his coworkers demonstrated jet and flash imprint lithography (J-FIL) can deliver a pattern-transfer compatible process whose resulting devices delivered electrical performance matching that achievable through conventional optical lithography means. The technique has the additional benefit of not being limited by traditional optical field limits on the order of 26x33mm.
In sum, Somervell concluded that strong synergies do exist between thin film head processing and NIL techniques.
Nanoimprint for quality
Nanoimprint lithography is one of the potential candidates for the next generation lithography for semiconductor, said Koji Ichimura, Dai Nippon Printing, in "Development status of nanoimprint template quality" [9049-37]. Ichimura reported on recent status of the replicated template quality, from the nanoimprint point of view.
The quality of the templates replicated from electron beam written "master templates" by nanoimprint lithography is one of the important aspects of the nanoimprint technology, she noted, while defect quality is one of the greatest concerns.
There are several nanoimprint-specific defects, which require special care in reduction. Because nanoimprint templates have 1:1 feature size, resolution and critical dimension uniformity are also of interest.
New state of the art
Giuseppe Calafiore of aBeam Technologies described a process to fabricate sub-15 nm metallic gratings by pre-spincoated film SR-NIL, in "Step-and-repeat nanoimprinting on pre-spin coated film: from sub-15nm metal patterning to the fabrication of a spectrometer-on-chip" [9049-38].
Moving from high-resolution structures to real and complex optical devices, Calafiore also reported on the fabrication of a nanospectrometer based on digital planar holography by the same method. He showed numerous test results on various devices, with results proving the flexibility and robustness of the pre-spin coated SR-NIL process and establishing a new state-of-the-art for SR-NIL.
Another evening of posters and connections
Wednesday night's poster session drew another big crowd to view posters and meet with colleagues; above from left, Matthias Rudolph (Fraunhofer CNT), Uzodinma Okoroanyanwu (GLOBALFOUNDRIES), and Xaver Thrun (Fraunhofer CNT). The poster session was sponsored by TOK. More photos are in the event photo gallery.
Tuesday 25 February
Check out the exhibition, see what's new
More than 60 suppliers of lithography R&D, devices, tools, fabrication, and services are on the exhibition floor as of Tuesday morning. The floor is open until 5 p.m. today, re-opening from 6 to 8 p.m. during the poster session. Wednesday hours are 10 a.m. to 4 p.m. -- see you there!
More photos are in the event photo gallery.
In the conference rooms
Tuesday brought even more choices among papers to hear in conference rooms, with the opening of the Optical Microlithography conference. Among opening papers was a keynote talk by Amazon Web Services' David Pellerin (at left in the photo at right, with conference chair Kafai Lai of IBM), on"Going wide in the cloud: why stability matters in a simulation-drive world" [9052-2].
Highliglhting recent trends in cloud-based computing for high-performance technical and scientific applications, Pellerin said that simulations are being run at massive scale in the cloud to solve vexing problems in engineering, life science, pharmaceuticals, big data analytics, and global finance. Pellerin provided real-world examples of scalable simulations being performance across industries, and offered predictions about the future of cloud-based design and layout verification and why scalability matters for increasingly complex EDA and semiconductor production workflows.
IMEC and SUNY College of Nanoscale Science and Engineering (CNSE) were among many organizations with multiple presentations in the program.
Roel Gronheid of IMEC noted that his organization's papers covered several topics in directed self-assembly (DSA), which offers promising solution for cutting costs as well as providing high-resolution with uniformity. In an SPIE Newsroom video interview, Gronheid said he sees the possibility for DSA and EUV in combination, as each tool provides different capabilities.
CNSE, with nearly two dozen papers, also stressed collaboration. Executive Vice President of Innovation and Technology and Vice President for Research Michael Liehr noted that CNSE's corporate partners in nanotechnology-based semiconductor research include SEMATECH, Dow Chemical, and Kumho Petrochemical.
3D approaches for scaling
Tuesday evening's panel discussion on "Alternative Forms of Scaling" focused on 3D methods for NAND flash, system-on-chip, memory, and alternative memory devices. With Christopher Bencher of Applied Materials and Philip Wong of Stanford University serving as moderators, each of the panelists was provided an opportunity to present the current status and merits of 3D approaches for their devices.
Johann Alsmeier of SanDisk Corporation discussed the motivation for 3D NAND flash citing scaling limits of high-voltage program and erase functions, decreasing storage charge, and cost which is ultimately driven not by lithography but by the etch and deposition modules. Alsmeier said that the migration from 2D to 3D should reduce proximity effects, increase endurance, result in higher write speeds and reduce power consumption.
Liam Madden from Xilinx discussed heterogeneous stacking for FPGA products. The historical issue with combining logic, memory and analog into a single package stemming from very different feature sizes and orders of magnitude differences in their respective package trace widths can now be addressed through the use of silicon interposers which also enable multiple products to be generated out of one tape-out through the use of different interposer schemes. This should allow for a cost-effective stacking scheme but it does depend on effective management of the chip manufacturing and packaging supply chain for fabless companies.
The potential for 3D stacked DRAM was described by Kunal Parekh of Micron Technology, who discussed hybrid cube memory (HCM). Although challenges induced by lithographic scaling such as data retention is important, DRAM scaling will ultimately be limited not by lithography but by challenges with the capacitor module. Stacking memory addresses bandwidth concerns by enabling higher densities and efficient power use while allowing for increased memory capacity craved by applications like enterprise computing.
Michael Van Buskirk of Adesto Technologies presented the case for 3D R-RAM (resistive RAM). After familiarizing the audience with the different switching schemes available with this technology and demonstrating a path from the traditional DRAM 6F2 cell to a 4F2 cell, Van Buskirk highlighted the benefits and drawbacks of 3D cross-point and vertical R-RAM schemes and argued that R-RAM provides a scaling advantage over traditional NAND architectures.
Several themes emerged during an enthusiastic question-and-answer on this obviously high-interest topic, touching on issues such as the need for good thermal management, the importance of stress management in stacking schemes, the role of defect management and suitable metrology, and the necessity for new materials.
The session ended with the panelists, in response to a question on projecting the likelihood of current university research work coming to fruition in industry, agreeing that while it is difficult to predict the future, clearly each of the approaches they represented have potential to extend to 3D and each has challenges to address along the way.
'Crimes' against Moore's Law!
The ersatz "Judge" Will Conley of Cymer presided over a panel discussion in the form of a mock trial themed "The Battle for the 7nm Node: What are the Non-EUV Solutions."
On trial? Patterning without EUV, for crimes against Moore's law and for introducing unnecessary complication and confusion into the industry.
After swearing in the "jury" to ensure their veracity (" ... so help me GORDON!") and informing the audience of the process, Judge Will read off the charges against each of the seven defendants, ranging from the ITRS roadmap, to equipment vendors, to material suppliers to designers.
Defendants -- several conference chairs and co-chairs represented the defendants while others served as jurors -- then had an opportunity to defend themselves of these heinous charges, a task they embraced with full vigor and a fair share of humor much to the audience's delight.
In the end, after hearing the passionate defenses offered up by the defendants, the jury found all of them "not guilty" of the charges, and they were set free to continue their efforts towards the 7nm node.
Sponsoring conference chairs and co-chairs acted as judge, jurors, and defendants in putting patterning without EUV on trial.
The panel discussion was sponsored by KLA Tencor.
Posters and authors, face-to-face
Tuesday evening's well-attended poster session featured papers from conferences on EUV Lithography, Alternative Technologies, Metrology, Patterning, Optical Microlithography, and Etch Technology for Nanopatterning. The poster session was sponsored by AZ Electronic Materials. More photos are in the event photo gallery.
Sunshine, fresh air, back for more
Warm weather early in the week lured conference participants out to the Market Terrace in the convention center during the afternoon break ...
... and a full slate of conferences drew them back in for more.
'We can fly!'
The hour between the end of Tuesday exhibit hours and the evening poster session was just enough time for Naoya Hayashi (Dai Nippon Photonics), to film part of a video promoting the Photomask Japan meeting in Yokohama in April. The theme "We Can Fly" was acted out by two of his colleagues, at right, and the flying was done by Hayashi's droid, hovering at left before soaring off across the length of the exhibit hall. At the planning breakfast earlier in the day for SPIE Photomask Technology, Hayashi recruited his fellow committee members to act out the same message -- will we see the video on YouTube?
Monday 24 February
Packed plenary audience opens 'the SPIE'
A standing-room-only audience of nearly 1,200 gathered in the new conference halls in the San Jose Convention Center to hear speakers in the opening plenary session.
'The SPIE' and more
Many in the international lithography community who have met at the SPIE-sponsored Advanced Lithography meeting in Silicon Valley over the past 38 years refer to their annual event as "the SPIE."
SPIE involvement in optics and photonics has some additional aspects in addition to lithography, however, noted plenary speaker Bill Arnold, ASML Chief Scientist and Vice President of the company's Technology Development Center: "The SPIE" is one of about 25 conferences SPIE organizes globally each year.
Now officially SPIE Immediate Past President, Arnold has traveled the globe on behalf of the society, and had a particularly busy year as President in 2013. While he talked about SPIE membership, altruistic activities, history, and publishing, a slide show rolled on one of the plenary room screens, showing images of Fellows of SPIE from the lithography community and photos from the numerous countries Arnold visited.
SPIE's membership includes a fast-growing student contingent, who are active in nearly 250 Student Chapters and Clubs in dozens of countries, Arnold said. Its "virtual" membership includes more than 14,000 members in the SPIE LinkedIn group and engagement with thousands more via Facebook pages, Twitter accounts, the SPIE.tv YouTube channel, and other social media.
Guided over the years by various committees and via a first-time popular vote by members in 2013, SPIE provides support for educational outreach, scholarships, free access to publications in qualifying countries and other activities, in line with the Society's mission to disseminate optics and photonics information as widely as possible. In 2013, Arnold noted, SPIE provided $3.2 million in support of education and outreach programs.
Arnold highlighted the Society's extensive publishing program, including the SPIE Digital Library containing nearly 400,000 conference proceedings papers and articles from its 12 peer-reviewed journals. Arnold displayed the very first "yellow book" -- the SPIE Proceedings print volume, characteristically bound in a yellow cover -- published in 1963 along with the first proceedings from the optical lithography conference, the precursor to SPIE Advanced Lithography, published in 1976.
Summing up, he urged the advanced lithography to get more involved - serve on SPIE committees, nominate deserving peers as Fellows of the Society, support the community's home journal, the Journal of Micro/Nanolithography, MEMS, and MOEMS, also known as JM3, with their article submissions.
Switching to a technical focus, Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon Division at Mentor Graphics Corporation, discussed the impact that ever-shrinking geometries have on design tools and manufacturers.
In his plenary talk titled, "Making the Impossible: Dealing with Patterns Throughout the Design and Manufacturing Flow," Sawicki noted that the dream scenario for lithographers -- a diffraction grating and its one-dimensional content -- doesn't get the industry very far. The introduction of line ends results in proximity effects driving the need for simple optical proximity corrections.
This simple approach has given way to more complicated solutions driven by the proliferation of complex patterns.
For those who work in electronic design automation (EDA), this means they must now put in place systems capable of simulating increasingly diverse sets of geometries. To improve manufacturability, many fabs have adopted restricted design rules limiting the number and types of geometries designers can use. This limitation began with front-end layers, namely poly and diffusion, but can now be found in back end layers as well.
The adoption of double-patterning schemes only made the challenge for design automation toolmakers and chip manufacturers more difficult, since now interplay between masks has to be considered.
Source mask optimization schemes provide one path to improved patterning fidelity, Sawicki said. Three-dimensional mask modeling taking into account such contributions as mask topography, resist profile and wafer topography enable additional refinement assuming one can obtain reasonable model accuracy for the computational complexity required. Inverse lithography techniques are also useful, particularly for addressing patterning hot spots.
Re detection and feedback schemes, Sawicki gave an example of the use of combinational logic to isolate defect areas and drive layout-aware diagnosis which can be used to study similar layouts. Moving from this to a detection scheme based on describing patterns in terms of pictures allowing for appropriate levels of ambiguity within that pattern and searching a design for this set of geometries allows for dealing with designs at a pattern level.
Looking towards the future, the expectation is that design and verification tools will continue to blend evolutionary trends such as enhancements to three dimensional mask design and yield learning with more revolutionary changes such as limiting geometries and pattern options available to designers.
Collaboration and integrated patterning solutions
The role of cooperation and collaboration was the theme that ran through Akihisa Sekiguchi's plenary talk, titled "Driving Device Scaling through Integrated Patterning Solutions." Sekiguchi is a Corporate Vice President and Deputy General Manager at Tokyo Electron Limited (TEL).
Scaling geometries have increased the complexity of patterning, Sekiguchi said. For example, in 2005, at the 65nm node, single exposure techniques were the norm, but, today, at the 22nm node, multiple passes are required to define critical features.
Patterning elements such as exposure wavelength, process conditions, masks, illumination conditions and optics have all evolved and must work together to enable scaling to be realized at the wafer level. Self-aligned multiple pass (SAMP) schemes add complexity and variability since each layer contributes errors which stack up rather than cancel out.
The situation will only increase in complexity as logic manufacturers see an increasing need for three dimensional features such as FinFET's as technology nodes dip below 10nm.
Integrated patterning solutions encompassing a flow including pre-patterning, multiplication, cut patterning, and line-cutting steps, with each step utilizing the appropriate material, processes, and equipment, are needed to address these scaling challenges. To address these ongoing challenges, Sekiguchi provided an overview of some of the work being done at TEL and which will be discussed in more detail in papers being presented at the Advanced Lithography conferences.
A new double-pattern freeze process combining a multi-pass scheme with a photoresist cure and silicon coating step prior to the second layer pass enables printing of geometries for future technology nodes. Collaborative efforts in EUV both between groups within TEL and across the EUV ecosystem were discussed as were similar efforts for directed self-assembly (DSA). In particular, for DSA, normalized data demonstrating a 100X improvement in defect density over the last year was presented and work continues in the areas of materials, etching and design.
In summary, Sekiguchi concluded that although lithography driven scaling is at its limits, an integrated and collaborative approach between the patterning community, materials suppliers and equipment suppliers provides the best pathway towards smaller geometries.
Outgoing symposium chair Harry Levinson (GLOLBALFOUNDRIES), at left, was presented with an award in appreciation for his contributions and leadership to SPIE Advanced Lithography. The presentation was made by his successor, Mircea Dusa (ASML), at right, and SPIE Immediate Past President Bill Arnold.
Levinson and Arnold also presented the Frits Zernike Award for Advances in Microlithography, sponosred by ASML, to Mordy Rothschild of MIT, and the 2013 Harold Edgerton Award to Martin Richardson, Director of the Townes Laser Institute, CREOL, College of Optics and Photonics, University of Central Florida. Award photos are in the event photo gallery.
Arnold also congratulated Frank Abboud (Intel), one of 76 new Fellows of the Society named this year. Abboud and other Fellows were guests of honor at a luncheon; see photos in the event photo gallery.
Tribute to a pioneer
The opening session of the conference on Metrology, Inspection, and Process Control for Microlithography included a tribute to Tencor founder, the late Karel Urbánek. On hand were Lida Urbánek and Bill Wheeler, shown above with conference chair Jason Cain (Advanced Micro Devices), at left, and former chair Alexander Starikov (I & I Consulting), at right. A new best paper award honoring Karel Urbánek is being sponsored by KLA Tencor and will be awarded for the first time on Thursday morning.
Overflowing on opening day
A talk by Tony Yen (TSMC) drew an overflow audience as conference sessions opened following the plenary talks. Yen presented on work co-authored by TSMC colleague Jack Jenghomg Chen, titled "Progress and challenges of EUV lithography for high-volume manufacturing" [9048-1].
Panel considers extending CMOS
In the week's first panel session "Extending the End of CMOS Through Nanotechnology" chaired by Richard Silver, Bryan Barnes, and Joseph Kline, all of NIST, experts shared their visions for how CMOS will trend in the future.
Panelists began with a short overview of their thoughts on the topic.
Reza Arghavani of Lam Research discussed the use of silicon FinFET's at the 22nm and 14nm nodes highlighting the need to replace silicon in the sub-10nm node regime with either Ge- or III-V-based materials.
New functionality would be essential for scaling, said An Chen of Global Foundries, who sees function-driven systems built on CMOS platforms and benefiting from low-power switching, structure and layout regularity, and more efficient logic implementation.
Intel's Florian Gstein spoke to the process simplification provided by EUV and directed self-assembly (DSA), techniques which mitigate pattern overlay complications brought on by other techniques.
Douglas Guerrero of Brewer Science focused on the positives and negatives of DSA and highlighted the relative merits of grapho- and chemo-epitaxy approaches.
The potential of e-beam lithography schemes was presented by Kees Hagen of TU-Delft as he described work done by his team producing sub-10nm geometries as part of a European Union project.
Daniel Herr from University of North Carolina Greensboro emphasized the importance of hybrid approaches and learning lessons taught by nature.
The gate-all-around approach was presented by Michael Guillorn of IBM as a technique which allows for gate and gate pitch scaling needed for the sub-10nm node regime.
After hearing the opinions and ideas put forth by the panel, the session was opened up to questions from the audience.
In response to the first question, on the future of EUV, Gstein said that since the issues are well known and solutions are not limited by fundamental physics constraints he expects to see these issues addressed. Guillorn commented that EUV is well-suited to handle complexities in circuit design encountered in the back end of the process, and Arghavani added that he expects EUV to be capable of sub-10nm node performance with the additional complexity of spacer patterning being needed. The topic turned to III-V materials with a question on their scaling potential.
Guillorn noted that one major piece missing in the III-V portfolio is a demonstration of scaled devices.
Arghavani discussed what he sees as the three major questions around these materials- the need for a high k gate material, the fact that unlike a single silicon atom the fundamental building block is now multiple atoms as in the case of a preferred III-V system, InGaAs, and the lack of salicide. Arghavani concluded that the need for a high k gate material was the most severe concern at this time.
The panel touched on scaling in the back end of the process while responding to another question.
Guillorn pointed out that metal pitch scaling is as aggressive as is that for gate pitch and discussed the need for some relief in design restrictions as well as the need for creative material engineering solutions as dimensions shrink.
Gstein agreed that back-end pitch scaling can be aggressive and noted that as dimensions continue to shrink, material properties may deviate from bulk behavior.
In response to a query on the biggest hurdles to DSA, Guerrero said that surface-layer defect control, particularly on the scale of 300mm or more, would be his biggest concern.
In final observations, Gstein used the example of chemically amplified resists to remind the audience that it does take time for new materials to mature and be adopted by the industry.
Arghavani said that these new challenges provide opportunities for inventions and innovations to meet the challenges.
Guillorn perhaps summed it up best by asking the question, "Why continue?" and then answering with an example of how increased computing power can improve fields such as medical imaging which impacts many lives on a daily basis.
The panel concluded that, while many issues exist to further scale CMOS, there are many avenues of pursuit and viable reasons for doing so.
Prizes -- and a BACUS piñata
Moderator Chris Progler (Photronics Inc.) offered audience members prizes or a swing at the BACUS piñata as a reward for asking questions at the BACUS panel discussion on "Managing EUV Masks in Wafer Fab."
Panelists and audience spent the evening exploring relevant fab management best practices to assess what might be applicable in the case of the EUV mask.
The panel was sponosred by KLA Tencor.
Sunday 23 February
SPIE Advanced Lithography returned to the San Jose Convention Center in the event's 38th year, opening today with the first of the week's 13 courses on current approaches in EUV lithography, DSA, multiple patterning, and more.
Conferences begin Monday morning following a plenary session -- it's going to be a busy week!
Books, posters, ties gifts at the Marketplace
The week's earliest shoppers stopped by the SPIE Marketplace to pick up free posters, browse new titles, and check out t-shirts, ties, and gifts on sale. The Marketplace is open during registration hours throughout the conference. New titles include:
- Field Guide to Lens Design, by Julie Bentley and Craig Olson
- Field Guide to Nonlinear Optics, by Peter E. Powers
- Field Guide to Physical Optics, by Daniel G. Smith
- Introduction to Semiconductor Manufacturing Technology, Second Edition, by Hong Xiao
- Laser Safety in the Lab, by Ken Barat
- Optical Imaging and Aberrations, Part III: Wavefront Analysis, by Virendra N. Mahajan
- The Proper Care of Optics: Cleaning, Handling, Storage, and Shipping, by Robert Schalck
Networking? Of course!
Networking opportunities among all segments of the community abound at Advanced Lithography. Participants in a KLA Tencor event enjoyed a reception break on Sunday, in one of many industry-sponsored events scheduled for the week.