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Proceedings of SPIE Volume 9781 • new

Design-Process-Technology Co-optimization for Manufacturability X
Editor(s): Luigi Capodieci
Format Member Price Non-Member Price
Softcover $67.50 $90.00

Volume Details

Volume Number: 9781
Date Published: 7 July 2016
Softcover: 43 papers (408) pages
ISBN: 9781510600164

Table of Contents
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Front Matter: Volume 9781
Author(s): Proceedings of SPIE
Toward the 5nm technology: layout optimization and performance benchmark for logic/SRAMs using lateral and vertical GAA FETs
Author(s): Trong Huynh-Bao; Julien Ryckaert; Sushil Sakhare; Abdelkarim Mercha; Diederik Verkest; Aaron Thean; Piet Wambacq
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Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs
Author(s): Hongyi Liu; Chuyang Hong; Ting Han; Jun Zhou; Yijian Chen
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Directed self-assembly aware restricted design rule and its impact on design ability
Author(s): Yulu Chen; Ryoung-han Kim
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Integrated routing and fill for self-aligned double patterning (SADP) using grid-based design
Author(s): Youngsoo Song; Jeemyung Lee; Seongmin Lee; Youngsoo Shin
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Integrated layout based Monte-Carlo simulation for design arc optimization
Author(s): Dongbing Shao; Larry Clevenger; Lei Zhuang; Lars Liebmann; Robert Wong; James Culp
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Impact of EUV patterning scenario on different design styles and their ground rules for 7nm/5nm node BEOL layers
Author(s): Tsann-Bim Chiou; Alek C. Chen; Mircea Dusa; Shih-En Tseng
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Methodology for analyzing and quantifying design style changes and complexity using topological patterns
Author(s): Jason P. Cain; Ya-Chieh Lai; Frank Gennari; Jason Sweis
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Using pattern enumeration to accelerate process development and ramp yield
Author(s): Linda Zhuang; Jenny Pang; Jessy Xu; Mengfeng Tsai; Amy Wang; Yifan Zhang; Jason Sweis; Ya-Chieh Lai; Hua Ding
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Optimization of self-aligned double patterning (SADP)-compliant layout designs using pattern matching for 10nm technology nodes and beyond
Author(s): Lynn T.-N. Wang; Uwe Paul Schroeder; Youngtag Woo; Jia Zeng; Sriram Madhavan; Luigi Capodieci
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Hybrid hotspot detection using regression model and lithography simulation
Author(s): Taiki Kimura; Tetsuaki Matsunawa; Shigeki Nojima; David Z. Pan
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Variability-aware compact modeling and statistical circuit validation on SRAM test array
Author(s): Ying Qiao; Costas J. Spanos
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Impacts of process variability of alternating-material self-aligned multiple patterning on SRAM circuit performance
Author(s): Ting Han; Chuyang Hong; Qi Cheng; Yijian Chen
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Modeling interconnect corners under double patterning misalignment
Author(s): Daijoon Hyun; Youngsoo Shin
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Model-based CMP aware RC extraction of interconnects in 16nm designs
Author(s): Yongchan Ban; Sang Min Han; Eunjoo Choi; Tamba Gbondo-Tugbawa; Kuang Han Chen
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Automatic layout feature extraction for lithography hotspot detection based on deep neural network
Author(s): Tetsuaki Matsunawa; Shigeki Nojima; Toshiya Kotani
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Pattern-based DTCO flow for early estimation of lithographic difficulty using optical image processing
Author(s): Moutaz Fakhry; Kareem Madkour; Wael ElManhawy; Jason Cain; Joe Kwan
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A random approach of test macro generation for early detection of hotspots
Author(s): Jong-hyun Lee; Chin Kim; Minsoo Kang; Sungwook Hwang; Jae-seok Yang; Mohammed Harb; Mohamed Al-Imam; Kareem Madkour; Wael ElManhawy; Joe Kwan
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Hotspot detection and removal flow using multi-level silicon-calibrated CMP models
Author(s): Ushasree Katakamsetty; Jansen Chee; Yongfu Li; Colin Hui; Jaime Bravo; Tamba Gbondo-Tugbawa; Brian Lee; Kuang-Han Chen; Aaron Gower-Hall; Sang-Min Han
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Migrating from older to newer technology nodes and discovering the process weak-points
Author(s): Linda Zhuang; Jenny Pang; Jessy Xu; MengFeng Tsai; Xue Long Shi; Qing Wei Liu; Ellyn Yang; Yifan Zhang; Jason Sweis; Ya-Chieh Lai; Hua Ding
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Triple/quadruple patterning layout decomposition via novel linear programming and iterative rounding
Author(s): Yibo Lin; Xiaoqing Xu; Bei Yu; Ross Baldick; David Z. Pan
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Design strategy for integrating DSA via patterning in sub-7 nm interconnects
Author(s): Ioannis Karageorgos; Julien Ryckaert; Maryann C. Tung; H.-S. Philip Wong; Roel Gronheid; Joost Bekaert; Evangelos Karageorgos; Kris Croes; Geert Vandenberghe; Michele Stucchi; Wim Dehaene
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Enablement of DSA for VIA layer with a metal SIT process flow
Author(s): L. Schneider; V. Farys; E. Serret; C. Fenouillet-Beranger
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Layout decomposition and synthesis for a modular technology to solve the edge-placement challenges by combining selective etching, direct stitching, and alternating-material self-aligned multiple patterning processes
Author(s): Hongyi Liu; Ting Han; Jun Zhou; Yijian Chen
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Interlayer design verification methodology using contour image
Author(s): Minyoung Shim; Seoksan Kim; Sungmin Park; Seiryung Choi; Namjung Kang; Hyunju Sung; Jinwoo Choi; Jaepil Shin; Jaekyun Park; Myoungseob Shim; Hyeongsun Hong; Kyupil Lee
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The new analysis method of PWQ in the DRAM pattern
Author(s): Daehan Han; Jinman Chang; Taeheon Kim; Kyusun Lee; Yonghyeon Kim; Jinyoung Kang; Aeran Hong; Bumjin Choi; Joosung Lee; Hyoung Jun Kim; Kweonjae Lee; Hyoungsun Hong; Gyoyoung Jin
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Verification and application of multi-source focus quantification
Author(s): J.-G. Simiz; T. Hasan; F. Staals; B. Le-Gratiet; W. T. Tel; C. Prentice; J.-W. Gemmink; A. Tishchenko; Y. Jourlin
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A comparative study on the yield performance of via landing and direct stitching processes for 2D pattern connection
Author(s): Jun Zhou; Yijian Chen
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Estimate design sensitivity to process variation for the 14nm node
Author(s): Guillaume Landié; Vincent Farys
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Design space exploration for early identification of yield limiting patterns
Author(s): Helen Li; Elain Zou; Robben Lee; Sid Hong; Square Liu; JinYan Wang; Chunshan Du; Recco Zhang; Kareem Madkour; Hussein Ali; Danny Hsu; Aliaa Kabeel; Wael ElManhawy; Joe Kwan
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Design technology co-optimization for 14/10nm metal1 double patterning layer
Author(s): Yingli Duan; Xiaojing Su; Ying Chen; Yajuan Su; Feng Shao; Recco Zhang; Junjiang Lei; Yayi Wei
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An integrated design-to-manufacturing flow for SADP
Author(s): Ahmed Hamed Fatehy; Rehab Kotb; James Word
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Using pattern analysis methods to do fast detection of manufacturing pattern failures
Author(s): Evan Zhao; Jessie Wang; Mason Sun; Jeff Wang; Yifan Zhang; Jason Sweis; Ya-Chieh Lai; Hua Ding
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Electron-beam lithography with character projection exposure for throughput enhancement with line-edge quality optimization
Author(s): Rimon Ikeno; Satoshi Maruyama; Yoshio Mita; Makoto Ikeda; Kunihiro Asada
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Rapid recipe formulation for plasma etching of new materials
Author(s): Meghali Chopra; Zizhuo Zhang; John Ekerdt; Roger T. Bonnecaze
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Expanding the printable design space for lithography processes utilizing a cut mask
Author(s): Jerome Wandell; Mohamed Salama; William Wilkinson; Mark Curtice; Jui-Hsuan Feng; Shao Wen Gao; Abhishek Asthana
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Characterization of shallow trench isolation CMP process and its application
Author(s): Helen Li; ChunLei Zhang; JinBing Liu; ZhengFang Liu; Kuang Han Chen; Tamba Gbondo-Tugbawa; Hua Ding; Flora Li; Brian Lee; Aaron Gower-Hall; Yang-Chih Chiu
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Advanced DFM application for automated bit-line pattern dummy
Author(s): Tae Hyun Shin; Cheolkyun Kim; Hyunjo Yang; Mohamed Bahr
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Wafer hotspot prevention using etch aware OPC correction
Author(s): Ayman Hamouda; Dave Power; Mohamed Salama; Ao Chen
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Building block style recipes for productivity improvement in OPC, RET and ILT flows
Author(s): Linghui Wu; Denny Kwa; Jinyin Wan; Tom Wang; Matt St. John; Steven Deeth; Xiaohui Chen; Tom Cecil; Xiaodong Meng; Kevin Lucas
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Hybrid pattern matching based SRAF placement
Author(s): Ahmed Omran; Andrey Lutich; Uwe Paul Schroeder
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LELE CD bias offset monitor through OVL measurement
Author(s): Chia Ching Lin; En Chuan Lio; Chang Mao Wang; Howard Chen; Sho Shen Lee; Henry Hsing; Kince Liu; Nuriel Amir
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Metal stack optimization for low-power and high-density for N7-N5
Author(s): P. Raghavan; F. Firouzi; L. Matti; P. Debacker; R. Baert; S. M. Y. Sherazi; D. Trivkovic; V. Gerousis; M. Dusa; J. Ryckaert; Z. Tokei; D. Verkest; G. McIntyre; K. Ronse
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