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Design-Process-Technology Co-optimization for Manufacturability VIII
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Volume Details

Volume Number: 9053
Date Published: 22 April 2014
Softcover: 33 papers (328) pages
ISBN: 9780819499769

Table of Contents
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Front Matter: Volume 9053
Author(s): Proceedings of SPIE
Lithography-induced limits to scaling of design quality
Author(s): Andrew B. Kahng
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A pattern-driven design regularization methodology
Author(s): Jason P. Cain; Norma P. Rodriguez; Jason Sweis; Frank E. Gennari; Ya-Chieh Lai
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Systematic physical verification with topological patterns
Author(s): Vito Dai; Ya-Chieh Lai; Frank Gennari; Edward Teoh; Luigi Capodieci
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Synthesis of lithography test patterns through topology-oriented pattern extraction and classification
Author(s): Seongbo Shim; Woohyun Chung; Youngsoo Shin
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Systematic data mining using a pattern database to accelerate yield ramp
Author(s): Edward Teoh; Vito Dai; Luigi Capodieci; Ya-Chieh Lai; Frank Gennari
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Layout pattern-driven design rule evaluation
Author(s): Yasmine Badr; Ko-wei Ma; Puneet Gupta
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Bridging the gap from mask to physical design for multiple patterning lithography
Author(s): Bei Yu; Jhih-Rong Gao; Xiaoqing Xu; David Z. Pan
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Demonstrating production quality multiple exposure patterning aware routing for the 10NM node
Author(s): Lars Liebmann; Vassilios Gerousis; Paul Gutwin; Mike Zhang; Geng Han; Brian Cline
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A fast triple patterning solution with fix guidance
Author(s): Weiping Fang; Srini Arikati; Erdem Cilingir; Marco A. Hug; Peter De Bisschop; Julien Mailfert; Kevin Lucas; Weimin Gao
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Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques
Author(s): Yijian Chen; Jun Zhou; Jun You; Hongyi Liu
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Self-aligned quadruple patterning-aware routing
Author(s): Fumiharu Nakajima; Chikaaki Kodama; Hirotaka Ichikawa; Koichi Nakayama; Shigeki Nojima; Toshiya Kotani
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Accurate lithography hotspot detection based on PCA-SVM classifier with hierarchical data clustering
Author(s): Jhih-Rong Gao; Bei Yu; David Z. Pan
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Model based multilayers fix for litho hotspots beyond 20nm node
Author(s): Asmaa Rabie; Kareem Madkour; Kirolos George; Wael ElManhawy; Jean-Marie Brunet; Joe Kwan
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Configurable hot spot fixing system
Author(s): Masanari Kajiwara; Sachiko Kobayashi; Hiromitsu Mashita; Ryota Aburada; Nozomu Furuta; Toshiya Kotani
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"Smart" source, mask, and target co-optimization to improve design related lithographically weak spots
Author(s): No-Young Chung; Pil-Soo Kang; Na-Rae Bang; Jong-Du Kim; Suk-Ju Lee; Byung-Il Choi; Bong-Ryoul Choi; Sung-Woon Park; Ki-Ho Baik; Stephen Hsu; Rafael Howell; Xiaofeng Liu; Keith Gronlund
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Layout induced variability and manufacturability checks in FinFETs process
Author(s): Yongchan Ban; Jason Sweis; Philippe Hurat; Ya-Chieh Lai; Yongseok Kang; Woo Hyun Paik; Wei Xu; Huiyuan Song
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Layout optimization of DRAM cells using rigorous simulation model for NTD
Author(s): Jinhyuck Jeon; Shinyoung Kim; Chanha Park; Hyunjo Yang; Donggyu Yim; Bernd Kuechler; Rainer Zimmermann; Thomas Muelders; Ulrich Klostermann; Thomas Schmoeller; Mun-hoe Do; Jung-Hoe Choi
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Lithography yield estimation model to predict layout pattern distortions with a reduced set of lithography simulations
Author(s): Sergio Gómez; Francesc Moll; Juan Mauricio
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Technology-design-manufacturing co-optimization for advanced mobile SoCs
Author(s): Da Yang; Chock Gan; P. R. Chidambaram; Giri Nallapadi; John Zhu; S. C. Song; Jeff Xu; Geoffrey Yeap
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Optimizing standard cell design for quality
Author(s): Chimin Yuan; Dave Tipple; Jeff Warner
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Analysis and optimization of process-induced electromigration on signal interconnects in 16nm FinFET SoC (system-on-chip)
Author(s): Yongchan Ban; Changseok Choi; Hosoon Shin; Yongseok Kang; Woo Hyun Paik
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Design technology co-optimization for a robust 10nm Metal1 solution for logic design and SRAM
Author(s): Boris Vandewalle; Bharani Chava; Sushil Sakhare; Julien Ryckaert; Mircea Dusa
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Physical verification and manufacturing of contact/via layers using grapho-epitaxy DSA processes
Author(s): J. Andres Torres; Kyohei Sakajiri; David Fryer; Yuri Granik; Yuansheng Ma; Polina Krasnova; Germain Fenger; Seiji Nagahara; Shinichiro Kawakami; Benjamen Rathsack; Gurdaman Khaira; Juan de Pablo; Julien Ryckaert
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ECO fill: automated fill modification to support late-stage design changes
Author(s): Greg Davis; Jeff Wilson; J. J. Yu; Anderson Chiu; Yao-Jen Chuang; Ricky Yang
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Yield-aware decomposition for LELE double patterning
Author(s): Yukihide Kohira; Yoko Yokoyama; Chikaaki Kodama; Atsushi Takahashi; Shigeki Nojima; Satoshi Tanaka
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A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method
Author(s): Qi Cheng; Jun You; Yijian Chen
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Localization concept of re-decomposition area to fix hotspots for LELE process
Author(s): Yoko Yokoyama; Keishi Sakanushi; Yukihide Kohira; Atsushi Takahashi; Chikaaki Kodama; Satoshi Tanaka; Shigeki Nojima
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Decomposition-aware layout optimization for 20/14nm standard cells
Author(s): Lynn T. -N. Wang; Sriram Madhavan; Shobhit Malik; Eric Chiu; Luigi Capodieci
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Resist profile aware source mask optimization
Author(s): Ao Chen; Yee Mei Foong; Michael Hsieh; Andrew Khoh; Stephen Hsu; Mu Feng; Jianhong Qiu; Chris Aquino
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Robust and automated solution for correcting hotspots locally using cost-function based OPC solver
Author(s): Carl Babcock; Dongok Yang; Sarah McGowan; Jun Ye; Bo Yan; Jianhong Qiu; Stanislas Baron; Taksh Pandey; Sanjay Kapasi; Chris Aquino
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A layout decomposition algorithm for self-aligned multiple patterning
Author(s): Jun You; Hongyi Liu; Yijian Chen
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Work smarter not harder: How to get more results with less modeling
Author(s): Kareem Madkour; Fedor Pikus; Mohab Anis
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Scanner correction capabilities aware CMP lithography hotspot analysis
Author(s): Ushasree Katakamsetty; Hui Colin; Sky Yeo; Perez Valerio; Yang Qing; Quek Shyue Fong; Narayana Samy Aravind; Ruhm Matthias; Schiwon Roberto
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