This PDF file contains the front matter associated with SPIE Proceedings Volume 8764, including the Title Page, Copyright Information, Table of Contents, and the Conference Committee listing.

A new low-voltage high-speed CMOS fully-differential adaptive equalizer based on the spectrum-balancing technique is presented. It was designed to compensate the strong attenuation of the transmitted signal through a 50-m length SI-POF. The proposed equalizer, which targets a 2.5 Gb/s transmission for a simple NRZ modulation, was designed in a standard 0.18-μm CMOS process and uses a 1-V supply voltage with a total power consumption below 17.3 mW. An enhancement in the signal BW from 100 MHz to 1.8 GHz for a 50-m POF length is achieved.

The demand of voltage-controlled oscillators (VCOs) with a broad tuning range can lead to unacceptable degradation of the 1/f³ phase-noise component if traditional voltage-biased topologies are implemented. In this paper, a novel VCO architecture is proposed, where a segmented transconductor tailors the negative-g_m depending on the operating range to ensure that flicker noise up-conversion remains minimal. The implemented oscillator covers both 4G and WiMAX 2.5-GHz operation modes and achieves a 10-dB reduction of the 1/f³ phase noise without impairing the 1/f² phase-noise performance.

The objective of this work is to study the possibility of implementing SOI rectennas for UWB RFIDs, with undoped Double Gate MOSFETs (DG-MOSFETs). For that purpose we use two commercial TCAD tools: Sentaurus Device (created by Synopsys), and ADS (created by Agilent) where in a large signal circuit model derived for the transistors is implemented with Verilog-A. Once the DG-MOSFETs output characteristics are fit, the rectennas performance at high frequencies is simulated; numerical and electrical results are successfully compared.

In the last few years the continuous demand of energy saving has brought continuous research on low-power devices, energy storage and new sources of energy. Energy harvesting is an interesting solution that captures the energy from the environment that would otherwise be wasted. This work presents an electric-mechanical model of a piezoelectric transducer in a cantilever configuration. The model has been characterized measuring the acceleration and the open circuit voltage of a piezoelectric cantilever subjected to a sinusoidal force with different values frequency and subject to an impulsive force. The model has been used to identify the optimal position in which the piezoelectric cantilever has to be placed on a shoe in order to obtain the maximum energy while walking or running. As a second step we designed the DC-DC converter with an hysteresis comparator. The circuit is able to give energy to switch on a microprocessor for the amount of time long enough to capture and store the information required. The complete system has been implemented, installed on a shoe and used in a 10 Km running competition.

This paper presents a simple 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 68.6 μW power consumption, simulations shows a 81 dB open loop gain, 64° phase margin, 13 MHz unity gain frequency for a capacitive load of 10pF and 75 dB CMRR. Adaptive biasing provides 30.7 V/μs slew-rate for a 10 pF load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. The designed LIA has a power consumption of 135 μW and recovers signals up to 1 MHz with relative errors below 2.6 % for noise and interference signals of the same amplitude as the signal of interest.

Steganalysis is a process to detect hidden data in cover documents, like digital images, videos, audio files, etc. This is the inverse process of steganography, which is the used method to hide secret messages. The widely use of computers and network technologies make digital files very easy-to-use means for storing secret data or transmitting secret messages through the Internet. Depending on the cover medium used to embed the data, there are different steganalysis methods. In case of images, many of the steganalysis and steganographic methods are focused on JPEG image formats, since JPEG is one of the most common formats. One of the main important handicaps of steganalysis methods is the processing speed, since it is usually necessary to process huge amount of data or it can be necessary to process the on-going internet traffic in real-time. In this paper, a JPEG steganalysis system is implemented in an FPGA in order to speed-up the detection process with respect to software-based implementations and to increase the throughput. In particular, the implemented method is the JPEG-compatibility detection algorithm that is based on the fact that when a JPEG image is modified, the resulting image is incompatible with the JPEG compression process.

This paper describes key concepts in the design and implementation of a deblocking filter (DF) for a H.264/SVC video decoder. The DF supports QCIF and CIF video formats with temporal and spatial scalability. The design flow starts from a SystemC functional model and has been refined using high‐level synthesis methodology to RTL microarchitecture. The process is guided with performance measurements (latency, cycle time, power, resource utilization) with the objective of assuring the quality of results of the final system. The functional model of the DF is created in an incremental way from the AVC DF model using OpenSVC source code as reference. The design flow continues with the logic synthesis and the implementation on the FPGA using various strategies. The final implementation is chosen among the implementations that meet the timing constraints. The DF is capable to run at 100 MHz, and macroblocks are processed in 6,500 clock cycles for a throughput of 130 fps for QCIF format and 37 fps for CIF format. The proposed architecture for the complete H.264/SVC decoder is composed of an OMAP 3530 SOC (ARM Cortex‐A8 GPP + DSP) and the FPGA Virtex‐5 acting as a coprocessor for DF implementation. The DF is connected to the OMAP SOC using the GPMC interface. A validation platform has been developed using the embedded PowerPC processor in the FPGA, composing a SoC that integrates the frame generation and visualization in a TFT screen. The FPGA implements both the DF core and a GPMC slave core. Both cores are connected to the PowerPC440 embedded processor using LocalLink interfaces. The FPGA also contains a local memory capable of storing information necessary to filter a complete frame and to store a decoded picture frame. The complete system is implemented in a Virtex5 FX70T device.

Current tendencies of consumer electronics have envisaged multiprocessor System-on-Chip (SoC) as a promising solution for the high performance embedding systems, and, in this scenario, Network-on-chip communication paradigm is considered as a way to improve on-chip communication efficiency. In this paper, a NoC based SoC emulation framework is designed and implemented on a low-cost FPGA device. The objective of this work is the design and implementation of a prototyping platform with NoC topology, which provides a demonstrator for the implementation of multimedia applications. The emulation platform will allow evaluation, comparison, and verification of different aspects of a NoC design for SoCs intended for the execution of multimedia applications. The proposed emulation platform consists of different type of functional IP blocks (microprocessors, memory blocks, peripherals, additional blocks, etc.) interconnected through an interconnection infrastructure based on NoC. In order to provide a low-cost solution, the platform design is restricted to use a single FPGA, resulting in a low-scale SoC due to the limited resources available in the FPGA used. However, the proposed design may be scalable and replicate in large scale FPGA or multi-FPGA devices to increase emulation performance. In this work, a design flow, which integrates different commercial EDA tools, is presented, and integration process is discussed in detail due to problems experienced in this stage. The platform is fully implemented on a Xilinx Spartan-6 LX45T FPGA and special attention is given to verification and floorplanning stages. Finally, various multimedia applications with real-time requirements are executed on the NoC-based SoC platform. At this stage, the performance results are analyzed according to the type of application, as well as the number of processors required.

Reliability and noise tolerance represent important requirements for digital networked systems, especially in critical working conditions. These issues mostly concern the communication tasks between the network nodes, which are usually implemented on the basis of formal protocol rules. A challenging target for a reliability analysis is to provide comprehensive evaluations and acceptably accurate results. However, the current complexity of many network applications entails relevant limitations to this possibility. In this paper we present a novel system-level methodology for noise analysis of digital networked systems. In our research we have defined a simulation/analytical approach entirely based on the protocol specifications and capable to address a fast and comprehensive study of the reliability properties. The proposed methodology is illustrated through a case study on the MOST 150 protocol, which is currently used to realize multimedia networks in automotive contexts.

This paper describes a simulation method to compute oscillator phase noise which combines transient and periodic-transfer-function analyses, available in most of the commercial circuit simulators. The proposed calculation technique is simple to implement and provides the designer a deep insight into phase noise generation mechanisms for both stationary and cyclostationary sources, thus resulting a powerful tool to perform an optimum design in RF applications.

Hardware virtualization is a major challenge in embedded virtualization. The key to improving resource utilization in a virtualized system is to allow maximum possible resource access operations to perform natively with minimal intervention by the virtual machine monitor, while at the same time ensuring protected operation among different virtual machines’ address space. An innovative I/O Memory Management Unit component (IOMMU) is architected to enable mapping of virtual addresses from multiple devices to the correct VM’s physical memory locations, offering enhanced protection, scatter-gather functions on distributed memory organizations, high performance supported by a configurable TLB and an integrated lightweight hardware monitoring unit to facilitate dynamic system optimizations. This new IOMMU is designed in a modular way supporting address translation along with protection and security extensions. The principal objective is to ensure device isolation by safely mapping a device to a particular guest without risking the integrity of other guests. Additionally, the IOMMU is designed to provide an increased level of security in scenarios without virtualization; with the aid of the IOMMU, the operating system is able to protect itself from malicious device drivers by limiting a device's memory accesses and managing the permissions of peripheral devices.

A system-level implementation of FFT architecture for long data series is presented. It exploits opportunities provided by the newest Programmable System-on-Chips (PSoC) to perform such intensive algorithms. The proposed strategy relies on a balanced partitioning of computational e ort between an embedded ARM processor and an on-purpose designed FFT module based on a Radix-2 algorithm. The external memories are used to accommodate the large amount of complex data and twiddle coefficients. The embedded controller is purposely programmed to allow the high-level management of the algorithm and the correct flow of data among peripherals, without need of extra control logic. The proposed architecture can be easily reconfigured, in order to change input data length. When implemented using a Microsemi A2F500 SmartFusion FPGA chip, it consumes approximately 61% of available logic resources to compute a 65536-point FFT.

In this paper, a 64 state soft decision Viterbi Decoder (VD) system by using a high speed radix-4 Add Compare Select (ACS) architecture is presented. The proposed VD system can support different data rate (from 53.5 Mbps to 480 Mbps) for Multiband Orthogonal Frequency-division Multiplexing (MB-OFDM) Ultra-Wideband (UWB) system when implemented onto the FPGA board. The proposed VD employs efficient two steps Radix 4 architecture, which is responsible of calculating two steps of 64 state Radix 4 Branch Metrics (BM) within one clock cycle. The branch metrics are calculated using a uniform distance measurement algorithm, which equals to the symbol itself when compared to logic-0 and equal to its one’s complement when compared to logic-1. By employing the modified Modulo Normalization algorithm, it is possible to use only a 10- bit memory block to restore each of the 64 state metrics, with the advantage of avoiding errors caused by overflow during the updating process for state metrics, and simplifying the comparator circuit of the ACS unit. The Two Pointer Even Algorithm, which is considered to be very simple and more hardware-efficient than the register exchange algorithm, is used for tracing back the survivor sequence and output the decoded data stream. 3-bit soft decision input sequences are used for gathering the experimental results. The sampling frequency of the MBOFDM UWB system is 528 MHz, by using the proposed two steps Radix 4 VD architecture we can process 4 input signals in parallel within one clock cycle, therefore only 132 MHz operating frequency is needed for the proposed VD system. This will dramatically reduce the dynamic power consumption for hardware implementation. Final results of the implementation show that the proposed VD architecture can support a maximum working frequency of 152.5 MHz on Xilinx XUPV5-LX110T Evaluation Platform.

In modern high-speed data communications systems, the limited bandwidth of the channel results in inter-symbol interference (ISI) at the received signal, which has to be compensated by equalization. Typically, equalization at the receiver is preferred to equalization at the emitter because it can be designed to take into account the varying characteristics of the channel in what is called adaptive equalization. Continuous-time adaptive equalizers base their operation on the fact that the spectrum of the incoming signal is known prior to its reception, so the degradation caused by the channel can be evaluated and subsequently corrected by comparing the power measured at different frequency ranges with the value expected in theory. In this paper, an ideal pseudo-random NRZ signal will be used, whose power spectrum can be described by a squared sinc function. Four different architectures have been proposed in the literature to carry out power spectrum comparison: two band-pass filters; one high-pass and one low-pass filter; one all-pass and one low-pass filter; and two low-pass filters. This work analyzes the differences between these techniques on the operation of continuous-time adaptive equalizers, establishing filter design criteria based on the characteristics of the channel and the equalizer filter. The paper is organized as follows: Section I is the introduction; Section 2 gives and overview of the spectrum balancing technique architectures; Section 3 outlines the proposed criteria to set the filter bandwidth; finally, conclusions are drawn in Section 4.

Benefits of dynamic and partial reconfigurable systems are increasingly being more accepted by the industry. For this reason, SRAM-based FPGA manufacturers have improved, or even included for the first time, the support they offer for the design of this kind of systems. However, commercial tools still offer a poor flexibility, which leads to a limited efficiency. This is witnessed by the overhead introduced by the communication primitives, as well as by the inability to relocate reconfigurable modules, among others. For this reason, authors have proposed an academic design tool called DREAMS, which targets the design of dynamically reconfigurable systems. In this paper, main features offered by DREAMS are described, comparing them with existing commercial and academic tools. Moreover, a graphic user interface (GUI) is originally described in this work, with the aim of simplifying the design process, as well as to hide the low level device dependent details to the system designer. The overall goal is to increase the designer productivity. Using the graphic interface, different reconfigurable architectures are provided as design examples. Among them, both conventional slot-based architectures and mesh type designs have been included.

Wireless Sensor Networks (WSNs) include low-power and low-cost devices (nodes) with demanding power requirements (long autonomous lifetime). The nodes have to use the available battery carefully and avoid expensive computations or radio transmissions. Therefore, effective simulation mechanisms that allow the developer to obtain estimations at the early stages of the WSN design, prior to deployment, are necessary. Power consumption is not the only important concern in this design but security is becoming a real problem too, since some WSNs process sensitive data. Thus, it is necessary to ensure that the processed data are tamper-proof. This paper proposes a framework for network simulation and embedded SW performance analysis that focuses not only on time and power estimation but also on two new metrics: the “entropy security-oriented metric” provides information about the security encryption used in WSN transmissions and the “heterogeneity metric” provides information to help avoid “replication attacks”. All this information will aid in the whole WSN deployment design, providing useful metrics about power and security.

One of the limiting factors that have prevented a widely dissemination of the reconfigurable technology is the absence of an appropriate model for certain target applications capable of offering a reliable control. Moreover, the lack of flexible and easy-to-use scheduling and management systems are also relevant drawbacks to be considered. Under static scenarios, it is relatively easy to schedule and manage the reconfiguration process since all the variations corresponding to predetermined and well-known tasks. However, the difficulty increases when the adaptation needs of the overall system change semi-randomly according to the environmental fluctuations. In this context, this work proposes a change in the paradigm of dynamically reconfigurable systems, by attending to the dynamically reconfigurable control problematic as a whole, in which the scheduling and the placement issues are packed together as a hierarchical management structure, interacting together as one entity from the system point of view, but performing their tasks with certain degree of independence each other. In this sense, the top hierarchical level corresponds with a dynamic scheduler in charge of planning and adjusting all the reconfigurable modules according to the variations of the external stimulus. The lower level interacts with the physical layer of the device by means of instantiating, relocating, removing a reconfigurable module following the scheduler’s instructions. In regards to how fast is the proposed solution, the total partial reconfiguration time achieved with this proposal has been measured and compared with other two approaches: 1) using traditional Xilinx’s tools; 2) using an optimized version of the Xilinx's drivers. The collected numbers demonstrate that our solution reaches a gain up to 10 times faster than the other approaches.

Multimedia embedded systems usually expose a chain-based architecture where each functional stage of the media algorithm is encapsulated in a media core in charge of processing the stream of data. Therefore, in this kind of systems, the interconnection mechanisms are key to cope with the enormous bandwidth demands. In this paper, we present a decentralized data transfer architecture for bus based embedded systems. The communication infrastructure introduced here is parameterizable, dynamically configurable and optimized for hardware media component processing platforms. Unlike conventional approaches, where a software control routine has to oversee all the steps of the data exchanging process (e.g. DMA configuration, trapping interruptions, ...), our approach moves such responsibility to the hardware components which are highly autonomous. This has a positive impact in performance since the processor is not mediating in every single data transfer that takes place in the system.

Collaborative hardening and hardware redundancy are nowadays the most interesting solutions in terms of fault tolerance achieved and low extra cost imposed to the project budget. Thanks to the powerful and cheap digital devices that are available in the market, extra processing capabilities can be used for redundant tasks, not only in early data processing (sensed data) but also in routing and interfacing¹

The utilization of SRAM-based FPGAs in the implementation of embedded systems is in continuous growth. The flexibility that these devices offer in terms of hardware re-programming can be also a critical point to take into account when designing fault tolerant systems. As configuration values are stored in volatile memory, any event that affects this configuration memory can lead to undesirable changes in the circuits and as a consequence, erroneous outcomes can be obtained. This paper presents an approach to add fault tolerance in an aerospace application implemented in a commercial-off-the shelf FPGA (Virtex-5). By using this device, the partial reconfiguration facility can be exploited. This feature allows us to get more flexibility in hardware management at run-time also as a mean to correct specific parts of the system when faults are detected. Results regarding influence in area by using different approaches are presented.

The introduction of hardware virtualization extensions on ARM Cortex-A15 processors has enabled the implementation of full virtualization solutions for this architecture, such as KVM on ARM. This trend motivates the need to quantify and understand the performance impact, emerged by the application of this technology. In this work we start looking into some interesting performance metrics on KVM for ARM processors, which can provide us with useful insight that may lead to potential improvements in the future. This includes measurements such as interrupt latency and guest exit cost, performed on ARM Versatile Express and Samsung Exynos 5250 hardware platforms. Furthermore, we discuss additional methodologies that can provide us with a deeper understanding in the future of the performance footprint of KVM. We identify some of the most interesting approaches in this field, and perform a tentative analysis on how these may be implemented in the KVM on ARM port. These take into consideration hardware and software based counters for profiling, and issues related to the limitations of the simulators which are often used, such as the ARM Fast Models platform.

It is well known that VLSI circuits must be designed to sustain the variations in process, voltage, temperature, etc. As a result, standard cell libraries (collections of the basic circuit components) are usually designed with large margin (also known as “timing slack”). However, in circuit manufacturing, only part of the margin will be utilized. The knowledge of the rest of the margin (over-designed timing slack), armed with models that link between timing domain and shape domain, can help to reduce the complexity of mask patterns and manufacturing cost. This paper proposed a novel methodology to simplify mask patterns in optical proximity correction (OPC) by using extra margin in timing (over-designed timing slack). This methodology can be applied after a conventional OPC, and is compatible with the current application-specific integrated circuit (ASIC) design flow. This iterative method is applied to each occurrence of over-designed timing slack. The actual value of timing slack can be estimated from post-OPC simulation. A timing cost function is developed in this work to map timing slack in timing domain to mask patterns in shape domain. This enables us to adjust mask patterns selectively based on the outcome of the cost function. All related mask patterns with over-designed timing slack will be annotated and simplified using our proposed mask simplification algorithm, which is in fact to merge the nearby edge fragments on the mask patterns. Simulations are conducted on a standard cell library and a full chip design to validate this proposed approach. When compared to existing OPC methods without mask simplification in the literature, our approach achieved a 51% reduction in mask fragment count, and this directly leads to a large saving in lithography manufacturing cost. The result also shows that timing closure is ensured, though part of the timing slack has been sacrificed.

In the last few years the increased development of wireless technologies led to the development of micropower devices with power management and real time power control, aimed to maximize the battery life time.¹ The main and simplest method to estimate residual battery life time is by voltage measurement. This kind of measurement is simple but is useless in many cases, especially when long term Lithium-Thionyl chloride batteries are used, since its voltage is flat for more than 90% of the battery discharge. In this case, a current control should be used. However, these kinds of devices have various problems as a limited range of measurement and not negligible quiescent current that may distort the measurements. In this work we developed a micropower supervisor for wireless sensor nodes with a charge battery monitor, whose features are aimed at solving the problems just described. The current measured by a sense resistor, is filtered by a super-capacitor, amplified by a current sense amplifier and then fed to a voltage to pulse frequency modulator. In this way, the charge consumption can be estimated without the saturation of the current sense amplifier, even if the wireless node consumes time limited high current spikes, for example during transmission.

In recent years, IEEE 802.15.4-based Wireless Sensor Networks (WSN) have experienced significant growth, mainly motivated by the standard features, such as small size oriented devices, low power consumption nodes, wireless communication links, and sensing and data processing capabilities. In this paper, the development, implementation and deployment of a novel fully compatible IEEE 802.15.4-based WSN architecture for applications operating over extended geographic regions with high node mobility support, is described. In addition, a practical system implementation of the proposed WSN architecture is presented and described for experimental validation and characterization purposes.

Sensorial materials consisting of high-density, miniaturized, and embedded sensor networks require new robust and reliable data processing and communication approaches. Structural health monitoring is one major field of application for sensorial materials. Each sensor node provides some kind of sensor, electronics, data processing, and communication with a strong focus on microchip-level implementation to meet the goals of miniaturization and low-power energy environments, a prerequisite for autonomous behaviour and operation. Reliability requires robustness of the entire system in the presence of node, link, data processing, and communication failures. Interaction between nodes is required to manage and distribute information. One common interaction model is the mobile agent. An agent approach provides stronger autonomy than a traditional object or remote-procedure-call based approach. Agents can decide for themselves, which actions are performed, and they are capable of flexible behaviour, reacting on the environment and other agents, providing some degree of robustness. Traditionally multi-agent systems are abstract programming models which are implemented in software and executed on program controlled computer architectures. This approach does not well scale to micro-chip level and requires full equipped computers and communication structures, and the hardware architecture does not consider and reflect the requirements for agent processing and interaction. We propose and demonstrate a novel design paradigm for reliable distributed data processing systems and a synthesis methodology and framework for multi-agent systems implementable entirely on microchip-level with resource and power constrained digital logic supporting Agent-On-Chip architectures (AoC). The agent behaviour and mobility is fully integrated on the micro-chip using pipelined communicating processes implemented with finite-state machines and register-transfer logic. The agent behaviour, interaction (communication), and mobility features are modelled and specified on a machine-independent abstract programming level using a state-based agent behaviour language (APL). With this APL a high-level agent compiler is able to synthesize a hardware model (RTL, VHDL), a software model (C, ML), or a simulation model (XML) suitable to simulate a multi-agent system using the SeSAm simulator framework. Agent communication is provided by a simple tuple-space database implemented on node level providing fault tolerant access of global data. A novel synthesis development kit (SynDK) based on a graph-structured database approach is introduced to support the rapid development of compilers and synthesis tools, used for example for the design and implementation of the APL compiler.

This paper presents STAR, a flexible Telemetry, Tracking & Command (TT&C) transponder for Earth Observation (EO) small satellites, developed in collaboration with INTECS and SITAEL companies. With respect to state-of-the-art EO transponders, STAR includes the possibility of scientific data transfer thanks to the 40 Mbps downlink data-rate. This feature represents an important optimization in terms of hardware mass, which is important for EO small satellites. Furthermore, in-flight re-configurability of communication parameters via telecommand is important for in-orbit link optimization, which is especially useful for low orbit satellites where visibility can be as short as few hundreds of seconds. STAR exploits the principles of digital radio to minimize the analog section of the transceiver. 70MHz intermediate frequency (IF) is the interface with an external S/X band radio-frequency front-end. The system is composed of a dedicated configurable high-speed digital signal processing part, the Signal Processor (SP), described in technology-independent VHDL working with a clock frequency of 184.32MHz and a low speed control part, the Control Processor (CP), based on the 32-bit Gaisler LEON3 processor clocked at 32 MHz, with SpaceWire and CAN interfaces. The quantization parameters were fine-tailored to reach a trade-off between hardware complexity and implementation loss which is less than 0.5 dB at BER = 10^-5 for the RX chain. The IF ports require 8-bit precision. The system prototype is fitted on the Xilinx Virtex 6 VLX75T-FF484 FPGA of which a space-qualified version has been announced. The total device occupation is 82 %.

This paper presents the design and optimization of an RF energy harvesting system from multiple sources. The RF power is harvested from four frequency bands representing five wireless systems, namely GSM, UMTS, DTV, Wi-Fi, and road tolling system. A Schottky diode model was developed based on which an RF-DC rectifier joined with a voltage multiplier circuits were designed. The simulation results of the complete RF harvesting system showed superior performance to similar state of the art systems. To further optimize the design, and to eliminate use of a non-standard CMOS process associated with Schottky diodes, the Schottky diode based rectifier was replaced by diode connected transistor configuration based on self-threshold cancellation (SVC) technique.

Because of the increasing in power density of electronic devices for medium and high power application, reliabilty of these devices is of great interest. Understanding the avalanche behaviour of a power device has become very important in these last years because it gives an indication of the maximum energy ratings which can be seen as an index of the device ruggedness. A good description of this behaviour is given by the static IV blocking characteristc. In order to avoid self heating, very relevant in high power devices, very short pulses of current have to be used, whose value can change from few milliamps up to tens of amps. The most used method to generate short pulses is the TLP (Transmission Line Pulse) test, which is based on charging the equivalent capacitance of a transmission line to high value of voltage and subsequently discharging it onto a load. This circuit let to obtain very short square pulses but it is mostly used for evaluate the ESD capability of semiconductor and, in this environment, it generates pulses of low amplitude which are not high enough to characterize the avalanche behaviour of high power devices . Advanced TLP circuit able to generate high current are usually very expensive and often suffer of distorption of the output pulse. In this article is proposed a simple, low cost circuit, based on a boosted-TLP configuration, which is capable to produce very square pulses of about one hundreds of nanosecond with amplitude up to some tens of amps. A prototype is implemented which can produce pulses up to 20A of amplitude with 200 ns of duration which can characterize power devices up to 1600V of breakdown voltage. Usage of microcontroller based logic make the circuit very flexible. Results of SPICE simulation are provided, together with experimental results. To prove the effectiveness of the circuit, the I-V blocking characteristics of two commercial devices, namely a 600V PowerMOS and a 1200V Trench-IGBT, are measured at different operating temperature.

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed but they optimize the performance for a given ASIC (Application Specific Integrated Circuits) technology. Nowadays, FPGA are very often used for the release of electronic systems. As a consequence, the study of the performance of advanced DDFS design techniques when implemented on FPGA devices, is of great interest. The paper presents various implementation of state of the art DDFS on various FPGA and compares their performance providing hints on optimal design as a function of the chosen performance parameter.

In this paper, an infrared wireless communication system based on Multiple Pulse Position Modulation (MPPM) employing angle-diversity detection is studied via simulation. The system can also be easily adapted for Visible Light Communications. MPPM is proposed as a modulation method to improve bandwidth efficiency in PPM. The system designed allows for comparing the performance based on the computation of the bit error rate (BER) as a function of the SNR for different MPPM and PPM modulation schemes employing angle-diversity detection. In this paper, two of the three ways to achieve angle-diversity detection are studied: conventional and sectored receivers. The results show a significant enhancement when angle-diversity receivers are employed, with the sectored receiver offering the highest performance. Furthermore, the results show that PPM offers a good performance for lower bit rates, though the BER increases rapidly when the bit rate is increased, even when angle-diversity receivers are used. MPPM proves to be more bandwidth efficient than PPM, since it allows to use a wider pulse for transmission of the same number of information bits per symbol.

The identification of moving objects is a fundamental step in computer vision processing chains. The development of low cost and lightweight smart cameras steadily increases the request of efficient and high performance circuits able to process high definition video in real time. The paper proposes two processor cores aimed to perform the real time background identification on High Definition (HD, 1920 1080 pixel) video streams. The implemented algorithm is the OpenCV version of the Gaussian Mixture Model (GMM), an high performance probabilistic algorithm for the segmentation of the background that is however computationally intensive and impossible to implement on general purpose CPU with the constraint of real time processing. In the proposed paper, the equations of the OpenCV GMM algorithm are optimized in such a way that a lightweight and low power implementation of the algorithm is obtained. The reported performances are also the result of the use of state of the art truncated binary multipliers and ROM compression techniques for the implementation of the non-linear functions. The first circuit has commercial FPGA devices as a target and provides speed and logic resource occupation that overcome previously proposed implementations. The second circuit is oriented to an ASIC (UMC-90nm) standard cell implementation. Both implementations are able to process more than 60 frames per second in 1080p format, a frame rate compatible with HD television.