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Design for Manufacturability through Design-Process Integration VII
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Volume Details

Volume Number: 8684
Date Published: 18 April 2013

Table of Contents
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Front Matter: Volume 8684
Author(s): Proceedings of SPIE
Design for manufacturability: a fabless perspective
Author(s): Jason P. Cain
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Diffraction pattern based optimization of lithographic targets for improved printability
Author(s): Shayak Banerjee; Kanak B. Agarwal
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Self-aligned double patterning friendly configuration for standard cell library considering placement impact
Author(s): Jhih-Rong Gao; Bei Yu; Ru Huang; David Z. Pan
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Evaluation of cost-driven triple patterning lithography decomposition
Author(s): Haitong Tian; Hongbo Zhang; Qiang Ma; Martin D. F. Wong
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Self-aligned double patterning compliant routing with in-design physical verification flow
Author(s): Jhih-Rong Gao; Harshdeep Jawandha; Prasad Atkar; Atul Walimbe; Bikram Baidya; Olivier Rizzo; David Z. Pan
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Pattern matching for identifying and resolving non-decomposition-friendly designs for double patterning technology (DPT)
Author(s): Lynn T. -N. Wang; Vito Dai; Luigi Capodieci
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Detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints
Author(s): Fumiharu Nakajima; Chikaaki Kodama; Hirotaka Ichikawa; Koichi Nakayama; Shigeki Nojima; Toshiya Kotani; Shoji Mimotogi; Shinji Miyamoto
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Pioneering an on-the-fly simulation technique for the detection of layout-dependent effects during IC design phase
Author(s): Amr M. S. Tossen; Ahmed Ramadan; Rami Fathy Salem
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Rethinking ASIC design with next generation lithography and process integration
Author(s): Kaushik Vaidyanathan; Renzhi Liu; Lars Liebmann; Kafai Lai; Andrzej Strojwas; Larry Pileggi
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Enhanced spacer-is-dielectric (sid) decomposition flow with model-based verification
Author(s): Yuelin Du; Hua Song; James Shiely; Martin D. F. Wong
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Mask strategy and layout decomposition for self-aligned quadruple patterning
Author(s): Weiling Kang; Chen Feng; Yijian Chen
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Process characteristics and layout decomposition of self-aligned sextuple patterning
Author(s): Weiling Kang; Yijian Chen
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Triple patterning lithography (TPL) layout decomposition using end-cutting
Author(s): Bei Yu; Jhih-Rong Gao; David Z. Pan
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Process window analysis of algorithmic assist feature placement options at the 2X nm node DRAM
Author(s): Jinhyuck Jeon; Shinyoung Kim; Jookyoung Song; Chanha Park; Hyunjo Yang; Donggyu Yim; Brian Ward; Yunqiang Zhang; Kevin Hooker; Munhoe Do; Jung-Hoe Choi; Stephen Jang
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Compact modeling of fin-width roughness induced FinFET device variability using the perturbation method
Author(s): Qi Cheng; Weiling Kang; Yijian Chen
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Understanding device impact of line edge/width roughness in frequency domain
Author(s): Peng Xie; He Ren; Aneesh Nainani; Huixiong Dai; Chris Bencher; Chris Ngai
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SRAM circuit performance in the presence of process variability of self-aligned multiple patterning
Author(s): Wei Xiao; Qi Cheng; Yijian Chen
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Post-routing back-end-of-line layout optimization for improved time-dependent dielectric breakdown reliability
Author(s): Tuck-Boon Chan; Andrew B. Kahng
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Double patterning: solutions in parasitic extraction
Author(s): Dusan Petranovic; James Falbo; Nur Kurt-Karsilayan
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Model based hint for litho hotspot fixing beyond 20nm node
Author(s): Jae-Hyun Kang; Byung-Moo Kim; Naya Ha; Hung bok Choi ; Kee sup Kim ; Sarah Mohamed; Kareem Madkour; Wael ElManhawy; Evan Lee; Jean-Marie Brunet; Joe Kwan
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A novel algorithm for automatic arrays detection in a layout
Author(s): Marwah Shafee; Jea-Woo Park; Ara Aslyan; Andres Torres; Kareem Madkour; Wael ElManhawy
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An automated resource management system to improve production tapeout turn-around time
Author(s): Eric Guo; Qingwei Liu; Sherry Zhu; Jason Wu; Jenny Tsai; Junwei Lu; Mark C. Simmons
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A novel methodology for building robust design rules by using design based metrology (DBM)
Author(s): Myeongdong Lee; Seiryung Choi; Jinwoo Choi; Jeahyun Kim; Hyunju Sung; Hyunyoung Yeo; Myoungseob Shim; Gyoyoung Jin; Eunseung Chung; Yonghan Roh
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