This PDF file contains the front matter associated with SPIE Proceedings Volume 8328, including the Title Page, Copyright information, Table of Contents, and the Conference Committee listing.

Advances in patterning techniques have enabled the extension of immersion lithography from 65/45nm through 14/10nm device technologies. A key to this increase in patterning capability has been innovation in the subsequent dry plasma etch processing steps. Multiple exposure techniques such as litho-etch-litho-etch, sidewall image transfer, line/cut mask and self-aligned structures have been implemented to solution required device scaling. Advances in dry plasma etch process control, across wafer uniformity and etch selectivity to both masking materials and have enabled adoption of vertical devices and thin film scaling for increased device performance at a given pitch. Plasma etch processes such as trilayer etches, aggressive CD shrink techniques, and the extension of resist trim processes have increased the attainable device dimensions at a given imaging capability. Precise control of the plasma etch parameters affecting across design variation, defectivity, profile stability within wafer, within lot, and across tools have been successfully implemented to provide manufacturable patterning technology solutions. IBM has addressed these patterning challenges through an integrated Total Patterning Solutions team to provide seamless and synergistic patterning processes to device and integration internal customers. This paper will discuss these challenges and the innovative plasma etch solutions pioneered by IBM and our alliance partners.

For the past 30 years, plasma etching technology has led in the efforts to shrink the pattern size of ultralarge-scale integrated (ULSI) devices. However, inherent problems in the plasma processes, such as charge buildup and UV photon radiation, limit the etching performance for nanoscale devices. To overcome these problems and fabricate sub-10-nm devices in practice, neutral-beam etching has been proposed. In this paper, we introduce the ultimate etching processes using neutral-beam sources and discuss the fusion of top-down and bottom-up processing for future nanoscale devices. Neutral beams can perform atomically damage-free etching and surface modification of inorganic and organic materials. This technique is a promising candidate for the practical fabrication technology for future nano-devices.

The root causes of issues in state-of-the-arts resist mask are low plasma tolerance in etch and resolution limit in lithography. This paper introduces patterning enhancement techniques (PETs) by reactive ion etch (RIE) that solve the above root causes. Plasma tolerance of resist is determined by the chemical structure of resin. We investigated a hybrid direct current (DC) / radio frequency (RF) RIE to enhance the plasma tolerance with several gas chemistries. The DC/RF hybrid RIE is a capacitive coupled plasma etcher with a superimposed DC voltage, which generates a ballistic electron beam. We clarified the mechanism of resist modification, which resulted in higher plasma tolerance^[1]. By applying an appropriate gas to DC superimposed (DCS) plasma, etch resistance and line width roughness (LWR) of resist were improved. On the other hand, RIE can patch resist mask. RIE does not only etch but also deposits polymer onto the sidewall with sedimentary type gases. In order to put the deposition technique by RIE in practical use, it is very important to select an appropriate gas chemistry, which can shrink CD and etch BARC. By applying this new technique, we successfully fabricated a 35-nm hole pattern with a minimum CD variation.

Self-organizing block copolymer thin films hold promise as a photolithography enhancement material for the 22-nm microelectronics technology generation and beyond, primarily because of their ability to form highly uniform patterns at the relevant nanometer-scale dimensions. Importantly, the materials are chemically similar to photoresists and can be implemented in synergy with photolithography. Beyond the challenges of achieving sufficient control of self-assembled pattern defectivity and feature roughness, block copolymer-based patterning requires creation of robust processes for transferring the polymer patterns into underlying electronic materials. Here, we describe research efforts in hardening block copolymer resist patterns using inorganic materials and high aspect ratio plasma etch transfer of self-assembled patterns to silicon using fluorine-based etch chemistries.

CMOS device patterning for aggressively scaled pitches (smaller than 80nm pitch) faces many challenges. Maybe one of the most crucial issues during device formation is the pattern transfer from a soft mask (carbon based) material into a hard mask material. A very characteristic phenomenon is that mechanical failure of the soft material may be observed. While this was observed first for patterning below 80nm pitch, it becomes increasingly important for even smaller pitches (≤ 40 nm). Further process optimization by various pre- and post-treatments has enabled robust pattern transfer down to 40nm pitch. A systematic study of the parameters impacting this phenomenon will be shown. Other challenges for patterning devices include profile control and material loss during gate stack patterning and spacer formation. Lastly, initial patterning experiments at an even more aggressive pitch show that the mechanical failure previously observed for larger pitches once again becomes an increasingly important issue to consider.

The challenges facing back-end-of-line (BEOL) etch as technology nodes progress are becoming increasingly difficult as the challenges due to shrinking dimensions are compounded by the challenges from new materials integration. Materials 100nm, new interactions of the materials with this critical dimension need to be considered. Both single and multipatterning schemes are considered, with some of the new challenges due to the multi-patterning schemes being highlighted. The need for a trench-first-via-last patterning scheme will also be reviewed in the context of advanced patterning nodes where M_x-to-V_x-1 spacing, via chamfering, and metal fill compatibility are key concerns. In addition, for trench double patterning, there is increased focus on the same-color tip-to-tip and tip-to-side rules, requiring etch to focus on CD control capabilities not only for the line CD but also for the line end, and line ends have always been a key challenge for k ≤ 2.55 etching, where metallization is most sensitive to dielectric damage structural effects. This paper will review several different patterning approaches and analyze the etch challenges as a function of dimensions, materials, or a combination of both.

Since more than 30 years, CW plasmas have been used in the microelectronics industry to pattern complex stacks of materials involved in Integrated Circuit technologies. Even if miniaturization challenges have been successfully addressed thanks to plasma patterning technologies, several fundamental limitations of the plasmas remain and are limiting our ability to shrink further the device dimensions. In this work, we analyze the capabilities of synchronized pulsed ICP technologies and their potential benefits for front end etch process performance. The impact of duty cycle and frequency on the ion energy distribution function and plasma chemistry is analyzed. Our results show that decreasing the duty cycle in ICP plasmas generates less fragmentation of the feed gas stock molecules compared to CW plasmas, leading in final to a decrease of the radical density in the plasma. On a process point of view, we have studied the etching of ultra-thin layers (SiO₂, HfO₂,SiN spacer) involved in front end processes and investigated what synchronized pulsed plasmas could bring to substrate damage and selectivity issues.

In recent years, NAND flash technology node has shrunk below to 1x nm patterning with significant progresses of double patterning technology (DPT) and spacer patterning technology (SPT). Plasma etching processes involved in the fabrication of advanced NAND flash device become increasingly challenging. As critical dimensions decrease, controlling of micro-loading and pattern wiggling such as line edge roughness (LER) and line width roughness (LWR) has become key issues. In order to define the fine pattern, plasma etch process regime has been changed to lower pressure and to higher plasma density below sub 40 nm. However, below 20 nm, it seems that control of pressure and plasma density is not enough. In an effort to overcome these huddles, pulsing plasma etch technology has been evaluated for 1x nm node. By using pulsing plasma we have obtained the improvement of etch selectivity and reduction of poly hard mask loss. In this study, we have found that pulse applied etching as well as film stack optimization is remarkably effective to reduce micro-loading and pattern wiggling.

With the decrease of semiconductor device dimensions, line width roughness (LWR) becomes a challenging parameter that needs to be controlled below 2nm in order to ensure good electrical performances of CMOS devices of the future technological nodes. One issue is the significant LWR of the photoresist patterns printed by 193nm lithography that is known to be partially transferred into the gate stack during the subsequent plasma etching steps. This issue could be partially resolved by applying plasma pre treatment on photoresist before plasma transfer. Another issue is linked to the noise level of the metrology tool, that causes a non negligible bias from true LWR values. Recently we proposed an experimental protocol combining CD-SEM measurements and Power Spectral Density (PSD) fitting method for an accurate estimation of the CDSEM noise level and extraction of unbiased LWR. In this article, we use the developed CDSEM protocol to extract roughness parameters (true LWR, correlation length, fractal exponent) of dense and isolated photoresist patterns exposed to various plasma treatments (HBr, H2, He, Ar), and also to follow the evolution of the LWR during the subsequent plasma etching steps involved in gate patterning. We show that the resist LWR is less improved in isolated than in dense lines with HBr plasma treatment because of carbon species redeposition more important on isolated resist pattern sidewalls. Plasmas such as H₂ that limit carbon redeposition are more efficient to decrease significantly resist LWR in both dense and isolated lines. In addition we show that all frequency roughness components are not equally transferred during gate patterning, and more particularly that the high frequency roughness components are lost.

Plasma-induced damage to low-k dielectric materials can be quantified by separation of the effects of charged-particle bombardment, photon bombardment, and gas-radical flux. For ion and photon bombardment, the spatial location and extent of the damage can be determined. Damage effects from radical flux will be shown to be small. Both SiCOH and photo-programmable low-k (PPLK) dielectrics will be discussed.

Photoresist strip has traditionally been a low technology process step, but is becoming increasingly more complex with the migration to ultra-shallow junctions, 3D structures, double patterning, and high-mobility channels. At junction depths of a few tens of nanometers, surface effects become increasingly important. Small changes to surface conditions can affect junction resistivity, junction depth, and dopant activation. Advanced high-resolution chemically amplified resist can be problematic when used as an implant mask. Ion beam induced chain scission and photoacid generation can lead to thermal instabilities during the resist strip process. Multilevel resist structures can be difficult to remove and rework and high aspect ratio 3D structures can require near infinite selectivity during the strip processes. This paper will summarize the issues and offer options for solutions.

We have investigated a H2 plasma smoothing process that improves the Line-Width-Roughness (LWR) and Line-Edge- Roughness (LER) of the EUV PR at 30 nm half pitch. This process reduces the LWR from ~5.8 to ~3.7 nm, a ~30% improvement. The main responsible for improving the LER/LWR under H₂ plasma seems to be the vacuum ultraviolet light (VUV) below 120 nm together with the low energy hydrogen ions and radicals. The Fourier transform infrared (FTIR), X-ray photoelectron spectroscopy (XPS) and liquid proton nuclear magnetic resonance (NMR) analyses suggest a depletion of oxygen containing groups and reduction of the aromatic groups in the PR. XPS revealed that the PR surface is rapidly modified by the H₂ plasma compared with the bulk (FTIR). Thus a cross-linked top surface is created which seems to be the limiting step for further LER/LWR improvement. The main challenge for dry etching is the EUV PR height which after lithography exposure and plasma smoothing, is less than 40 nm, provoking a low process window for subsequent etching steps. One strategy to open the process window is to encapsulate the PR with a more resistant material without destroying the lithography pattern. For this purpose a process was developed where 5-7nm of SiO₂-like layer was deposited on top of the PR at low temperature (50 degrees Celsius). The main advantage of this deposited layer is that it is thicker on the top of the lines than in between them.

The best strategy to transfer nanopatterns formed from the self assembly of PS/PMMA bloc copolymers into a silicon substrate is investigated. We show that a hard mask patterning strategy combined with a plasma cure treatment of the PS mask are necessary to reproduce the PS mask pattern into the silicon with a good critical dimension control. In addition, typical silicon etching plasma condition must be revisited to allow the etching of sub-20 nm holes. These results indicate that block copolymer can be readily used as etching masks for advanced CMOS technology.

This paper introduces a new technique utilizing a direct current superimposed (DCS) capacitively-coupled plasma (CCP) to enhance the etch selectivity to EUV resist with decreasing line width roughness (LWR). This new technique includes chemical and e-beam curing effects. DCS CCP generates ballistic electrons, which reform the chemical structure of photoresist. This surface modification hardens the photoresist (PR), and enhances the etch selectivity. The PR-hardening technique also improves the tolerance towards stress by polymer. Hence, a polymer becomes applicable to protect photoresist, and the etch selectivity increases even more. As a result, this cure can be processed without consuming the thickness of EUV resist. The mechanism of EUV resist cure is discussed based on the surface analysis. In addition to the basic physics of PR-hardening, this paper shows the benchmark results between DCS CCP and the conventional curing techniques by RIE, such as HBr cure and H₂ cure. Several new chemistries were applied to DCS CCP. In consequence, the PR-hardening by DCS CCP achieved a 33% reduction in LWR at pre-etch treatment, and a 30% reduction during under layer etch simultaneously maintaining enough thickness of EUV resist.

Self-aligned triple patterning (SATP) technique offers both improved resolution and quasi-2D design flexibility for scaling integrated circuits down to sub-15nm half pitch. By implementation of active layout decomposition/synthesis using mandrel and spacer engineering, SATP process represents a prospective trend that not only drives up the feature density, but also breaks the 1-D gridded limitations posed to future device design. In this paper, we shall present the research progress made in optimizing SATP process to improve its lithographic performance. To solve the previously reported difficulties in etching small mandrels and removing sacrificial spacers, new materials are tested and a promising scheme (using oxide as the mandrel and poly/amorphous Si as the sacrificial spacer) is identified. In the new process, a diluted HF process is applied to shrink the mandrel (oxide) line CD and a highly selective dry etch (which does not attack the mandrel and structural spacer) is developed to strip the sacrificial Si spacers, resulting in significantly improved process performance. We also address the issue of reducing SATP process complexity by exploring the feasibility of a 2-mask concept for specific types of layout.

The optimized dry development condition of low-k etcher obtained before is transferred to and optimized in DPSII metal etcher in this study to avoid resist pillar collapse, etch residual magnification, process continuity and tool simplicity. Three key process parameters of oxygen flow rate, bottom power and e-chuck temperature are studied for vertical pillars with various pattern densities. HSQ pillar patterning is transferred from diluted Fox-12 to commercialized XR1541-002 where the film thickness and patterned CD are matched. LTN hard mask (HM) of 100 nm thick above RRAM film stack is deposited for reducing proximity effect of XR1541-002 and improving etch resistance. Experimental results are summarized below. Highest AR of ~3.9 for HSQ/AR3 BLR semi-dense L/S=1/3 pillar with vertical profile is obtained with optimized dry develop condition of O2, N2, flow rates, chamber pressure and temperature, top and bottom power of 8, 5, sccm, 3 mTorr, 80oC, 200 and 100 watts respectively. AR is lower for looser pattern density. Oxygen flow rate and bottom power are the most critical process parameters for obtaining high AR BLR pillar and most vertical profile of pillar, just like the case of low-k etcher. E-chuck temperature is critical in profile control. Etch residual is magnified to broaden LTN pillar CD and degrade CD uniformity (CDU) if its etch process is not immediately continued after dry development process.

Utilizing thin photoresist layers for successful pattern transfer has gained acceptance as the lithography process of record, primarily due to the incorporation of silicon-containing hardmask (HM) layers for added etching resistance. Our work includes understanding the impact of HfO₂ and ZrO₂ nanocrystal additives incorporated into spin-on HM materials. The goal is to quantify both etch selectivity and the improvements in the lithography process windows with the addition of HfO₂ nanocrystals into various types of polymers. Conventional 193-nm photoresists and spin-on carbon materials were selected as references for etch selectivity calculations. Results indicate there are process window advantages with improvements in the depth of focus (DOF) and overall pattern collapse margins. In addition, the ability to quantify line width roughness (LWR) as a function of resolution has been accomplished for these HM materials, and results show low levels of LWR are achievable. Overall lithography process margins are positive for DOF, exposure latitude (EL), LWR, and pattern collapse with the incorporation of HfO₂-enhanced HM coatings for etch protection.

We investigated removal of chemically amplified negative-tone i-line resist SU-8 using hydrogen radicals, which was generated by the catalytic decomposition of H2/N2 mixed gas (H2:N2 = 10:90vol.%) using tungsten hot-wire catalyzer. SU-8 with exposure dose from 7 (Dg¹⁰⁰×0.5) to 280mJ/cm² (Dg¹⁰⁰×20) were removed by hydrogen radicals without a residual layer. When the distance between the catalyzer and the substrate was 100mm, the catalyzer temperature was 2400°C, and the initial substrate temperature was 50°C, removal rate of SU-8 was 0.17μm/min independent of exposure dose to the SU-8. Finally, we obtained high removal rate for SU-8 (exposure dose = 14mJ/cm² (Dg¹⁰⁰)) of approximately 4μm/min when the distance between the catalyzer and the substrate was 20mm, the catalyzer temperature was 2400°C, and the initial substrate temperature was 165°C.

We developed Fluor-based RIE processes to fabricate nanoimprint template in silicon and to transfer patterns from the imprint resist to the silicon substrate. The etched silicon patterns have slightly tapered and smooth sidewalls. The sidewall angle can be controlled between 85° and 90° by varying the ratio of the used gas. The dimension of the etched structures is identical with the patterns in the resist. We demonstrated line structures in silicon substrate down to 50 nm. The etching rate is over 100 nm per minute and the maximal achieved aspect ratio is more than 10.

Directed self-assembly (DSA) has shown the potential to replace traditional resist patterns and provide a lower cost alternative for sub-20-nm patterns. One of the possible roadblocks for DSA implementation is the ability to etch the polymers to produce quality masks for subsequent etch processes. We have studied the effects of RF frequency and etch chemistry for dry developing DSA patterns. The results of the study showed a capacitively-coupled plasma (CCP) reactor with very high frequency (VHF) had superior pattern development after the block co-polymer (BCP) etch. The VHF CCP demonstrated minimal BCP height loss and line edge roughness (LER)/line width roughness (LWR). The advantage of CCP over ICP is the low dissociation so the etch rate of BCP is maintained low enough for process control. Additionally, the advantage of VHF is the low electron energy with a tight ion energy distribution that enables removal of the polymethyl methacrylate (PMMA) with good selectivity to polystyrene (PS) and minimal LER/LWR. Etch chemistries were evaluated on the VHF CCP to determine ability to treat the BCPs to increase etch resistance and feature resolution. The right combination of RF source frequencies and etch chemistry can help overcome the challenges of using DSA patterns to create good etch results.

As lithographic resolution has increased to meet the demand for smaller devices it has been necessary to use extremely thin photoresist films to mitigate aspect ratio related resist feature collapse during development. Even with high etchdurability photoresists, usable photoresist thickness limits etch depth, and it is becoming increasingly difficult to transfer the pattern directly from the photoresist to the substrate. As feature sizes have diminished the use of multilayer etch stacks has been increasingly investigated to further increase aspect ratio. Typically, a thick layer of amorphous carbon is deposited by chemical vapor deposition, and then coated with thin silicon and resist layers. To improve manufacturability it would be beneficial to use spin-on-carbon in the bottom layer. Here we introduce a fullerene based spin-on carbon with high etch-durability. Sub 50 nm features with aspect ratios in excess of 15:1 have been produced in silicon using ICP etching.

The line edge roughness transfer from the resist to the underlying substrate via plasma etching is studied with a 3d modeling framework. The framework includes the generation of 3d rough resist lines with predetermined roughness parameters [root mean square roughness (σ), correlation length (ξ), and roughness exponent]. The pattern transfer of the generated 3d lines to the substrate is captured by an abstractive geometric model: Plasma etching is considered anisotropic and the shadowing of the incident ions by the protrusions of the initial resist sidewall determines the roughness of the substrate sidewall. Shadowing is enough to induce the striations and the reduction of σ at the substrate sidewall. The effect of the sidewall roughness (σ and ξ) and shape (thickness and sidewall slope) of the initial resist line as well as the etching selectivity and etching depth on a) σ and b) the slope of the substrate sidewall is investigated. A linear relation between σ of the substrate and σ of the initial resist sidewalls is found, consistently with pertinent experimental studies. It is found that the reduction of σ is favored by a low correlation length of the initial resist sidewall and by thicker resist films. The decrease of σ of the initial resist sidewall, the increase of the etching selectivity, and the increase of the initial resist thickness favors a slope of the substrate sidewall closer to 90°. The slope of the initial resist sidewall affects the slope of the substrate sidewall only for low values of σ.