Share Email Print
cover

Proceedings of SPIE Volume 7275

Design for Manufacturability through Design-Process Integration III
Format Member Price Non-Member Price
Softcover $105.00 * $105.00 *

*Available as a photocopy reprint only. Allow two weeks reprinting time plus standard delivery time. No discounts or returns apply.


Volume Details

Volume Number: 7275
Date Published: 16 March 2009
Softcover: 55 papers (528) pages
ISBN: 9780819475282

Table of Contents
show all abstracts | hide all abstracts
Front Matter: Volume 7275
Author(s): Proceedings of SPIE
Hierarchical modeling of spatial variability with a 45nm example
Author(s): Kun Qian; Borivoje Nikolić; Costas J. Spanos
Show Abstract
Tiny footprint programmable electrical defocus monitors
Author(s): Wojtek Poppe; Patrick Au; Darshana Jayasuriya; Juliet Rubinstein; Andrew R. Neureuther
Show Abstract
The nebulous hotspot and algorithm variability
Author(s): Alfred K. K. Wong; Edmund Y. Lam
Show Abstract
Simplify to survive: prescriptive layouts ensure profitable scaling to 32nm and beyond
Author(s): Lars Liebmann; Larry Pileggi; Jason Hibbeler; Vyacheslav Rovner; Tejas Jhaveri; Greg Northrop
Show Abstract
Illustration of illumination effects on proximity, focus spillover, and design rules
Author(s): Lynn T.-N. Wang; Anthony Yeh; Lilly Kem; Andrew R. Neureuther
Show Abstract
2D design rule and layout analysis using novel large-area first-principles-based simulation flow incorporating lithographic and stress effects
Author(s): Steven L. Prins; James Blatchford; Oluwamuyiwa Olubuyide; Deborah Riley; Simon Chang; Qi-Zhong Hong; T. S. Kim; Ricardo Borges; Li Lin
Show Abstract
Exploration of complex metal 2D design rules using inverse lithography
Author(s): Simon Chang; James Blatchford; Steve Prins; Scott Jessen; Thuc Dam; Guangming Xiao; Linyong Pang; Bob Gleason
Show Abstract
Compensating non-optical effects using electrically driven optical proximity correction
Author(s): Shayak Banerjee; Kanak B. Agarwal; James A. Culp; Praveen Elakkumanan; Lars W. Liebmann; Michael Orshansky
Show Abstract
Impact of lithography variability on analog circuit behavior
Author(s): Christopher Progler; Bhaskar Banerjee; M. F. Haniff; T. Mahzabeen
Show Abstract
Design specific variation in pattern transfer by via/contact etch process: full-chip analysis
Author(s): Valeriy Sukharev; Ara Markosian; Armen Kteyan; Levon Manukyan; Nikolay Khachatryan; Jun-Ho Choy; Hasmik Lazaryan; Henrik Hovsepyan; Seiji Onoue; Takuo Kikuchi; Tetsuya Kamigaki
Show Abstract
Interval-value based circuit simulation for statistical circuit design
Author(s): Qian Ying Tang; Costas J. Spanos
Show Abstract
Variations in timing and leakage power of 45nm library cells due to lithography and stress effects
Author(s): Kayvan Sadra; Mark Terry; Arjun Rajagopal; Robert A. Soper; Donald Kolarik; Tom Aton; Brian Hornung; Rajesh Khamankar; Philippe Hurat; Bala Kasthuri; Yajun Ran; Nishath Verghese
Show Abstract
Parameter-specific electronic measurement and analysis of sources of variation using ring oscillators
Author(s): Lynn T.-N. Wang; Liang-Teck Pang; Andrew R. Neureuther; Borivoje Nikolić
Show Abstract
Manufacturing system based on tolerance deduced from design intention
Author(s): Suigen Kyoh; Shimon Maeda; Sachiko Kobayashi; Soichi Inoue
Show Abstract
Directional 2D functions as models for fast layout pattern transfer verification
Author(s): J. Andres Torres; Mark Hofmann; Oberdan Otto
Show Abstract
Score-based fixing guidance generation with accurate hot-spot detection method
Author(s): Yong-Hee Park; Dong-Hyun Kim; Jung-Hoe Choi; Ji-Suk Hong; Chul-Hong Park; Sang-Hoon Lee; Moon-Hyun Yoo; Jun-Dong Cho
Show Abstract
Algorithm for determining printability and colouring of a target layout for double patterning
Author(s): Justin Ghan; Apo Sezginer
Show Abstract
Verification of extraction repeating pattern efficiency from many actual device data
Author(s): Masahiro Shoji; Tadao Inoue; Masaki Yamabe
Show Abstract
Design ranking and analysis methodology for standard cells and full chip physical optimization
Author(s): Yosi Vaserman; Eitan Shauly
Show Abstract
Practical implementation of via and wire optimization at the SoC level
Author(s): Chi-Min Yuan; Guy Assad; Bob Jarvis; Marc Olivares; Lionel Riviere Cazaux; Puneet Sharma; Jayathi Subramanian; Matt Thompson; Kevin Wu
Show Abstract
Test structures for 40 nm design rule evaluation
Author(s): Jonathan Ho; Yan Wang; Benjamin Lin
Show Abstract
Computational requirements for OPC
Author(s): Chris Spence; Scott Goad
Show Abstract
Hotspot management for spacer patterning technology with die-to-database wafer inspection system
Author(s): Yoshinori Hagio; Ichirota Nagahama; Yasuo Matsuoka; Hidefumi Mukai; Koji Hashimoto
Show Abstract
Source-mask selection using computational lithography incorporating physical resist models
Author(s): Sanjay Kapasi; Stewart Robertson; John Biafore; Mark D. Smith
Show Abstract
Application of pixel-based mask optimization technique for high transmission attenuated PSM
Author(s): Kyohei Sakajiri; Alexander Trichkov; Yuri Granik; Eric Hendrickx; Geert Vandenberghe; Monica Kempsell; Germain Fenger; Klaus Boehm; Thomas Scheruebl
Show Abstract
Transistor layout configuration effect on actual gate LER
Author(s): Guy Ayal; Eitan Shauly; Israel Rotshtein; Ovadya Menadeva; Amit Siany; Ram Peltinov; Yosi Shacham-Diamand
Show Abstract
Layout electrical cooptimization for increased tolerance to process variations
Author(s): Lionel Riviere-Cazaux; Philippe Hurat; Bala Kasthuri; Larry Layton; Nishath Verghese
Show Abstract
The PIXBAR OPC for contact-hole pattern in sub-70-nm generation
Author(s): KunYuan Chen; ChunCheng Liao; ShuHao Chen; Todd Wey; Phoeby Cheng; Pinjan Chou; Jochen Schacht; Dyiann Chou; Srividya Jayaram
Show Abstract
Computational technology scaling from 32 nm to 28 and 22 nm through systematic layout printability verification
Author(s): Jason P. Cain; Luigi Capodieci
Show Abstract
Variability aware interconnect timing models for double patterning
Author(s): Eric Y. Chin; Andrew R. Neureuther
Show Abstract
Design-overlay interactions in metal double patterning
Author(s): Rani S. Ghaida; Puneet Gupta
Show Abstract
Detecting context sensitive hot spots in standard cell libraries
Author(s): Jen-Yi Wuu; Fedor G. Pikus; Andres Torres; Malgorzata Marek-Sadowska
Show Abstract
Clustering and pattern matching for an automatic hotspot classification and detection system
Author(s): Justin Ghan; Ning Ma; Sandipan Mishra; Costas Spanos; Kameshwar Poolla; Norma Rodriguez; Luigi Capodieci
Show Abstract
Developing DRC plus rules through 2D pattern extraction and clustering techniques
Author(s): Vito Dai; Luigi Capodieci; Jie Yang; Norma Rodriguez
Show Abstract
Electrical impact of line-edge roughness on sub-45nm node standard cell
Author(s): Yongchan Ban; Savithri Sundareswaran; Rajendran Panda; David Z. Pan
Show Abstract
Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulation
Author(s): Eitan Shauly; Andres Torres; Loran Friedrich; Moran Cohen-Yasour; Ovadya Menadeva; Fedor Pikus
Show Abstract
Circuit-topology driven OPC for increased performance/yield ratio
Author(s): Edmund Pierzchala; Fedor Pikus; J. Andres Torres
Show Abstract
Systematic study of the impact of curved active and poly contours on transistor performance
Author(s): Victor Moroz; Munkang Choi; Xi-Wei Lin
Show Abstract
Lithography aware statistical context characterization of 40nm logic cells
Author(s): Mark E. Rubin; Naohiro Kobayashi; Toshiaki Yanagihara
Show Abstract
Implementing self-aligned double patterning on non-gridded design layouts
Author(s): Huixiong Dai; Jason Sweis; Chris Bencher; Yongmei Chen; Jen Shu; Xumou Xu; Chris Ngai; Judy Huckabay; Milind Weling
Show Abstract
High-precision contouring from SEM image in 32-nm lithography and beyond
Author(s): Hiroyuki Shindo; Akiyuki Sugiyama; Hitoshi Komuro; Yutaka Hojo; Ryoichi Matsuoka; John L. Sturtevant; Thuy Do; Ir Kusnadi; Germain Fenger; Peter De Bisschop; Jeroen Van de Kerkhove
Show Abstract
Uniformity-aware standard cell design with accurate shape control
Author(s): Hongbo Zhang; Martin D. F. Wong; Kai-Yuan Chao; Liang Deng; Soo-Han Choi
Show Abstract
Contour-based optical proximity correction
Author(s): Brian Zhou; Liang Zhu; Yingchun Zhang; Yili Gu; Xiaohui Kang
Show Abstract
Model-based adaptive fragmentation
Author(s): Daisy Liu; Cheng He Li; Xiao Hui Kang
Show Abstract
Process variation aware OPC modeling for leading edge technology nodes
Author(s): Qiaolin Zhang; Ebo Croffie; Yongfa Fan; Jianliang Li; Kevin Lucas; Brad Falch; Lawerence Melvin
Show Abstract
Large-scale double-patterning compliant layouts for DP engine and design rule development
Author(s): Christopher Cork; Kevin Lucas; John Hapli; Herve Raffard; Levi Barnes
Show Abstract
Statistical approach to design DRAM bitcell considering overlay errors
Author(s): Yu-Jin Pyo; Dae-Wook Kim; Jai-Kyun Park; Ji-Seong Doh; Hyun-Jae Kang; Ji-Suk Hong; Chul-Hong Park; Sang-Hoon Lee; Moon-Hyun Yoo
Show Abstract
Enhanced layout optimization of sub-45nm standard: memory cells and its effects
Author(s): Seung Weon Paek; Dae Hyun Jang; Joo Hyun Park; Naya Ha; Byung-Moo Kim; Hyo Sig Won; Kyu-Myung Choi; Kuang-Kuo Lin; Simon Klaver; Shobhit Malik; Michiel Oostindie; Frank Driessen
Show Abstract
Integration of mask and silicon metrology in DFM
Author(s): Ryoichi Matsuoka; Hiroaki Mito; Akiyuki Sugiyama; Yasutaka Toyoda
Show Abstract
Implementing a framework to generate a unified OPC database from different EDA vendors for 45nm and beyond
Author(s): Shady Abdel Abdelwahed; Mohamed Al-Iman; Rami Fathy; Nader Hindawy; Jochen Schacht; Regina Shen; Chia Wei Huang; Pei Ru Tsai; Te Hung Wu; Chuen Huei Yang
Show Abstract
Timing-aware metal fill for optimized timing impact and uniformity
Author(s): Usha Katakamsetty; Colin Hui; Li-Da Huang; Lannie Weng; Peter Wu
Show Abstract
Process variability band analysis for quantitative optimization of exposure conditions
Author(s): John L. Sturtevant; Srividya Jayaram; Le Hong
Show Abstract
Hotspot detection and design recommendation using silicon calibrated CMP model
Author(s): Colin Hui; Xian Bin Wang; Haigou Huang; Ushasree Katakamsetty; Laertis Economikos; Mohammed Fayaz; Stephen Greco; Xiang Hua; Subramanian Jayathi; Chi-Min Yuan; Song Li; Vikas Mehrotra; Kuang Han Chen; Tamba Gbondo-Tugbawa; Taber Smith
Show Abstract
Convergent automated chip level lithography checking and fixing at 45nm
Author(s): Valerio Perez; Shyue Fong Quek; Sky Yeo; Colin Hui; Kuang Kuo Lin; Walter Ng; Michel Cote; Bala Kasthuri; Philippe Hurat; Matt A. Thompson; Chi-Min Yuan; Puneet Sharma
Show Abstract
Modeling and simulation of transistor performance shift under pattern-dependent RTA process
Author(s): Yun Ye; Frank Liu; Yu Cao
Show Abstract

© SPIE. Terms of Use
Back to Top