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- Front Matter: Volume 7122
- Plenary Paper from Advanced Lithography 2008
- Invited Session
- Mask Materials for Optical Extensions
- Advanced Mask Processing
- Patterning Technologies and Tools
- DPL Implementation I
- DPL Implementation II
- RET and OPC/ORC I
- Advanced Cleaning
- Haze Contamination Control
- Wafer Plane Inspection
- Inspection
- Defect Repair
- RET and OPC/ORC II
- Simulation and Modeling I
- Simulation and Modeling II
- DFM
- EUV Mask Processing and Substrates
- EUV Mask Process Correction
- EUV Mask Inspection I
- EUV Mask Inspection II
- EUV Mask Repair
- Masks for Nano-Imprint Lithography
- Mask Business
- SEM CD Metrology
- Advanced CD Metrology
- Metrology for Placement and Optical Structure
- Poster Session: Mask Business
- Poster Session: Advanced Mask Patterning
- Poster Session: Advanced Mask Processing and Materials
- Poster Session: Metrology
- Poster Session: Inspection and Repair
- Poster Session: Contamination Control and Cleaning
- Poster Session: EUV Mask Processing and Substrates
- Poster Session: Nano-Imprint
- Poster Session: DFM
- Poster Session: Simulation and Modeling
- Poster Session: RET and OPC/ORC
Front Matter: Volume 7122
Front Matter: Volume 7122
Show abstract
This PDF file contains the front matter associated with SPIE
Proceedings Volume 7122, including the Title Page, Copyright
information, Table of Contents, Introduction (if any), and the
Conference Committee listing.
Plenary Paper from Advanced Lithography 2008
Lithography and design in partnership: a new roadmap
Andrew B. Kahng
Show abstract
We discuss the notion of a 'shared technology roadmap' between lithography and design from several perspectives. First,
we examine cultural gaps and other intrinsic barriers to a shared roadmap. Second, we discuss how lithography technology
can change the design technology roadmap. Third, we discuss how design technology can change the lithography
technology roadmap. We conclude with an example of the 'flavor' of technology roadmapping activity that can truly
bridge lithography and design.
Invited Session
Mask industry assessment: 2008
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Microelectronics industry leaders routinely name the cost and cycle time of mask technology and mask supply as top
critical issues. A survey was created with support from SEMATECH and administered by David Powell Consulting
to gather information about the mask industry as an objective assessment of its overall condition. The survey is
designed with the input of semiconductor company mask technologists, merchant mask suppliers, and industry
equipment makers. This year's assessment is the seventh in the current series of annual reports. With ongoing
industry support, the report can be used as a baseline to gain perspective on the technical and business status of the
mask and microelectronics industries. The report will continue to serve as a valuable reference to identify the
strengths and opportunities of the mask industry. The results will be used to guide future investments pertaining to
critical path issues. This year's survey is basically the same as the 2005 through 2007 surveys. Questions are
grouped into categories: General Business Profile Information, Data Processing, Yields and Yield Loss Mechanisms,
Delivery Times, Returns, and Services. Within each category is a multitude of questions that create a detailed profile
of both the business and technical status of the critical mask industry.
PMJ panel discussion overview on mask complexities, cost, and cycle time in 32-nm system LSI generation: conflict or concurrent?
Show abstract
This is a report on a panel discussion organized in Photomask Japan 2008, where the challenges about "Mask
Complexities, Cost, and Cycle Time in 32-nm System LSI Generation" were addressed to have a look over the possible
solutions from the standpoints of chipmaker, commercial mask shop, DA tool vendor and equipments makers. The
wrap-up is as follows: Mask complexities justify the mask cost, while the acceptable increase rate of 32nm-mask cost
significantly differs between mask suppliers or users side. The efficiency progress by new tools or DFM has driven their
cycle-time reductions. Mask complexities and cost will be crucial issues prior to cycle time, and there seems to be linear
correlation between them. Controlling complexity and cycle time requires developing a mix of advanced technologies,
and especially for cost reduction, shot prices in writers and processing rates in inspection tools have been improved
remarkably by tool makers. In addition, activities of consortium in Japan (Mask D2I) are expected to enhance the total
optimization of mask design, writing and inspection. The cycle-time reduction potentially drives the lowering of mask
cost, and, on the other, the pattern complexities and tighter mask specifications get in the way to 32nm generation as well
as the nano-economics and market challenges. There are still many difficult problems in mask manufacturing now, and
we are sure to go ahead to overcome a 32nm hurdle with the advances of technologies and collaborations by not only
technologies but also finance.
Mask Materials for Optical Extensions
Characterization of binary and attenuated phase shift mask blanks for 32nm mask fabrication
Show abstract
During the development of optical lithography extensions for 32nm, both binary and attenuated phase shift Reticle
Enhancement Technologies (RETs) were evaluated. The mask blank has a very strong influence on the minimum feature
size and critical dimension (CD) performance that can be achieved on the finished reticle and can have a significant
impact on the ultimate wafer lithographic performance. Development of a suitable high resolution binary mask making
process was particularly challenging. Standard chrome on glass (COG) binary blanks with 70 nm thick chrome films
were unable to support the required minimum feature size, linearity, and through pitch requirements. Two alternative
mask blank configurations were evaluated for use in building high resolution binary masks: a binary (BIN) mask blank
based on the standard attenuated PSM blank and an Opaque MoSi on Glass (OMOG) mask blank consisting of a newly-
developed opaque MoSi [1]. Data comparing the total process bias, minimum feature size, CD uniformity, linearity,
through pitch, etch loading effects, flatness, film stress, cleaning durability and radiation durability performance of the
different binary and attenuated PSM mask blanks are reported. The results show that the new OMOG binary blank offers
significant mask performance benefits relative to the other binary and attenuated PSM mask blanks. The new OMOG
blank was the opaque mask blank candidate most capable of meeting 32nm binary mask fabrication requirements..
Impact of the OMOG substrate on 32 nm mask OPC inspectability, defect sensitivity, and mask design rule restrictions
Show abstract
Aggressive optical proximity correction (OPC) has enabled the extension of advanced lithographic technologies to the
32nm node. The associated sub-resolution features, feature-feature spacings, and fragmented edges in the design data are
difficult to reproduce on masks and even more difficult to inspect. The patterns themselves must be differentiated from
defects for inspectability, while the ability to recognize small deviations must be maintained for sensitivity. This must be
done without restricting necessary OPC design features. The semi-transparent nature of industry-standard 6% attenuated
phase shift substrates introduces a host of problems relative to inspectable dimensions and subsequent defect
sensitivities. The result is a reduction in inspectability, defect sensitivity and the inability to inspect smaller critical
dimensions and OPCed features. The introduction of a binary-type attenuated phase shift film improves the ability to
inspect smaller critical dimensions and smaller OPC features without loss of inspectability and sensitivity extending the
capability of existing inspection hardware for 32nm ground rule masks. This paper introduces inspection characterization
results for this new film, opaque MoSi on glass (referred to as OMOG in this paper) and draws a correlation between the
film's transmission qualities and inspectability of 32nm OPC features. The paper will further show a correlation between
OPC feature size and defect sensitivity for 32nm ground rule designs. Aerial Image (AIMS) analysis will be used to
identify areas where the enhanced inspection capability can be leveraged to avoid unnecessary restrictions on OPC.
Evaluation of 32nm advanced immersion lithography pellicles
Show abstract
Advanced immersion lithography utilizes higher numerical aperture (NA) stepper lenses resulting in higher angles of
light illumination through photomasks. Transmission in conventional pellicles (830 nm thickness) is generally
maximized at 0 degree illumination and decreases significantly at the higher angles. Most pellicle suppliers have
developed thinner pellicle membranes (~280 nm) which allow considerably improved transmission of light at angles up
to 20 degrees. In addition, aluminum frames have been shortened, potentially allowing inspection closer to the inside of
the frame and reduced mask flatness distortion upon pellicle mount. Suppliers have also developed advanced adhesives
which reduce outgassing even beyond the low levels obtained with current 45 nm pellicles. In this paper, advanced
immersion pellicles from several suppliers are evaluated and compared with conventional 45 nm pellicles for the
following quality parameters: physical durability, foreign material, ease of demounting and glue removal, chemical
outgassing, mask flatness distortion and susceptibility to radiation damage. Improvements in mask inspection and
pellicle optical transmission at higher incident angles are also evaluated and are discussed.
Advanced Mask Processing
Road to a zero degree total temperature range post exposure bake process
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With tighter CD uniformity requirements, a tighter temperature control during a Post Exposure Bake (PEB) process for
photomask production becomes more and more important. CD non uniformities can be partially ascribed to deficiencies
of the measurement devices used for the process qualification of a PEB hotplate system. In this paper, a new routine is
proposed to overcome the deficiencies of the measurement devices used, so that further improvement of the hotplate
performance becomes possible. Using a 25 point sensor array, we finally achieved a bake performance of the hotplate
system described in terms of "real" total temperature range on the mask surface, of 0.4°C during temperature ramp-up
and below 0.1°C at steady state for a final mean temperature of 100°C. This is a first step in the right direction towards a
temperature range of zero for the bake process.
Study of second-generation Proximity Gap Suction Development System (PGSD-II) for mask fabrication
Show abstract
Development process for 3x nm node devices and beyond is becoming a great issue in mask
fabrication. The following items, such as uniformity, repeatability, loading effect and defect must be
improved. To evolve the development process, TEL, DNP Omron and Toshiba have been jointly
developed next generation equipment which is called "Second-generation PGSD (Gen.2)".
In this paper, PGSD Gen.2 concept is introduced and its performance is reported.
Process control of chrome dry etching by complete characterization of the RF power delivery
Show abstract
In order to fulfil the upcoming requirements for photomasks there is a need for improving the process stability
(reproducibility) of the unit processes in photomask fabrication. In order to understand and minimize the etch
contribution to the CD stability impedance sensors integrated into the capacitively coupled radio frequency (RF) circuit
(bias circuit) have shown a big potential.
The last step towards a full characterization of the RF properties is the integration of impedance sensors in the
inductively coupled RF circuit (source). This kind of sensor measures voltage, current and phase angle for the
fundamental (13.56 MHz) and higher harmonics (up to the 5th harmonic).
In this paper we are describing the integration of the Z-Scan sensors into the source RF matchbox and its impact on the
RF and CD characteristics of the mask etcher. The central point is the correlation of impedance data to CD data. We will
also compare the responses for bias and source impedance measurements.
Integrating Cr and MoSi etch for optimal photomask critical dimension uniformity and phase uniformity
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Two key parameters of attenuated phase shift masks are critical dimension uniformity (CDU) and phase uniformity.
This study examines the important role that plasma etch plays in determining these parameters. For optimal results, the
impact which Cr and MoSi etch have on uniformity must be understood not only individually, but also as a
complementary pair. A two-step MoSi etch was developed; the first step was tuned to have a higher etch bias at the edge
than at the center, while the second step had a very uniform etch bias. By controlling the fraction of the MoSi consumed
by each step, the MoSi etch was adapted to complement the Cr etch and thus optimize overall CDU and phase
uniformity.
Electric field-induced progressive CD degradation in reticles
Show abstract
Reticles have been found to be susceptible to damage by the Electric Field induced Migration of chrome (EFM) at field
levels >100x lower than those that cause ESD. The experimental quantification data are reviewed briefly and detailed
AFM imagery is presented illustrating the nature of the reticle degradation process. The characteristics of EFM and its
very low onset threshold have significant implications for the protection of advanced reticles so a new reticle handling
methodology is proposed which is designed to minimize the risk of field induced damage.
Don't kill canaries! Introducing a new test device to assess the electrostatic risk potential to photomasks
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Electrostatic protection is an issue for all masks, whether during mask production, shipping, storage, handling or
inspection and exposure. Up to now, only manual electrostatic field measurements, or expensive and elaborate analyses
with Canary reticles have given hints about the risks of pattern damage by ESD events.
A new test device is being introduced, which consists of electrostatic field sensors, integrated INSIDE a closed fused
quartz housing which has the outside dimensions of a 6 inch mask.
This device can be handled and used like a normal 6 inch reticle. It can be handled and processed while recording the
electrostatic charges on the chrome patterns created by friction or field induction just as a reticle would "see" during
normal processing.
Patterning Technologies and Tools
Damage mechanisms and process optimization for photomasks with sub-resolution assist features
Show abstract
Sub-Resolution Assist Features (SRAFs) are typically the smallest features on a photomask and amplify many of the
challenges in mask manufacturing. During the initial stages of process development, resist feature adhesion is the
dominate damage mechanism. Throughout mask fabrication, the influence of inherent material properties and wet
processing can eventually delaminate SRAFs. The various mechanisms that cause SRAF damage will be presented
systematically. Process optimization steps to address the failure mechanisms will be presented. Data illustrating the
improved process window for small features will be included.
New electron optics for mask writer EBM-7000 to challenge hp 32nm generation
Show abstract
Semiconductor scaling is expected to continue to hp32nm and beyond, accompanied by explosive data volume
expansion. Required minimum feature size at hp 32nm will be less than 50nm on the mask, according to ITRS2007(1).
EBM 7000 is a newly designed mask writer for the hp32 nm node with an improved electron optical column providing
the beam resolution (10 nm measured in situ) and beam current density (200 A/cm2) necessary for cost effective mask
production at hp32nm node. In this paper we report on column improvements, the in situ beam blur measurement
method and writing results from EBM 7000. Written patterns show dose margin (CD change [nm] / 1 % dose change) of
.94 nm /1 % dose for line/space arrays using chemically amplified resist PRL009 and our standard processing. Using a
simple model to relate the measured beam intensity distribution to the measured dose margin, we infer an effective total
blur of 30 nm, dominated by a contribution of 28 nm from the resist exposure and development process. Further
evidence of the dominance of the process contribution is the measured improvement in dose margin to .64 nm/% dose
obtained by modifying our standard process. Even larger process improvements will be needed for successful fabrication
of hp22nm masks.
E-beam exposure system using multi column cell (MCC) with CP for mask writing
Show abstract
In the Mask D2I project at ASET, the authors designed a novel electron beam exposure system using the concepts of
MCC (multi column cell), CP (character projection), and VSB (variable shaped beam) to improve the throughput of
electron beam exposure systems. They presented outlines of a proof-of-concept system of MCC, and have shown the
performances of VSB and CP in the system. They evaluated the impacts on beam position in one column cell caused by
deflections in another column cell. The impacts were found to be less than 0.1nm in presence of major deflections in the
neighboring column cell. Hence it was concluded that there was no noticeable impact on deflections cause by the
neighboring column cells in the MCC system.
Results obtained with the CHARPAN Engineering Tool and prospects of the ion Mask Exposure Tool (iMET)
Show abstract
Projection Mask-Less Patterning (PMLP) is based on many hundred thousands of ion beams working in parallel. A PMLP
proof-of-concept tool has been realized as part of the European project CHARPAN (Charged Particle Nanotech) and has
been presented at SPIE Photomask BACUS 2007. Using 10 keV protons, 16nm hp resolution has been demonstrated in non-
CAR materials (HSQ) with 25μC/cm2 exposure dose. The system is upgraded to a CHARPAN Engineering Tool (CHET)
with a laser-interferometer controlled vacuum stage and a CMOS based programmable Aperture Plate System (APS)
providing ca. 40,000 beams with < 20nm spot size. The engineering of an ion Mask Exposure Tool (iMET) for the 22nm hp
mask node has been started; main iMET features are discussed.
Effects of heated substrates on bimetallic thermal resist for lithography and grayscale photomask applications
Show abstract
Bimetallic thin-films of Bi/In act as negative thermal resists when laser exposure pulse (7mJ/sq. cm for 4 nsec)
converts the film into a transparent eutectic metallic oxide alloy. Resist transparency varies with exposed laser power,
changing from <0.1% (3.0 OD) unexposed to >60% (0.22 OD) exposed. This generates direct-write gray scale
photomasks, and adding a feedback system where the transparency is measured and adjusts the writing process to
account for local variations in the film, achieves >64 gray level control. These resists are also wavelength invariant,
operating from visible to EUV with a resolution >42nm after development using a diluted RCA-2 solution
(HCl:H2O2:H20 @ 1:1:48) with a gamma of 2-18. Longer duration exposures with lower instantaneous intensities result
in lower gammas, while shorter exposures with higher energies give higher gammas. One limitation on these resists is
that the exposure energy must be delivered in a single pulse. This limitation puts pulse energy requirements into the mJ
per pulse range: greater than desired for EUV exposure systems. Bimetallic thermal resists remain almost unaffected
during a sub-threshold exposure that does not reach the activation energy. It has been shown that the resist and substrate
can be heated below the threshold energy, to temperatures of at least 90°C, without creating any exposure of the resist.
In this research, Bi/In resists are heated through a range of substrate temperatures, measured for their optical exposure
requirements and gammas under these conditions, and used to determine if substrate heating can improve the film's
sensitivity.
DPL Implementation I
Revisiting the layout decomposition problem for double patterning lithography
Show abstract
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features
must be assigned opposite colors (corresponding to different exposures) if their spacing is less than the minimum
coloring spacing.5, 11, 14 However, there exist pattern configurations for which pattern features separated by
less than the minimum coloring spacing cannot be assigned different colors. In such cases, DPL requires that
a layout feature be split into two parts. We address this problem using a layout decomposition algorithm that
incorporates integer linear programming (ILP), phase conflict detection (PCD), and node-deletion bipartization
(NDB) methods. We evaluate our approach on both real-world and artificially generated testcases in 45nm
technology. Experimental results show that our proposed layout decomposition method effectively decomposes
given layouts to satisfy the key goals of minimized line-ends and maximized overlap margin. There are no design
rule violations in the final decomposed layout. While we have previously reported other facets of our research
on DPL pattern decomposition,6 the present paper differs from that work in the following key respects: (1)
instead of detecting conflict cycles and splitting nodes in conflict cycles to achieve graph bipartization,6 we split
all nodes of the conflict graph at all feasible dividing points and then formulate a problem of bipartization by
ILP, PCD8 and NDB9 methods; and (2) instead of reporting unresolvable conflict cycles, we report the number
of deleted conflict edges to more accurately capture the needed design changes in the experimental results.
Evaluation of Double Process Lithography (DPL) with bi-layer photo-resist process for contact layer-patterning
Show abstract
Double Process Lithography (DPL) has been widely accepted as a viable printing technique for
critical layers at 45nm nodes and below. In addition, DPL technique also allows us to use available process
tool-sets with less capability to develop the next node CMOS devices in early research and development
stages with additional photo-masks. One practical issue of applying DPL technique is the process crosstalk,
which is the impact of the existing etched patterns after the 1st process to the overall lithography
performance during the 2nd printing process. In this paper, we evaluated the DPL process for contact holetype
patterning with a 193nm silicon-containing bi-layer photo-resist. We explained the bi-layer photoresist
process flow and its low process cross-talk characteristics when applied in our DPL process. We also
discussed the challenges of printing small contacts in the DPL process. The preliminary experiment results
indicated that silicon-containing photo-resist process is a good candidate for DPL process in the contact
hole-type of patterns, and it has good characteristics of low process cross-talk. The flexibility of the drydevelop
process in bi-layer resist also offered us another way to form small contacts in the substrate film.
At the end, we provided some suggestions in contact pattern decomposition algorithm and related
exposure-tool alignment strategies for future implementation of DPL technology.
Mask defect printability in the spacer patterning process
Show abstract
We studied the mask defect printability for both opaque and clear defects in the spacer patterning process. The spacer
patterning process consists of the development of photoresist film, the etching of the core film using the photoresist
pattern as the etching mask, the deposition of a spacer film on both sides of the core film pattern, and the removal of the
core film. The pattern pitch of the spacer film becomes half that of the photoresist. The opaque defect and the clear
defect of the mask, respectively, resulted in an "open-short complex" defect and a short defect in the spacer pattern, The
defect size of both the opaque and clear defect became smaller as the process proceeded from the development to the
core film etching and the spacer pattern fabrication. The decrease of the mask defect printability during the spacer
process is likely to be related to the reduction of the line width roughness (LWR) and to the reduction of mask enhanced
factor (MEF). The acceptable mask defect size was also studied from the viewpoint of the defect printability to the
spacer pattern for both the opaque and clear defect, and found to be 55-60nm, which was relaxed from that in ITRS2007.
DPL Implementation II
Printability verification for double-patterning technology
Show abstract
For keeping pace with Moore's Law of reducing the feature sizes on integrated circuits, the driving forces have been
reductions in the exposure-tool wavelength, and increases in the lens numerical aperture (NA). With extreme ultra-violet
(EUV) lithography and 3rd-generation immersion delayed for production use, these driving forces are now stalled at a
wavelength of 193 nm and an NA of 1.35. Therefore, double-patterning technology (DPT) is needed for printing 22 nm
device node features. With DPT, a 22 nm layout is split into two patterns. Each pattern is printed using 32 nm node
lithography technology, and the original pattern is recovered by a logical summation (the Boolean OR operation) of
these two separately exposed patterns. DPT presents several challenges for printability verification. First, the etch target
can be very different from the resist target because significant biasing is used to improve the lithography process
window. Second, overlaps between the two patterns produce new problems such as sharp-cornered pinching at pattern
junctions, and bridging between patterns. Finally, there are additional process variations: misalignment between the two
patterns, and twice as many dose and defocus dimensions. We present results from a full-chip DPT-verification tool that
addresses these challenges. We also provide examples of lithography problems that are specific to DPT, and describe
possible guidance for the resolution enhancement techniques (RET) and design tools.
Double dipole RET investigation for 32 nm metal layers
Show abstract
For 32 nm test chips, aggressive resolution enhancement technology (RET) was required for 1x metal layers to enable
printing minimum pitches before availability of the final 32 nm exposure tool. Using a currently installed immersion
scanner with 1.2 numerical aperture (NA) for early 32 nm test chips, one of the RET strategies capable of resolving the
minimum pitch with acceptable process latitude was dipole illumination. To avoid restricting the use of minimum pitch
to a single orientation, we developed a double-expose/single-develop process using horizontal and vertical dipole
illumination. To enable this RET, we developed algorithms to decompose general layouts, including random logic,
interconnect test patterns, and SRAM designs, into two mask layers: a first exposure (E1) of predominantly vertical
features, to be patterned with horizontal dipole illumination; and, a second exposure (E2) of predominantly horizontal
features, to be patterned with vertical dipole illumination. We wrote this algorithm into our OPC program, which then
applies sub-resolution assist features (SRAFs) separately to the E1 and E2 masks, coordinating the two to avoid
problems with overlapping exposures. This was followed by two-mask OPC, using E1 and E2 as mask layers and the
original layout (single layer) as the target layer. In this paper, we describe some of the issues with decomposing layout
by orientation, issues that arise in SRAF application and OPC, and some approaches we examined to address these
issues.
Double-patterning decomposition, design compliance, and verification algorithms at 32nm hp
Show abstract
Double patterning (DP) technology is one of the main candidates for RET of critical layers at 32nm hp. DP technology is
a strong RET technique that must be considered throughout the IC design and post tapeout flows. We present a complete
DP technology strategy including a DRC/DFM component, physical synthesis support and mask synthesis.
In particular, the methodology contains:
- A DRC-like layout DP compliance and design verification functions;
- A parameterization scheme that codifies manufacturing knowledge and capability;
- Judicious use of physical effect simulation to improve double-patterning quality;
- An efficient, high capacity mask synthesis function for post-tapeout processing;
- A verification function to determine the correctness and qualify of a DP solution;
Double patterning technology requires decomposition of the design to relax the pitch and effectively allows processing
with k1 factors smaller than the theoretical Rayleigh limit of 0.25. The traditional DP processes Litho-Etch-Litho- Etch
(LELE) [1] requires an additional develop and etch step, which eliminates the resolution degradation which occurs in
multiple exposure processed in the same resist layer. The theoretical k1 for a double-patterning technology applied to a
32nm half-pitch design using a 1.35NA 193nm imaging system is 0.44, whereas the k1 for a single-patterning of this
same design would be 0.22 [2], which is sub-resolution.
This paper demonstrates the methods developed at Mentor Graphics for double patterning design compliance and
decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. It also
demonstrates verification solution implementation in the chip design flow and post-tapeout flow.
RET and OPC/ORC I
Pixel-based SRAF implementation for 32nm lithography process
Show abstract
A Pixel-based sub-resolution assist feature (SRAF) insertion technique has been considered as one of the promising
solutions by maximizing the common process window. However, process window improvement of the pixel-based
SRAF technique is limited by the simplification of SRAFs for mask manufacturability. Mask simplification and mask
rule check (MRC) constraints parameters for pixel-based SRAF technique are the critical factors for mask production
without a big loss of its benefit. In this study, correlation of MRC control was analyzed in terms of the robustness to
process variation for a contact layer of 32nm device node. An optimum condition of MRC constraints was selected by
balancing the process window and mask manufacturability. In addition, a novel and practical methodology for 32nm
device node development was proposed to keep the mask complexity low and to take full advantage of process window
improvement using pixel-base SRAF insertion.
Model-based assist feature placement: an inverse imaging approach
Show abstract
The continuing reduction in feature dimensions and tightening of process constraints have led to an
increasing demand for model-based approaches, which can efficiently explore the AF solution
space, and achieve AF configurations not easily accessible via rules. In this work, we approach the
AF placement problem as an inverse imaging problem. We discuss the generation of an inverse
mask field and its use in determining the assist feature location. The results are compared with the
single iteration intensity-field based AF placement with regard to symmetry, speed, memory,
convergence, and accuracy. Several results with different pitches and illumination conditions are
presented to demonstrate the robustness and adaptability of the inverse mask AF placement.
Optimizing models based OPC fragmentation using genetic algorithms
Show abstract
Models Based Optical Proximity Correction (MBOPC) is used extensively in the semiconductor industry to achieve
robust pattern fidelity in modern lithographic processes. Much of the complexity in OPC algorithms is handled by
advanced commercial software packages. These packages give users the ability to set many parameters in the OPC code
decks which are used to customize the recipes for specific design styles and manufacturing process settings. Some of the
most important parameters in traditional OPC recipes are the fragmentation rules, which determine how edges of
polygons are fragmented in a traditional edge-based correction algorithm. It is important to find settings which can
deliver good results on a wide variety of complex layout styles.
One approach to setting these parameters is through a Design of Experiments (DOE) approach where many different
settings are tested in a systematic fashion, in an attempt to find appropriate fragmentation rules for a wide variety of
layouts. This is a very straight-forward and powerful technique, but it can be very computationally expensive,
particularly as the number of independent variables becomes large. In this paper we examine the usefulness of Genetic
Algorithm (GA) optimization techniques for setting the fragmentation parameters. Our work is focused on using GAs to
tune parameters rather than on core algorithms used in mask data correction. We use challenging metal layout patterns
and optimize fragmentation rules to try to minimize residual edge placement errors, while trying to generate
fragmentation that does not result in excessive runtime, or mask manufacturing challenges.
Single exposure is still alive: gate patterning at 45nm technology node
Show abstract
A single patterning solution is still desirable to keep the costs low for high volume wafer manufacturing. This paper will
outline the process steps necessary to scale the single patterning approach for gate level from 65mn into the 45nm
technology node. They consist mainly of the introduction of a new software for optical proximity correction, the
introduction of model based process window correction, the switch to model based etch proximity correction, and
support of an ultra dense SRAM cell. All technology requirements could be met with this single patterning solution.
Advanced mask technique to improve bit line CD uniformity of 90 nm node flash memory in low-k1 lithography
Show abstract
As devices size move toward 90nm technology node or below, defining uniform bit line CD of flash devices is one of
the most challenging features to print in KrF lithography. There are two principal difficulties in defining bit line on wafer.
One is insufficient process margin besides poor resolution compared with ArF lithography. The other is that asymmetric
bit line should be made for OPC(Optical Proximity Correction) modeling. Therefore advanced ArF lithography scanner
should be used for define bit line with RETs (Resolution Enhancement Techniques) such as immersion lithography, OPC,
PSM(Phase Shift Mask), high NA(Numerical Aperture), OAI(Off-Axis Illumination), SRAF(Sub-resolution Assistant
Feature), and mask biasing.. Like this, ArF lithography propose the method of enhancing resolution, however, we must
spend an enormous amount of CoC(cost of ownership) to utilize ArF photolithography process than KrF.
In this paper, we suggest method to improve of bit line CD uniformity, patterned by KrF lithographic process in 90nm
sFlash(stand alone Flash) devices. We applied new scheme of mask manufacturing, which is able to realize 2 different
types of mask, binary and phase-shift, into one plate. Finally, we could get the more uniform bit lines and we expect to
get more stable properties then before applying this technique.
OPC hotspot identification challenges: ORC vs. PWQ on wafer
Show abstract
The identification of OPC induced litho hotspots within the product design is essential and a must to make sure
that a new OPC model is working correctly and does no harm to the design and future product.
Several techniques and methods for OPC verification and identification of hotspots are known and long adopted
within the field. An optical rule check done by the simulation software after OPC is one way of identifying
hotspots within the design of the whole chip. This is typically done by using a DRC-type width or space check on
simulation contours (nominal exposure contour or process window contours). However, the pass/fail nature of this
check at a single CD value requires good calibration of the simulation model to avoid false positives and ease of
disposition at tapeout. Another method is the process window qualification method which uses the defect
inspection of a focus exposure matrix wafer for OPC hotspot identification. However, this can not be done prior to
ordering a mask.
Based on a 45nm line space layer OPC qualification, we will demonstrate how optical rule check and process
window qualification is performed, what the individual results will be, and how they can be used for OPC quality
evaluation. The general goal of this work is to show the capabilities of optical rule check and process window
qualification, compare both methods, and detect limitations.
Challenges for the quality control of assist features for 45nm node technology and beyond
Show abstract
Current flash memory technology is facing more and more challenges for 45nm and 32nm node technology. To get good
CD and yield control, optimized RET, OPC modeling and DFM techniques have to be applied [1]. To enhance process
window (PW) and better CD control for main features, assist features (SB) have to be used. Simulation and wafer
evaluation show that the SB CD performance is very critical. Based on OPC simulation, we can get a very good
prediction about the CD size and placement of assist features. However, we can not always get what we want from mask
suppliers. For 45nm node technology and beyond, The SB CD size (~ 20nm at 1X) has almost pushed to the current
mask process limit. Wafer fabs have a very big concern about the stability of linearity signatures from different
suppliers and different products in order to keep high accuracy of OPC models. Actually the CD linearity signature
varies from one mask supplier to another and also varies from product to product. To improve the SB CD control, the
ideal goal is to make "flat" linearity for all mask suppliers. By working closely with TPI mask supplier, we come up
solutions to improve SB CD control to get "flat" linearity. Also technology development is causing more severe SB
printability, we proposed a methodology to use AIMS for predicting SB printability. Wafer results proved the feasibility
for these methodologies.
Advanced Cleaning
Impact of MegaSonic process conditions on PRE and sub-resolution assist feature damage
Show abstract
The use of MegaSonic energy is widely accepted in photomask cleaning. For the advanced technology nodes, beyond
65nm, the problem of damaged sub resolution assist features (SRAF) becomes highly prevalent. Such feature damages
are often related to the application of MegaSonic energy.
We investigated the influence of common cleaning media and MegaSonic parameters for damaging SRAF patterns. A
special option of our cleaning tool was utilized to test a large number of different settings with low resources for test
mask and defect inspections. In this paper we will present the results of our investigations and present conditions for
MegaSonic cleaning which will enable the wide use of this technology beyond the 45nm technology node.
Tunable droplet momentum and cavitation process for damage-free cleaning of challenging particles
Show abstract
Particle removal without damage has been demonstrated for <60nm photomask sub-resolution assist features with
droplet momentum cleaning technology that employs NanoDropletTM mixed-fluid jet nozzle. Although 99%+ particle
removal efficiency can be achieved for standard Si3N4 particles with broad size distribution, there are some cleaning
challenges with small (<100nm) and large contact area (>500nm) particles. It was found that tunable uniform cavitation
can provide the additional physical assist force needed to improve cleaning efficiency of these challenging particles
while meeting the damage-fee cleaning requirement. An integrated cleaning process was developed that combines both
droplet momentum and damage-free cavitation technology. Cleaning tests were performed with different types of
challenging particles. The results showed 5-8% particle removal efficiency improvement as compared to momentum
based only cleaning. All masks were processed using the TetraTM mask cleaning tool configured with NanoDropletTM
mixed fluid jet technology and full face megasonics.
Phase shift improvement in ArF/KrF haze-free mask cleaning
Show abstract
The continuous evolution of LSI design rules has created an increased demand for the use of KrF and ArF
phase-shift photomasks (EPSMs). One of the critical issues in the use of those photomasks, especially ArF half-tone
photomasks, has been the generation of optical hazes known as (NH4)2SO4. The other critical issue has been a relatively
large phase shift of those ArF and KrF photomasks caused by so-called haze-free mask cleaning..
In the present study we used an SPM integrated clean (as a reference) consisting of heated SPM, diluted SC-1 and
heated UPW (widely known for rinsing), and a haze-free integrated mask clean consisting of Ozonated-water with a
simultaneous 222nm Excimer UV irradiation, diluted SC-1 and heated UPW. We found that both Ozonated-water with a
simultaneous 222nm Excimer UV irradiation and the diluted SC-1 (the components of the haze-free integrated clean)
caused a sizable phase shift during the mask clean. We also found that the other component of the haze-free integrated
clean, the heated UPW developed a relatively large phase shift in those photomasks. We have confirmed that the more
we repeat the use of the 172nm Excimer UV light irradiation treatment before the clean, the less (more improved) phase
shift has been realized in the haze-free clean. We found that the haze-free integrated clean also developed the CD shifts
of the above photomasks and that those CD shifts could be recovered (reduced) drastically by the use of the 172nm
Excimer UV light irradiation before the clean.
Haze Contamination Control
Crystal growth printability in an advanced foundry FAB: a correlation study between STARlight and ultra broadband BrightField inspection technologies
Show abstract
In advanced IC manufacturing reticle contamination through crystal growth causing printed defects¹ is a major source of yield
loss. This crystal growth requires frequent inspection to ensure reticles are free from such contamination (reticle requalification).
STARlight is the industry accepted method for mask inspection in wafer fabs for reticle re-qualification (requal)
². The principal focus of this paper is a study correlating the detection of contamination (crystal growth) on logic product
masks found with STARlight to defects that can be found on a print-check wafer (a photo-resist test wafer). A critical
component in this study was the translation of reticle coordinates to wafer coordinates and integrating the results between
high-resolution broadband DUV BrightField inspection (BF) and scanning electron microscope (SEM) review. All of the
STARlight defect locations were reviewed using the SEM regardless if the defect was found on opaque or on clear surfaces of
the mask. As such defects being SEM reviewed were classified as either 'printing', 'early-warning' or 'non-printing'. BF defect
inspection results after repeater analysis were compared with STARlight results to determine the correlations. SEM Defect
Review was performed on STARlight inspection results and the resulting classified data was correlated to the BF defect
inspection results.
Report of latent contamination factors inducing lithographic variation
Show abstract
We have investigated the factors having influence on the lithographic fidelity variation in 193nm masks. Significant
researches have been studied that haze contamination, resulting from the absorption of chemical residual ions and mask
container out-gassing in mask fabrication, is one of the major component to reduce the optimized lithography condition
such as Best Focus, Depth of Focus and Exposure latitude of individual feature. And also environment being containing
humidity, ambient AMC (airborne molecular contamination) react with high exposure energy to form crystal growth of
ionic molecular complex such as ammonium sulfate causing abnormal printability. Moreover, optical issue of organic
pellicle membrane is thoroughly considered that perfluoro polymer degradation induced by high photon energy affect the
transmittance intensity. Consequently, these photophysical alterations bring about the lithographic variation and cause
considerable defects in wafer printing.
In this paper, we tried to verify the influence grade inducing the lithographic variation among the latent contamination
factors consisting of mask back-side quartz contamination, the growth of exposure energy based haze phenomena, thin
organic pellicle membrane degradation and modified character of MoSiN surface. Metrological inspection and
photochemical reaction evaluations were conducted with several equipments including AIMS, Scatterometer, XPS, SIMS,
FT-IR, UV, ArF acceleration laser to demonstrate the proposal mechanism of correlation between lithographic variation
and latent contamination factors. The optical issues and lifetime of ArF PSM were simulated with the evaluation of
effects of pellicle degradation and surface modification.
Detection of progressive transmission loss due to haze with Galileo mask DUV transmittance mapping based on non imaging optics
Show abstract
In this paper, we expand on our earlier work1,2 reporting the use of high sensitivity DUV transmission metrology as a
means for detection of progressive transmission loss on mask and pellicle surfaces. We also report a use case for
incoming reticle qualification based on DUV transmission uniformity.
Traditional inspection systems rely on algorithms to locate discrete defects greater than a threshold size (typically >
100nm), or printing a wafer and then looking for repeating defects using wafer inspection and SEM review. These
types of defect inspection do not have the ability to detect transmission degradation at the low levels where it begins
to impact yield. There are numerous mechanisms for transmission degradation, including haze in its early, thin film
form, electric-field induced field migration, and pellicle degradation.
During the early development of haze, it behaves as a surface film which reduces 193nm transmission and requires
compensation by scanner dose. The film forms in a non-uniform fashion, resulting from non-uniformity of exposure
on the pattern side due to varying dose passing through the attenuating layers. As this non-uniformity evolves, there
is a gradual loss of wafer critical dimension uniformity (CDU) due to a degradation of the exposure dose
homogeneity. Electric-field induced migration also appears to manifest as a non-uniform transmission loss,
typically presenting with a radial signature.
In this paper we present evidence that a DUV transmission measurement system, GalileTM, is capable of detecting
low levels of transmission loss, prior to CDU related yield loss or the appearance of printing defects. Galileo is an
advanced DUV transmission metrology system which utilizes a wide-band, incoherent light source and non-imaging
optics to achieve sensitivities to transmission changes of less than 0.1%. Due to its very high SNR, it has a fast
MAM time of less than 1 sec per point, measuring a full field mask in as little as 30 minutes. A flexible user
interface enables users to easily define measurement recipes, threshold sensitivities, and time-based tracking of
transmission degradation. The system measures through pellicle under better than class 1 clean air conditions.
A new paradigm for haze improvement: retardation of haze occurrence by creating mask substrate insensitive to chemical contamination level
Show abstract
Haze issues are getting more serious since size of Haze defect printable on the water surface that could matter is
decreasing further with reduced pattern size. Many efforts have been made to reduce the contamination level on the
photomask surface by applying wet or dry processes. We have successfully reduced surface contamination down to subppb
level for organic and inorganic chemicals. No matter how well the mask surface is cleaned, chemical contaminant
cannot be perfectly eliminated from the surface. As long as contaminants exist on the surface, they are getting aggregated
around certain points with higher energy to create defects on it during laser exposure. Also, the cleaned mask surface
could be contaminated again during following processes such as shipping and storage.
Here, we propose a new paradigm for Haze retardation where we severely decelerate defect generation and growth
rather than eliminate chemical contaminants on the mask surface. We have made mask surface on which chemical
contaminants are hardly accumulated to generate Haze defects even during laser exposure. By creating mask surface
insensitive to chemical impurity level up to a certain degree, we are able to retard Haze occurrence much better than by
reducing surface impurities down to sub-ppb level. This approach has another advantage of allowing a freedom for mask
environment during the process of shipping, storage, and exposure.
We further investigate how the treated mask surface should have strong resistance against chemical contaminant
aggregation towards Haze defect generation around specific points with high energy.
Simulation analysis of backside defects printability in 193nm photolithography
Show abstract
Backside defects a few micrometers in size are serious concern in lithography because they can degrade the image
quality on a wafer. It was known that defects attached on the backside affected the printing images on a wafer by locally
altering the partial coherence (σ) and the transmitted intensity of the illumination. The ability to detect and to simulate
their impact of defects on the backside is one of the key components in ensuring quality of photomask.
The purpose of this study is to determine the minimum size of defects on the backside which would be affected
printability in 193nm photolithography. It was investigated to the influence of wafer critical dimension (CD) variation
according to illumination and NA, that of refraction according to defect size.
For this study, a reticle was designed to include line and space patterns, contact patterns and isolated patterns on the front
side. And the type of defects attached on the backside was made of chrome to investigate the relation between
transmittance of backside defects and its printability.
The correlation of measurements made with UV and DUV-based inspection system; simulation performed with a
193nm aerial image measurement system. Besides the allowable size of backside defects was determined using the
criterion of a maximum intensity variation of 10%.
Wafer Plane Inspection
Optimal mask characterization by Surrogate Wafer Print (SWaP) method
Show abstract
Traditionally, definition of mask specifications is done completely by the mask user, while characterization of the mask
relative to the specifications is done completely by the mask maker. As the challenges of low-k1 imaging continue to
grow in scope of designs and in absolute complexity, the inevitable partnership between wafer lithographers and mask
makers has strengthened as well. This is reflected in the jointly owned mask facilities and device manufacturers'
continued maintenance of fully captive mask shops which foster the closer mask-litho relationships. However, while
some device manufacturers have leveraged this to optimize mask specifications before the mask is built and, therefore,
improve mask yield and cost, the opportunity for post-fabrication partnering on mask characterization is more apparent
and compelling.
The Advanced Mask Technology Center (AMTC) has been investigating the concept of assessing how a mask images,
rather than the mask's physical attributes, as a technically superior and lower-cost method to characterize a mask. The
idea of printing a mask under its intended imaging conditions, then characterizing the imaged wafer as a surrogate for
traditional mask inspections and measurements represents the ultimate method to characterize a mask's performance,
which is most meaningful to the user. Surrogate wafer print (SWaP) is already done as part of leading-edge wafer fab
mask qualification to validate defect and dimensional performance.
In the past, the prospect of executing this concept has generally been summarily discarded as technically untenable and
logistically intractable. The AMTC published a paper at BACUS 2007 successfully demonstrating the performance of
SWaP for the characterization of defects as an alternative to traditional mask inspection [1]. It showed that this concept is
not only feasible, but, in some cases, desirable.
This paper expands on last year's work at AMTC to assess the full implementation of SWaP as an enhancement to mask
characterization quality including defectivity, dimensional control, pattern fidelity, and in-plane distortion. We present a
thorough analysis of both the technical and logistical challenges coupled with an objective view of the advantages and
disadvantages from both the technical and financial perspectives. The analysis and model used by the AMTC will serve
to provoke other mask shops to prepare their own analyses then consider this new paradigm for mask characterization
and qualification.
High resolution inspection with wafer plane die: database defect detection
Show abstract
High Resolution reticle inspection is well-established as a proven, effective, and efficient means of detecting yieldlimiting
mask defects as well as defects which are not immediately yield-limiting yet can enable manufacturing process
improvements. Historically, RAPID products have enabled detection of both classes of these defects. The newlydeveloped
Wafer Plane Inspection (WPI) detector technology meets the needs of some advanced mask manufacturers to
identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. Wafer
Plane Inspection accomplishes this goal by performing defect detection based on a modeled image of how the mask
features would actually print in the photoresist. This has the effect of reducing sensitivity to non-printing defects while
enabling higher sensitivity focused in high MEEF areas where small reticle defects still yield significant printing defects
on wafers.
This approach has several important features. The ability to ignore non-printing defects and to apply additional effective
sensitivity in high MEEF areas enables advanced node development. In addition, the modeling allows the inclusion of
important polarization effects that occur in the resist for high NA operation. This allows for the results to better match
wafer print results compared to alternate approaches. Finally, the simulation easily allows for the application of
arbitrary illumination profiles. With this approach, users of WPI can make use of unique or custom scanner illumination
profiles. This allows the more precise modeling of profiles without inspection system hardware modification or loss of
company intellectual property.
A previous paper [1] introduced WPI in D:D mode. This paper examines the operation and results for WPI in
Die:Database mode.
Wafer plane inspection evaluated for photomask production
Show abstract
Wafer Plane Inspection (WPI) is a novel approach to inspection, developed to enable high inspectability on fragmented
mask features at the optimal defect sensitivity. It builds on well-established high resolution inspection capabilities to
complement existing manufacturing methods. The production of defect-free photomasks is practical today only because
of informed decisions on the impact of defects identified. The defect size, location and its measured printing impact can
dictate that a mask is perfectly good for lithographic purposes. This inspection - verification - repair loop is timeconsuming
and is predicated on the fact that detectable photomask defects do not always resolve or matter on wafer.
This paper will introduce and evaluate an alternative approach that moves the mask inspection to the wafer plane. WPI
uses a high NA inspection of the mask to construct a physical mask model. This mask model is used to create the mask
image in the wafer plane. Finally, a threshold model is applied to enhance sensitivity to printing defects. WPI essentially
eliminates the non-printing inspection stops and relaxes some of the pattern restrictions currently placed on incoming
photomask designs. This paper outlines the WPI technology and explores its application to patterns and substrates
representative of 32nm designs. The implications of deploying Wafer Plane Inspection will be discussed.
Wafer plane inspection with soft resist thresholding
Show abstract
Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto-
noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to
enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers
to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI
accomplishes this goal by performing defect detection based on a modeled image of how the mask features would
actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images
provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane
allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic
portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window
inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a
valuable addition to the KLA-Tencor detection algorithm suite.
The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be
adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated
processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist
threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome
requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative
approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most
challenging processes. This approach is just finishing beta testing with a customer developing advanced node designs.
AIMS and resist simulation
Show abstract
The AIMTM45-193i is the established tool for mask performance qualification and defect printing
analysis in the mask shop under scanner conditions. Vector effects are taken into account by the
proprietary Zeiss vector effect emulator. In several studies an excellent correlation to wafer prints has
been reported. However, a systematic offset to wafer prints in terms of mask error enhancement factor
(MEEF) and exposure latitude has been observed which is attributed to well known resist effects.
The AIMSTM measures the aerial image in resist whereas in a real lithography process further image blur
of the latent image is caused by photo acid diffusion during wafer processing and resist development. To
explain the gap between the AIMTM and wafer prints we have investigated aerial images in combination
with an easy to use resist model. It does take resist effects into account with sufficient accuracy to
explain printing behavior of photo masks but without the need to calibrate lots of parameters of the
actually used resist which usually are not known to a mask shop.
The resist effects predominantly reduce the image contrast and thus increase the MEEF and the
sensitivity to mask defects. This somewhat counterintuitive behavior is labeled "contrast enhancement
by contrast reduction". Additionally application of the resist model improves the agreement of e.g. the
exposure latitude or MEEF measured by the AIMSTM compared to wafer prints.
AIMS-45 image validation of contact hole patterns after inverse lithography at NA 1.35
Show abstract
The AIMSTM-45, when used in scanner mode, can emulate image intensity as seen in resist on the wafer at scanner
illumination conditions. We show that this feature makes AIMSTM-45 well-suited to analyze patterns treated with
inverse lithography. We have used an inverse lithography technique by Mentor Graphics, to treat a random contact hole
layout (drawn at minimal pitch 115nm) for imaging at NA 1.35. The combination of the dense 115nm pitch and available
NA of 1.35 makes Quasar illumination necessary, and the inverse lithography treatment automatically generated optimal
(model-based) Assist Features (AF) for all geometries in the design. The mask, after inverse lithography treatment, has
CH patterns with numerous AF of different sizes and orientations, and is a challenge for both mask making and mask
qualification. We have analyzed the inverse lithography masks with the model-based AF using an AIMSTM-45 aerial
image measurement tool, and compare the results of the AIMSTM-45 to wafer data obtained after exposure on an ASML
XT:1900i. A first benefit of AIMTM-45 is that the most meaningful quantity (image in resist) is generated without the
intermediate steps of doing multiple reticle SEM measurements followed by extensive simulation. A second point of
interest is that the AIMSTM-45 generates image intensities, which allows a direct validation of the intensity-driven
inverse litho conversion. Both features prove the value of the AIMSTM-45 for analyzing inverse litho masks and
geometries.
Inspection
Auto-classification and simulation of mask defects using SEM and CAD images
Show abstract
Mask defect disposition gets more difficult and time-consuming with each progressive lithography node. Mask
inspection tools commonly use 250 nm wavelength, giving resolution of 180 nm, so critical defect sizes are far less than
the optical resolution - too small for defect analysis. Thus the rate of false or nuisance defect detection is increasing
rapidly and analysis of detected defects is increasingly difficult. As to judging the wafer printability of defects, AIMS
(Aerial Image Measurement System) tools are commonly used but are also time-consuming if defect count is high. For
improving the efficiency of mask defect disposition, we propose the combination of a SEM defect review tool and defect
disposition and simulation software, which use high-resolution SEM images of defects to do defect review, defect
disposition, and wafer printing simulation of defects automatically or manually.
The SEM defect review tool, DIS-05 developed by Holon Co. Ltd., is designed for defect review and disposition using
reference images derived from e-beam files or CAD database. This tool uses the Automated Defect Analysis Software
(ADAS) developed from AVI LLC. to interface the inspection tool and the DIS-05. ADAS detects false defects before
SEM imaging and performs aerial image simulation from the SEM and CAD images to estimate the wafer CD error
caused by each defect. We report on its speed (>300 defects/hour), classification accuracy and simulation accuracy when
used with masks at the 45 nm technology node and beyond. This combination of SEM and ADAS is expected to
significantly accelerate process development and production for the 45 and 32 nm nodes. It will also increase the masksper-
day throughput of inspection and AIMS tools by shifting most defect review to ADAS software using SEM images.
At preliminary tests showed the combination tool can do auto defect disposition and simulation with promising results.
Novel mask inspection flow using Sensitivity Control Layers (SCL) on the TeraScanHR-587 platform
Show abstract
Conventional photomask inspection techniques utilize global sensitivity for all inspected area in the die; SRAF and OPC
features become the sensitivity-limiters, which can result in reduced visibility to defects of interest (DOI). We describe
the implementation of Sensitivity Control Layer (SCL), a novel database inspection methodology for the KLA-Tencor
TerascanHR platform. This methodology enables inspection at maximum sensitivity in critical die-areas via "layer
definition" during job set-up and sensitivity management of the layers during inspection. Memory device inspection
performance was improved through the use of up to six control layers to increase sensitivity in the active area while
reducing nuisance detections by as much as 100X. The corresponding inspection time was reduced by 30%, illustrating
the potential for substantial throughput advantage using SCL. Post-inspection analysis and improved disposition
accuracy of the SCL-enabled inspections will also benefit cycle time and higher throughput. In all test cases, sensitivity
parameters were increased in the regions of interest over baseline inspections run with typical production-use
methodologies. SCL inspection management and application on OPC structures, SRAFs, and MRC violations (slivers)
are discussed in detail.
Evaluating practical vs. theoretical inspection system capability with a new programmed defect test mask designed for 3X and 4X technology nodes
Show abstract
Programmed defect test masks serve the useful purpose of evaluating inspection system sensitivity and capability. It is
widely recognized that when evaluating inspection system capability, it is important to understand the actual sensitivity
of the inspection system in production; yet unfortunately we have observed that many test masks are a more accurate
judge of theoretical sensitivity rather than real-world usable capability. Use of ineffective test masks leave the purchaser
of inspection equipment open to the risks of over-estimating the capability of their inspection solution and overspecifying
defect sensitivity to their customers. This can result in catastrophic yield loss for device makers. In this paper
we examine some of the lithography-related technology advances which place an increasing burden on mask inspection
complexity, such as MEEF, defect printability estimation, aggressive OPC, double patterning, and OPC jogs. We
evaluate the key inspection system component contributors to successful mask inspection, including what can "go
wrong" with these components. We designed and fabricated a test mask which both (a) more faithfully represents actual
production use cases; and (b) stresses the key components of the inspection system. This mask's patterns represent
32nm, 36nm, and 45nm logic and memory technology including metal and poly like background patterns with
programmed defects.
This test mask takes into consideration requirements of advanced lithography, such as MEEF, defect printability, assist
features, nearly-repetitive patterns, and data preparation. This mask uses patterns representative of 32nm, 36nm, and
45nm logic, flash, and DRAM technology. It is specifically designed to have metal and poly like background patterns
with programmed defects. The mask is complex tritone and was designed for annular immersion lithography.
Defect Repair
Nanomachining photomask repair of complex patterns
Show abstract
Improvements in repair process, software, and AFM tip technology have brought about an overall 2D shape
reconstruction capability to nanomachining that has not been previously imagined. Repair results are shown
for various processes to highlight their relative strengths and weaknesses. The impact of technical
improvements is shown in the advances in repair dimensional precision and overall imaging performance. The
greater technical potential of nanomachining is realized in this examination for mask repair scaled to smaller
repair geometries while repairing larger defects that may span these critical patterns.
Practical laser mask repair in the contemporary production environment
Show abstract
It has been found that the femtosecond DUV laser mask repair tool has significant utility in the repair of unknown
foreign material (FM) contamination of sizes ranging from 50 nm to 30 μm with highly variable z-heights both
isolated and within critical complex patterns. Another significant ROI is the repair of masks which have already
been pelliclized (through pellicle repair or TPR) where the laser repair tool may work in conjunction with existing
through-pellicle inspection hardware to detect and remove FM and correct pattern errors. The capability of the tool
is also explored for repairs in patterns including the 45 nm technology node.
Advanced process capabilities for electron beam based photomask repair in a production environment
Show abstract
The cost and time associated with the production of photolithographic masks continues to grow, driven by the ever
decreasing feature size, advanced mask technologies and complex resolution enhancing techniques. Thus employment of
a high-resolution, comprehensive mask repair tool becomes a key element for a successful production line. The MeRiT®
utilizes electron beam induced chemistry to repair both clear and opaque defects on a variety of masks and materials with
the highest available resolution and edge placement precision. This paper describes the benefits of the electron beam
induced technique as employed by the MeRiT® system for a production environment.
RET and OPC/ORC II
32nm 1-D regular pitch SRAM bitcell design for interference-assisted lithography
Show abstract
As optical lithography advances into the 45nm technology node and beyond, new manufacturing-aware design requirements
have emerged. We address layout design for interference-assisted lithography (IAL), a double exposure method that
combines maskless interference lithography (IL) and projection lithography (PL); cf. hybrid optical maskless lithography
(HOMA) in [2] and [3]. Since IL can generate dense but regular pitch patterns, a key challenge to deployment of IAL is
the conversion of existing designs to regular-linewidth, regular-pitch layouts. In this paper, we propose new 1-D regular
pitch SRAM bitcell layouts which are amenable to IAL. We evaluate the feasibility of our bitcell designs via lithography
simulations and circuit simulations, and confirm that the proposed bitcells can be successfully printed by IAL and that
their electrical characteristics are comparable to those of existing bitcells.
Convergence-based OPC method for dense simulations
Show abstract
As the process of migration of Optical process correction (OPC) recipes continues to go from sparse to dense
computations, a run time effectiveness issue persists to remain for huge structures that exist in some metal and active
layers designs. Even for 45 and 32 nm technology nodes, some polygons might be several microns in width consuming a
vast amount of simulation time and order of magnitudes more than sparse simulations to converge. Practically, this
problem is pronounced, which is usually the case, when the design comprises these huge structures and other small
critical ones that needs many iterations and careful tuning to converge. And thus, a considerable amount of run time will
be wasted while applying these sophisticated recipes on big structures that could originally converge within few
iterations using a simple recipe.
In this context, a convergence-based dense OPC recipe is proposed to deal with designs that have both types of
structures. The basic idea is to check convergence prior starting next iteration and skip the rest of the iterations if the
whole simulated frame has converged within a predefined tolerance. Also, a reasonable way to define tolerances is
explored.
Combination of rule and pattern based lithography unfriendly pattern detection in OPC flow
Show abstract
Foundry companies encounter again and again the same or similar lithography unfriendly patterns (Hot-spots) in
different designs within the same technology node and across different technology nodes, which eluded design rule
check (DRC), but detected again and again in OPC verification step. Since Model-based OPC tool applies OPC on
whole-chip design basis, individual hot-spot patterns are treated same as the rest of design patterns, regardless of its
severity.
We have developed a methodology to detect those frequently appeared hot-spots in pre-OPC design, as well as post
OPC designs to separate them from the rest of designs, which provide the opportunity to treat them differently in early
OPC flow. The methodology utilizes the combination of rule based and pattern based detection algorithms. Some hotspot
patterns can be detected using rule-based algorithm, which offer the flexibility of detecting similar patterns within
pre-defined ranges. However, not all patterns can be detected (or defined) by rules. Thus, a pattern-based approach is
developed using defect pattern library concept. The GDS/OASIS format hot-spot patterns can be saved into a defect
pattern library. Fast pattern matching algorithm is used to detect hot-spot patterns in a design using the library as a
pattern template database. Even though the pattern matching approach lacks the flexibility to detect patterns' similarity,
but it has the capability to detect any patterns as long as a template exists. The pattern-matching algorithm can be either
exact match or a fuzzy match. The rule based and pattern based hot-spot pattern detection algorithms complement each
other and offer both speed and flexibility in hot spot pattern detection in pre-OPC and post-OPC designs.
In this paper, we will demonstrate the methodology in our OPC flow and the benefits of such methodology application
in production environment for 90nm designs. After the hot spot pattern detection, examples of special treatment to
selected hot spot patterns will be shown.
Automated OPC model collection, cleaning, and calibration flow
Show abstract
OPC model calibration requires thousands of experimental data points. These are then used to calibrate an OPC model. Today, the majority of these steps are performed manually. Metrology for example involves taking the CD-SEM offline for an operator to program it. Considerable time savings is possible by writing the CD-SEM recipe offline. Experimental data preparation is also often performed manually. Manual review of thousands of data points is a tedious task prone to human errors. Here again, automation can greatly alleviate the engineering effort, reduce cycle-time and improve data quality. Data quality improvement alone has been shown to have a significant benefit to model calibration accuracy and predictability.
In this paper we present an automated solution for the currently engineering effort intensive components of the OPC model calibration flow. The flow we present is integrated inside the OPC environment. We suggest best practices identified through the implementation of an automated flow, and discuss benefits. Our results demonstrate the capability and quantify the benefits which automation brings in human effort, reduced time to accurate model and improved model quality.
Simulation and Modeling I
Improvements in accuracy of dense OPC models
Show abstract
Performing model-based optical proximity correction (MBOPC) on layouts has become an integral part of
patterning advanced integrated circuits. Earlier technologies used sparse OPC, the run times of which explode when the
density of layouts increases. With the move to 45 nm technology node, this increase in run time has resulted in a shift to
dense simulation OPC, which is pixel-based. The dense approach becomes more efficient at 45nm technology node and
beyond. New OPC model forms can be used with the dense simulation OPC engine, providing the greater accuracy
required by smaller technology nodes. Parameters in the optical model have to be optimized to achieve the required
accuracy. Dense OPC uses a resist model with a different set of parameters than sparse OPC. The default search ranges
used in the optimization of these resist parameters do not always result in the best accuracy. However, it is possible to
improve the accuracy of the resist models by understanding the restrictions placed on the search ranges of the physical
parameters during optimization. This paper will present results showing the correlation between accuracy of the models
and some of these optical and resist parameters. The results will show that better optimization can improve the model
fitness of features in both the calibration and verification set.
Defining a physically accurate laser bandwidth input for optical proximity correction (OPC) and modeling
Show abstract
In this study, we discuss modeling finite laser bandwidth for application to optical proximity
modeling and correction. We discuss the accuracy of commonly-used approximations to the laser spectrum
shape, namely the modified Lorentzian and Gaussian forms compared to using measurement-derived laser
fingerprints. In this work, we show that the use of the common analytic functions can induce edge
placement errors of several nanometers compared to the measured data and therefore do not offer
significant improvement compared to the monochromatic assumption. On the other hand, the highlyaccurate
laser spectrum data can be reduced to a manageable number of samples and still result in sub
0.5nm error through pitch and focus compared to measured spectra. We have previously demonstrated that
a 23-point approximation to the laser data can be generated from the spectrometry data, which results in
less than 0.1nm RMS error even over varied illumination settings. We investigate the further reduction in
number of spectral samples down to five points and consider the resulting accuracy and model-robustness
tradeoffs. We also extend our analysis as a function of numerical aperture and illumination setting to
quantify the model robustness of the physical approximations. Given that adding information about the
laser spectrum would primarily impact the model-generation run-times and not the run-times for the OPC
implementation, these techniques should be straightforward to integrate with current full-chip OPC flows.
Finally, we compare the relative performance of a monochromatic model, a 5-point laser-spectral
fingerprint, and two Modified Lorentzian fits in a commercial OPC simulator for a 32nm logic lithography
process. The model performance is compared at nominal process settings as well as through dose, focus
and mask bias. Our conclusions point to the direction for integration of this approach within the framework
of existing EDA tools and flows for OPC model generation and process-variability verification.
Benchmark of rigorous methods for electromagnetic field simulations
Show abstract
We have developed an interface which allows to perform rigorous electromagnetic field (EMF) simulations with
the simulator JCMsuite and subsequent aerial imaging and resist simulations with the simulator Dr.LiTHO.With
the combined tools we investigate the convergence of near-field and far-field results for different DUV masks.
We also benchmark results obtained with the waveguide-method EMF solver included in Dr.LiTHO and with
the finite-element-method EMF solver JCMsuite. We demonstrate results on convergence for dense and isolated
hole arrays, for masks including diagonal structures, and for a large 3D mask pattern of lateral size 10 microns
by 10 microns.
Fast and accurate hybrid subgrid and subcell finite-difference time-domain methods for the simulation of mask electromagnetic effects in sub-45nm lithography
Show abstract
Subgrid and subcell FDTD (S-FDTD) methods are described. They can be used for the fast and accurate
simulation of mask electromagnetic effects in sub-45nm lithography. The accuracies of the S-FDTD methods are
verified by comparison with FDTD and with a very accurate pseudospectral reference solution. The S-FDTD
methods are an order of magnitude or more faster than FDTD. Furthermore, the S-FDTD methods require much
less memory than FDTD for time marching. Hence, much larger mask areas can be simulated with S-FDTD than
with FDTD.
An efficient method for transfer cross coefficient approximation in model based optical proximity correction
Show abstract
Model Based Optical Proximity Correction (MBOPC) is since a decade a widely used technique that permits
to achieve resolutions on silicon layout smaller than the wave-length which is used in commercially-available
photolithography tools. This is an important point, because masks dimensions are continuously shrinking.
As for the current masks, several billions of segments have to be moved, and also, several iterations are needed
to reach convergence. Therefore, fast and accurate algorithms are mandatory to perform OPC on a mask in a
reasonably short time for industrial purposes.
As imaging with an optical lithography system is similar to microscopy, the theory used in MBOPC is drawn
from the works originally conducted for the theory of microscopy. Fourier Optics was first developed by Abbe to
describe the image formed by a microscope and is often referred to as Abbe formulation. This is one of the best
methods for optimizing illumination and is used in most of the commercially available lithography simulation
packages.
Hopkins method, developed later in 1951, is the best method for mask optimization. Consequently, Hopkins
formulation, widely used for partially coherent illumination, and thus for lithography, is present in most of the
commercially available OPC tools. This formulation has the advantage of a four-way transmission function independent
of the mask layout. The values of this function, called Transfer Cross Coefficients (TCC), describe
the illumination and projection pupils.
Commonly-used algorithms, involving TCC of Hopkins formulation to compute aerial images during MBOPC
treatment, are based on TCC decomposition into its eigenvectors using matricization and the well-known Singular
Value Decomposition (SVD) tool. These techniques that use numerical approximation and empirical determination
of the number of eigenvectors taken into account, could not match reality and lead to an information loss.
They also remain highly runtime consuming.
We propose an original technique, inspired from tensor signal processing tools. Our aim is to improve the simulation
results and to obtain a faster algorithm runtime. We consider multiway array called tensor data T CC. Then,
in order to compute an aerial image, we develop a lower-rank tensor approximation algorithm based on the signal
subspaces. For this purpose, we propose to replace SVD by the Higher Order SVD to compute the eigenvectors
associated with the different modes of TCC. Finally, we propose a new criterion to estimate the optimal number
of leading eigenvectors required to obtain a good approximation while ensuring a low information loss.
Numerical results we present show that our proposed approach is a fast and accurate for computing aerial
images.
Simulation and Modeling II
Scanner-specific separable models for computational lithography
Show abstract
The usage of conventional OPC models traditionally was confined to the specific process conditions at which the models
were. Separable models for computational lithography (CL), including OPC and post-OPC layout verification, allow
extrapolation of the calibrated model and accurate prediction at process conditions different from the exact settings used
for model calibration. This capability enables significantly reduced turnaround time in early process development, and it
opens the way for new applications such as model based process optimization. It relies on sufficiently accurate modeling
of litho process components as separate subsystems, in particular mask, scanner optics, and resist process. Inclusion of
actual machine parameters of the exposure tool in the optical model can improve model accuracy and predictability,
while 'actual machine parameters' may represent either a specific scanner type or an individual exposure tool. We study
the impact of machine parameters that can be incorporated in a modern computational litho model, by analyzing their
relative effect on predicted CD measurements and extract a ranking in terms of their expected benefit for model
separability. An experimental study demonstrates improved model accuracy and separability by inclusion of either
scanner-type specific model data or individual machine-specific metrology data in the CL model building process.
Considering MEEF in inverse lithography technology (ILT) and source mask optimization (SMO)
Show abstract
Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM and RET flow required to
continue shrinking designs in the low-k1 lithography regime. The ability to model and minimize MEEF during
lithography optimization and RET application is essential to obtain a usable process window (PW). In Inverse
Lithography Technology (ILT), MEEF can be included in the cost function as a nonlinear factor, so that the inversion
minimizes MEEF, in addition to optimizing PW and edge placement error (EPE). ILT has been shown to optimize
masks for a given source. Using ILT for contemporaneous Source and Mask co-Optimization (SMO) can provide further
benefit by balancing the complexity of mask and source. Results demonstrating the benefits of "MEEF-aware" ILT and
SMO for advanced technology nodes are presented in this paper.
Smoothing based model for images of buried EUV multilayer defects near absorber features
Show abstract
A modification has been made to the fast simulator RADICAL which allows it to simulate the reflected field from an EUV mask with a buried defect 15,000 times faster than the finite difference time domain method (FDTD). This new version uses an advanced single surface approximation (SSA) instead of ray tracing to model the defective multilayer stack. RADICAL with SSA can simulate a 32nm line space pattern with a buried defect in 4.0s. The accuracy of this method is verified with comparisons to FDTD simulations and good agreement is shown. The ability of this method to simulate large layouts with arbitrary defects is demonstrated. A 1.5μm x 1.5μm layout with an arbitrary buried defect and multilayer surface roughness is simulated in 75s.
An alternative algebraic fast model for buried defects near absorber lines is also investigated based on the linear relationship between the surface height of isolated buried defects and the aerial image dip strength. However, the interaction is shown to be too complicated for accurate representation with the model proposed.
Simulation-based EUV source and mask optimization
Show abstract
Source and mask optimization has become a promising technique to push the limits of 193 nm immersion lithography. As
the introduction of EUV lithography is at least delayed to the 22 nm technology node, sophisticated resolution enhancement
techniques will already be required at a very early stage. Thus, pinpointing ideal mask layouts, mask materials, and
illumination settings are as important aspects for EUV as for optical lithography. In this paper, we propose the application
of global optimization techniques to identify appropriate process conditions for EUV lithography, using rigorous mask and
imaging simulations.
DFM
DFM viewpoints of cell-level layout assessments and indications for concurrent layout optimization
Show abstract
Design-for-manufacturing (DFM) is becoming an actual design practice among IC manufacturers, designers and
EDA companies. Layout assessment by design-rule-check (DRC) using EDA tools is a common practice today to ensure
well-manufactured design geometries. Standalone DFM tools, which require iteration loops of DFM analysis and fixing,
do not fit well in design flows and are considered cumbersome. A better layout assessment method for DFM issues is
required: one that gives actionable feedback, and that can be used with automatic optimization in early design stages.
The latter is needed to avoid costly design re-spins that will consume critical time-to-market as well as use a lot of
engineering resources, reticles and wafer material costs. For example, a DFM checking tool may report the hotspot types
and locations, but this information is not sufficient for designers to decide tradeoffs between different fixing choices and
to take care of trade-off between physical and electrical design constraints at the same time. When model-based
properties are introduced such as lithographic contour, the tradeoffs between rule-based and model-based properties can
only be resolved by the automatic and concurrent optimization.
This work demonstrates a methodology of DFM scoring of layout based on preferred rules compliance, lithography
GATE printability, as well as the layout fixing. The electrical impact on gates is analyzed and showed reduced variability
(compared to nominal behavior) in gate performance. Designers can get visual feedback of the layout quality, as well as
improvement suggestions. Takumi TKE software is used to demonstrate automatic and concurrent optimization. The
method applies to both cell-level and custom designs.
Concurrent optimization of MDP, mask writing, and mask inspection for mask manufacturing cost reduction
Show abstract
As the feature size of LSI shrinks the cost of mask manufacturing and turn-around-time (TAT) continues to increase.
These increases are reaching to points of great concerns. Association of Super-Advanced Electronics Technologies
(ASET) Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) launched a 4-year
program for reducing mask manufacturing cost and TAT by concurrent optimization of MDP, mask writing, and mask
inspection that involves exploitation of close relationships and synergism among them. The task will be accomplished by
sharing four key avenues: a) common data format, b) clever use of repeating patterns, c) pattern prioritization based on
design intent, and d) parallel processing. Under the concurrent optimization scheme, mask pattern priorities that we call
as Mask Data Rank (MDR) are extracted from the design side, and repeating patterns are extracted from mask pattern
data. These are fed-forward to mask writing and mask inspection sides. In mask writing, MDR is employed to optimize
the writing conditions; and in Character Projection (CP) writing, repeating patterns are utilized for that purpose. In mask
inspection, MDR is used to optimize defect judgment conditions, and repeating patterns are utilized for efficient review.
For mask writing, we are developing a parallel e-beam writing system Multi Column Cell (MCC). Furthermore, we are
developing an integrated diagnostic system for e-beam mask writer, and a technology for defect judgment technology
based on defect printability in mask inspection. In this paper we describe details of our activity, its status, and some
recent results.
Design for manufacturability guideline development: integrated foundry approach
Show abstract
It has been widely accepted that to ensure good yield in IC wafer manufacturing, early adaptation of DFM (Design for
Manufacturability) guidelines in design phase is required and it is particularly true in Foundry business. Integrated
foundry approaches for DFM guideline development were presented in this paper. With emphasis of process variations
and process sensitivity impact on design patterns, we describe the procedure of the combination of rule-based and
simulation-based lithographical hotspot pattern characterizations. An evaluation of process sensitivity metrics for
analyzing potential pattern hotspots is then described. In addition, based on hotspot pattern severity, repeated patterns
from different designs are saved into a pattern library as knowledge deposition tool and those patterns can be easily
identified later in new designs through pattern search, which is much faster than simulation based hotspot detections.
With this approach, a set of DFM compliance rules is derived to designs in the design implementation stage for both
110nm and 90nm technology nodes, striving to gain more yield, device performance, and improve time-to-volume
production.
Flexible sensitivity inspection with TK-CMI software for criticality-awareness
Show abstract
In this paper we present the method that NuFlare photomask inspection systems can use to strongly reduce
pseudo detections by use of TK-CMI software. The NuFlare inspection system is capable to detect the
smallest defects in the 45 and 32-nm nodes and has recently been introduced to production. It links up with
a compute cluster with Takumi's Criticality-Marker Information software (TK-CMI). TK-CMI quickly analyzes
the ~200GB post-OPC layout or multi-layer pre-OPC layout and assigns various types of criticality regions.
The basic set of criticalities is made to address the challenges that typical maskmakers experience. The TKCMI
system also supports design-intent-based criticalities. The NuFlare inspection system uses this full-mask
criticality information and generates flexible inspection recipes that inspect low-criticality areas with relaxed
sensitivity resulting in reduction of pseudo detections in such regions.
Improving contact and via process latitude through selective upsizing
Show abstract
This paper describes a simple technique to improve the process latitude for contact and via printing. The technique
applies a selective upsizing algorithm to the mask data during the mask preparation step. For each contact or via, the
algorithm looks for available spaces by checking relevant layers near it. When spaces are available, selective edges of a
contact or via will be sized to improve the process latitude. This paper describes algorithms used to implement this
technique. Multiple designs of various design styles are used to demonstrate the effectiveness of the algorithms. The
implications on mask preparation, mask making and wafer processing are also discussed.
Assist feature aware double patterning decomposition
Show abstract
Double patterning has gained prominence as the most likely lithographic methodology to help keep Moore's law going
towards 32nm 1/2 pitch lithography. While solutions, to date, have focused mainly on gap splitting to avoid minimum
spacing violations, the decomposition should, ideally, also attempt to optimize the process window of the decomposed
masks. A major contributor to process window sensitivity is the correct placement of sub-resolvable assist features.
These features are placed once the polygons of each mask are defined, i.e. post decomposition. If some awareness of this
downstream process step is made available to the double patterning decomposition stage, then a more robust
decomposition can be achieved.
EUV Mask Processing and Substrates
Development status of EUVL mask blanks
Show abstract
Extreme ultraviolet lithography (EUVL) is the most promising lithographic technology to fabricate the next
generation devices with a 20~30 nm feature size or smaller. The production of the EUVL mask blank is one of the
critical issues to realize the EUVL because of various kinds of stringent requirements. For instance, a <+/-5 ppb/K
thermal expansion coefficient (CTE) and a <30 nm surface flatness of the polished substrate, a high and uniform
reflectivity at the 13~14 nm wavelength of the reflective multilayer film, and a low defect density as small as 30nm of
the blank. Most of these requirements are different from the optical lithography mask blank and some are specific to the
EUVL blank. We have continuously been developing all of key materials and processes essential to prepare the EUVL
mask blank, and we showed a good progress in its performance improvement. Our low thermal expansion material
(LTEM) showed the CTE properties requirements defined in SEMI P37, which were 0 +/- 5 ppb/K mean CTE at 22°C
and < +/-3 ppb/K CTE spatial variation across 6 inch square substrate. ~30nm flatness was demonstrated on both front
and back surfaces of the LTEM polished substrate, which was very close to the most stringent flatness requirement of
SEMI P37. Ta-based absorber film and anti-reflective film were also developed. Their film properties almost met SEMI
P38 class A, and the absorbers showed good etching and patterning performances with the inductively coupled plasma
etching process. In addition, the thinner resist coating process was developed. As a consequence, Asahi Glass has a
capability to deliver the ready-to-write EUVL blank which is the most suitable for the EUVL process developments by
using the full field exposure tools.
Chemical durability studies of Ru-capped EUV mask blanks
Show abstract
Surface cleaning has become one of the most critical processes in photomask manufacturing in the last few years
because of the demands for high cleaning efficiency with no film loss and no damage to fragile patterns. The requirement
is getting tighter as the feature-size shrinks. In addition, EUV masks pose further unique challenges in the cleaning
process, because of the reflective multilayer (ML) mask structure, which is sensitive to surface damage, and a more
frequent cleaning requirement due to the lack of pellicle protection during handing and usage. To address the challenge
of ML surface damage from EUV mask cleaning processes, this paper presents the chemical durability of Ru-capped ML
blanks against two types of chemistries: a mixture of sulfuric acid and hydrogen peroxide (SPM) and ozonated water
(DIO3). The authors found that SPM slightly oxidized the Ru capping layer, but with minimal effect to EUV reflectivity.
It was observed that DIO3 damaged the Ru capping layer and resulted in a significant EUV reflectivity drop. An alloyed
Ru-capping layer showed improved durability against DIO3 damage. The changes to the Ru-surface were characterized
with atomic force microscopy (AFM) and X-ray photo electron spectroscopy (XPS).
EUVL practical mask structure with light shield area for 32nm half pitch and beyond
Show abstract
The effect of mask structure with light shield area on the printability in EUV lithography was studied. When very
thin absorber on EUVL mask is used for ULSI application, it then becomes necessary to create EUV light shield area
on the mask in order to suppress possible leakage of EUV light from neighboring exposure shots. We proposed and
fabricated two types of masks with very thin absorber and light shield area structure. For both types of masks we
demonstrated high shield performances at light shield areas by employing a Small Field Exposure Tool (SFET).
Control of the sidewall angle of an absorber stack using the Faraday cage system for the change of pattern printability in EUVL
Show abstract
A patterned TaN substrate, which is candidate for a mask absorber in extreme ultra-violet lithography (EUVL), was
etched to have inclined sidewalls by using a Faraday cage system under the condition of a 2-step process that allowed the
high etch selectivity of TaN over the resist. The sidewall angle (SWA) of the patterned substrate, which was in the shape
of a parallelogram after etching, could be controlled by changing the slope of a substrate holder that was placed in the
Faraday cage. The performance of an EUV mask, which contained the TaN absorber of an oblique pattern over the
molybdenum/silicon multi-layer, was simulated for different cases of SWA. The results indicated that the optical
properties, such as the critical dimension (CD), an offset in the CD bias between horizontal and vertical patterns (H-V
bias), and a shift in the image position on the wafer, could be controlled by changing the SWA of the absorber stack. The
simulation result showed that the effect of the SWA on the optical properties became more significant at larger
thicknesses of the absorber and smaller sizes of the target CD. Nevertheless, the contrast of the aerial images was not
significantly decreased because the shadow effect caused by either sidewall of the patterned substrate cancelled with
each other.
EUV Mask Process Correction
Pattern placement correction due to bending in EUVL masks
Show abstract
Extreme Ultraviolet Lithography (EUVL) masks have residual stress induced by several thin films on low thermal
expansion material (LTEM) substrates. The stressed thin films finally result in convex out-of-plane displacement (OPD)
of several 100s of nm on the pattern side of the mask. Since EUVL masks are chucked on EUVL scanners differently
from on e-beam writer, the mask pattern placement errors (PPE) are necessary to be corrected for to reduce overlay
errors. In this paper, experimental results of pattern placement error correction using standard chrome on glass (COG)
plate will be discussed together with simulations. Excellent agreement with simple bending theory is obtained.
Suitability of the model to compensate for other EUVL-related PPEs due to mask non-flatness will be discussed.
EUV Mask Inspection I
Signal analysis for the actinic full-field EUVL mask blank inspection system
Show abstract
We have developed an actinic full-field inspection system to detect multilayer phase defect with dark field imaging. With
this system, programmed phase defects on a mask blank were observed. The system can detect phase defects caused by a
1.5 nm high and 60 nm wide protrusion on a multilayer surface. Background intensity and signal to background ratio
(SBR) of the observed defect images are analyzed with simulation. The background intensities were calculated with the
model that it is generated by light scattered from mask surface roughness. The result indicates that the larger outer NA
(numerical aperture) leads to an increase in the background intensity. In this correlation of NA with the background
intensity, the calculation and experimental results correspond well. The defect images were simulated using the point
spread function (PSF) of flare generated by mirror surface roughness employing Fourier technique. The SBRs of
simulated defect images corresponded well with the SBRs of the observed images. These results support the calculation
and simulation models are proper.
Benchmarking EUV mask inspection beyond 0.25 NA
Show abstract
The SEMATECH Berkeley Actinic Inspection Tool (AIT) is an EUV zoneplate microscope dedicated to photomask
research. Recent upgrades have given the AIT imaging system selectable numerical aperture values of 0.25, 0.30, and
0.35 (4 equivalent). The highest of which provides resolution beyond the current generation of EUV lithography research
tools, giving above 75% contrast for dense-line features with 100-nm half-pitch on the mask, and above 70% for
88-nm half-pitch. To improve the imaging system alignment, we used through-focus images of small contacts to extract
aberration magnitudes and compare with modeling. The astigmatism magnitude reached a low value of 0.08 waves
RMS. We present the results of performance benchmarking and repeatability tests including contrast, and line width
measurements.
EUV Mask Inspection II
The study of EUVL mask defect inspection technology for 32-nm half-pitch node device and beyond
Show abstract
In this paper, we will report on our experimental and simulation results on the impact of EUVL mask absorber
structure and of inspection system optics on mask defect detection sensitivity. We employed a commercial simulator
EM-Suite (Panoramic Technology, Inc.) which calculated rigorously using FDTD (Finite-difference time-domain)
method. By using various optical constants of absorber stacks, we calculated image contrasts and defect image signals as
obtained from the mask defect inspection system. We evaluated the image contrast and the capability of detecting
defects on the EUVL masks by using a new inspection tool made by NuFlare Technology, Inc. (NFT) and Advanced
Mask Inspection Technology, Inc. (AMiT). This tool is based on NPI-5000 which is the leading-edge photomask defect
inspection system using 199nm wavelength inspection optics. The programmed defect masks with LR-TaBN and LRTaSi
absorbers were used which had various sized opaque and clear extension defects on hp-160nm, hp-225nm, and hp-
325nm line and space patterns. According to the analysis, reflectivity of EUVL mask absorber structures and the
inspection optics have large influence on image contrast and defect sensitivity. It is very important to optimize absorber
structure and inspection optics for the development of EUVL mask inspection technology, and for the improvement of
performance of EUV lithographic systems.
An investigation of EUV lithography defectivity
Show abstract
We have used ASML's full field step-and-scan exposure tool for extreme ultraviolet lithography (EUVL), known as an
Alpha Demo Tool, to investigate one of the critical issues identified for EUVL, defectivity associated with EUV masks.
The main objective for this work was to investigate the infrastructure currently in place to examine defects on a EUV
reticle and identify their consequence in exposed resist. Unlike many previous investigations this work looks at
naturally occurring defects in a EUV exposed metal layer from a 45 nm node device. The EUV exposure was also
integrated into a standard process flow where the other layers were patterned using more conventional 193-nm
lithography techniques.
This presentation correlates reticle level defectivity to resulting wafer exposures. Defect inspection data from both the
28xx family of KLA-Tencor wafer inspection tool and Terascan reticle inspection tools are presented. Defect
populations were characterized with a KLA 5200 Review SEM. Observed defectivity modes were analyzed using both
conventional defect inspection methodology as well as advanced techniques in order to gain further insight. We find
good correlations between reticle level defects and the resulting wafer exposure defects.
EUV Mask Repair
Study of EUVL mask defect repair using FIB-GAE method
Show abstract
We evaluated a new FIB-GAE (Focused Ion Beam-Gas Assisted Etching) repairing process for the absorber defects on
EUVL mask. XeF2 gas and H2O gas were used as etching assist agent and etching stop agent respectively. The H2O gas
was used to oxidize Ta-nitride side-wall and to inactivate the remaining XeF2 gas after the completion of defect repair.
At the Photomask Japan 2008 we had reported that side-etching of Ta-nitride caused CD degradation in EUVL. In the
present paper we report on the performance of defect repair by FIB, and of printability using SFET (Small Field
Exposure Tool). The samples evaluated, were in form of bridge defects in hp225nm L/S pattern. The cross sectional
SEM images certified that the newly developed H2O gas process prevented side-etching damage to TaBN layer and
made the side-wall close to vertical. The printability also showed excellent results. There were no significant CD
changes in the defocus characterization of the defect repaired region. In its defect repair process, the FIB method showed
no signs of scan damage on Cr buffered EUV mask. The repair accuracy and the application to narrow pitched pattern
are also discussed.
Analysis of process margin in EUV mask repair with nano-machining
Show abstract
Reduced design rules demand higher sensitivity of inspection, and thus small defects which did not affect printability
before require repair now. The trend is expected to be similar in extreme ultraviolet lithography (EUVL) which is a
promising candidate for sub 32 nm node devices due to high printing resolution. The appropriate repair tool for the small
defects is a nanomachining system. An area which remains to be studied is the nano-machining system performance
regarding repair of the defects without causing multilayer damage. Currently, nanomachining Z-depth controllability is 3
nm while the Ru-capping layer is 2.5 nm thick in a Buffer-less Ru-capped EUV mask. For this report, new repair
processes are studied in conjunction with the machining behavior of the different EUVL mask layers. Repair applications
to achieve the Edge Placement(EP) and Z-depth controllability for an optimal printability process window are discussed.
Repair feasibility was determined using a EUV micro exposure tool (MET) and Actinic Imaging Tool (AIT) to evaluate
repairs the 30 nm and 40 nm nodes. Finally, we will report the process margin of the repair through Slitho-EUVTM
simulation by controlling side wall angle, Z-depth, and EP (Edge Placement) on the base of 3-dimensional experimental
result.
Ga implantation and interlayer mixing during FIB repair of EUV mask defects
Show abstract
EUV mask damage caused by Ga focused ion beam irradiation during the mask defect repair was studied. The
concentration of Ga atom implanted in the multilayer through the buffer layer and distributions of recoil atoms were
calculated by SRIM. The reflectivity of the multilayer was calculated from the Ga distribution below the capping layer
surface. To validate the calculation, Ga focused ion beam was irradiated on the buffer layer. The EUV reflectivity was
measured after the buffer layer etching process. The measured reflectivity change was considerably larger than the one
predicted from the absorption of light by the implanted Ga. The large reflectivity loss was primarily due to the absorption
of light by chromium silicide residue which was generated by the intermixing of the buffer and the capping layer. Both
lowering of the acceleration voltage and using thicker buffer layer were found to be effective in reducing this intermixing.
The reduction of the reflectivity loss by using thicker buffer layer was confirmed by our experiments. An aerial image of
patterns with etching residue formed by the intermixing was simulated. When the thickness of the intermixed layer
happened to be 8 nm and the size of the resulting residue was larger than 100 nm, then the impact of the estimated
absorption by the residue on the linewidth of 32 nm hp line pattern became more than 5 %.
Masks for Nano-Imprint Lithography
Defect inspection of imprinted 32 nm half pitch patterns
Show abstract
Step and Flash Imprint Lithography redefines nanoimprinting. This novel technique involves the field-by-field
deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask
is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this
filling step, the resist is crosslinked under UV radiation, and then the mask is removed leaving a patterned solid on the
substrate. Compatibility with existing CMOS processes requires a mask infrastructure in which resolution, inspection
and repair are all addressed. The purpose of this paper is to understand the limitations of inspection at half pitches of 32
nm and below.
A 32 nm programmed defect mask was fabricated. Patterns included in the mask consisted of an SRAM Metal 1
cell, dense lines, and dense arrays of pillars. Programmed defect sizes started at 4 nm and increased to 48 nm in
increments of 4 nm. Defects in both the mask and imprinted wafers were characterized scanning electron microscopy
and the measured defect areas were calculated. These defects were then inspected using a KLA-T eS35 electron beam
wafer inspection system. Defect sizes as small as 12 nm were detected, and detection limits were found to be a function
of defect type.
Evaluation of e-beam repair for nanoimprint templates
Show abstract
Two essential process steps of the template fabrication chain are inspection and repair. The widely introduced gas
assisted e-beam etching and deposition technique for mask repair offers crucial advantages, especially regarding the
resolution capability. We started the evaluation of a new e-beam repair test stand based on the Zeiss MeRiT technology
for UV-NIL template repair. For this purpose, templates with programmed defects of different shapes and sizes have
been designed and fabricated. The repair experiments were focused on the development of recipes for quartz etching and
deposition specifically tailored for NIL repair requirements Both, clear and opaque programmed defects have been
repaired and the results have been analyzed. After recipe optimization, templates with repaired programmed defects have
been imprinted on a Molecular Imprints Imprio 250 tool. By comparing template and imprint results we investigated the
repair capability.
Mask Business
Diamonds in the rough: key performance indicators for reticles and design sets
Show abstract
The discussion on reticle cost continues to raise questions by many in the semiconductor industry. The
diamond industry developed a method to judge and grade diamonds. [1, 11] The diamond-marketing tool of "The
4Cs of Diamonds" and other slogans help explain the multiple, complex variables that determine the value of a
particular stone. Understanding the critical factors of Carat, Clarity, Color, and Cut allows all customers to
choose a gem that matches their unique desires. I apply the same principles of "The 4Cs of Diamonds" to
develop an analogous method for rating and tracking reticle performance.
I introduced the first 3Cs of reticle manufacturing during my BACUS presentation panel at SPIE in February
2008. [2] To these first 3Cs (Capital, Complexity, and Content), I now add a fourth, Cycle time. I will look at
how our use of reticles changes by node and use "The 4Cs of Reticles" to develop the key performance
indicators (KPI) that will help our industry set standards for evaluating reticle technology.
Capital includes both cost and utilization. This includes tools, people, facilities, and support systems required
for building the most critical reticles. Tools have highest value in the first two years of use, and each new
technology node will likely increase the Capital cost of reticles.
New technologies, specifications, and materials drive Complexity for reticles, including smaller feature size,
increased optical proximity correction (OPC), and more levels at sub-wavelength. The large data files needed
to create finer features require the use of the newest tools for writing, inspection, and repair.
Content encompasses the customer's specifications and requirements, which the mask shop must meet. The
specifications are critical because they drive wafer yield. A clear increase of the number of masking levels has
occurred since the 90 nm node.
Cycle time starts when the design is finished and lasts until the mask house ships the reticle to the fab.
Depending on the level of Complexity, a reticle can take from as few as one, to more than forty, days to build.
By using the 4Cs, I can show how the reticle build has changed from the 90 nm technology node. I will begin
by delineating proposed KPIs for reticles.
Accelerated data communication of semiconductor design files
Show abstract
The new Flume data communication protocol takes a unique approach to addressing the effects of latency in long-distance
data transmission. In addition to managing the data itself through compression, delta processing and error
correction, Flume eliminates the impact of latency by transmitting a continuous stream of data without ever pausing
to wait for acknowledgements from the data receiver. Transmission times are accelerated by 5X - 100X and these
speedups continue at least linearly with added bandwidth. A second, optional mode of operation, transmits separate
pieces of the data to be transmitted to different locations which can then exchange data among themselves to recreate
the complete data at all sites.
Compute resource management and turn around time control in mask data prep
Show abstract
With each new process technology node chip designs increase in complexity and size, and mask data prep flows require
more compute resources to maintain the desired turn around time (TAT) at a low cost. Securing highly scalable
processing for each element of the flow - geometry processing, resolution enhancements and optical process correction,
verification and fracture - has been the focal point so far. The utilization for different flow elements depends on the
operation, the data hierarchy and the device type. This paper introduces a dynamic utilization driven compute resource
control system applied to large scale parallel computation environment. The paper will analyze performance metrics
TAT and throughput for a production system and discuss trade-offs of different parallelization approaches in data
processing regarding interaction with dynamic resource control. The study focuses on 65nm and 45nm designs.
SEM CD Metrology
International photomask linewidth comparison by NIST and PTB
Show abstract
In preparation of the international Nano1 linewidth comparison on photomasks between 9 national metrology institutes,
NIST and PTB have started a bilateral linewidth comparison in 2008, independent of and prior to the Nano1 comparison
in order to test the suitability of the mask standards and the general approach to be used for the Nano1 comparison. This
contribution describes the rationale of both comparisons, the design of the mask comparison standards to be used and the
measurement methods applied for traceable photomask linewidth metrology at NIST and PTB.
Re-calibration of the NIST SRM 2059 master standard using traceable atomic force microscope metrology
Show abstract
The current photomask linewidth Standard Reference Material (SRM) supplied by the National Institute of Standards
and Technology (NIST), SRM 2059, is the fifth generation of such standards for mask metrology. An in house optical
microscope tool developed at NIST, called the NIST ultra-violet (UV) microscope, was used in transmission mode to
calibrate the SRM 2059 photomasks. Due to the limitations of available optical models for determining the edge
response in the UV microscope, the tool was used in a comparator mode.
One of the masks was selected as a master standard - and the features on this mask were calibrated using traceable
critical dimension atomic force microscope (CD-AFM) dimensional metrology. The optical measurements were then
used to determine the relative offsets between the widths on the master standard and individual masks for sale to
customers. At the time of these measurements, however, the uncertainties in the CD-AFM reference metrology on the
master standard were larger than can now be achieved because the NIST single crystal critical dimension reference
material (SCCDRM) project had not been completed.
Using our CD-AFM at NIST, we have performed new measurements on the SRM 2059 master standard. The new AFM
results are in agreement with the prior measurements and have expanded uncertainties approximately one fourth of
those of the earlier results for sub-micrometer features. When the optical comparator data for customers masks are
reanalyzed using these new AFM results, we expect to reduce the combined reported uncertainties for the linewidths on
the actual SRMs by at least 40 % for the nominal 0.25 μm features.
A study of the limited area scanning system in the mask CD-SEM
Show abstract
Measurement of resist critical dimensions (CDs) utilizing a scanning electron microscope (SEM)
based metrology system causes the resist to change due to irradiation effects of the electrons. A new
and novel scanning approach has been developed in an effort to minimize the effects electron
irradiation and exposure during the measurement process. This technique is especially pertinent in
view of the tightening requirements for process control to achieve single digit CD uniformity on
leading edge photo masks being produced today. The measurement of OPC features necessitates
utilization of SEM based metrology due to resolution requirements, but the effects of high
magnification imaging presents unique challenges. By controlling the scanned region of interest
(ROI) it is possible to reduce exposure and irradiation effects. This paper will detail this new
approach as it is utilized on the LWM9045 SEM Metrology system. The LWM9000SEM mask CD
SEM was introduced earlier.
Exploring new metrology for complex photomask patterns
Show abstract
Photomask pattern sizes are usually defined by a one-dimensional Critical Dimension (CD). As mask pattern shapes
become more complex, a single CD no longer provides sufficient information to characterize the mask feature. For
simple square contacts, an area measurement is generally accepted as a better choice for determining contact uniformity.
However, the area metric may not adequately characterize complex shapes; it does not lend itself to CD metrology and it
ignores pattern placement. This paper investigates new ways of measuring complex mask shapes with aggressive Optical
Proximity Correction (OPC). An example of more informative metric is center of gravity. This new metric will be
compared to more traditional mask characterization variables like CD mean to target, CD uniformity, and Image
Placement (IP). Wafer simulations of the mask shapes will be used to understand which mask pattern metrics are most
representative of the image transferred to wafer images. The results will be discussed in terms of their potential to
improve mask quality for 32nm technology and beyond.
New method of 2-dimensional metrology using mask contouring
Show abstract
We have developed a new method of accurately profiling and measuring of a mask shape by utilizing a Mask
CD-SEM. The method is intended to realize high accuracy, stability and reproducibility of the Mask
CD-SEM adopting an edge detection algorithm as the key technology used in CD-SEM for high accuracy CD
measurement. In comparison with a conventional image processing method for contour profiling, this edge
detection method is possible to create the profiles with much higher accuracy which is comparable with
CD-SEM for semiconductor device CD measurement. This method realizes two-dimensional metrology for
refined pattern that had been difficult to measure conventionally by utilizing high precision contour profile.
In this report, we will introduce the algorithm in general, the experimental results and the application in
practice.
As shrinkage of design rule for semiconductor device has further advanced, an aggressive OPC (Optical
Proximity Correction) is indispensable in RET (Resolution Enhancement Technology). From the view point
of DFM (Design for Manufacturability), a dramatic increase of data processing cost for advanced MDP
(Mask Data Preparation) for instance and surge of mask making cost have become a big concern to the device
manufacturers. This is to say, demands for quality is becoming strenuous because of enormous quantity of
data growth with increasing of refined pattern on photo mask manufacture. In the result, massive amount of
simulated error occurs on mask inspection that causes lengthening of mask production and inspection period,
cost increasing, and long delivery time. In a sense, it is a trade-off between the high accuracy RET and the
mask production cost, while it gives a significant impact on the semiconductor market centered around the
mask business.
To cope with the problem, we propose the best method of a DFM solution using two-dimensional
metrology for refined pattern.
Advanced CD Metrology
Comparative scatterometric CD measurements on a MoSi photo mask using different metrology tools
Show abstract
The demands on CD metrology techniques in terms of both reproducibility and measurement uncertainty
increase with decreasing critical dimensions (CD) on lithography masks. Additionally a full 3D characterization
of the mask structures becomes more and more important to understand and control the printing behavior of state
of the art photomasks. Furthermore, an extension of metrology characterization including material properties can
provide the final puzzle pieces for a better correlation of mask metrology to wafer metrology. Here, optical
metrology systems, especially at-wavelength systems, are very well suited to characterize structure features of a
photomask regarding their printing behavior on a wafer. In particular scatterometry is able to provide a better
understanding of the investigated structure and allows for modeling of secondary structure parameters as well as
material composition.
AMTC has a commercial scatterometer from n&k Technology (n&k 5700-CDRT) in use. This system measures
the spectral transmission and reflection, the 0th diffraction order. Beside thin film characterization this system is
used for CD and edge profile characterization, also. The analysis of the data uses a look-up table approach in
combination with a database, which has been generated and can be expanded, respectively, using a RCWA
based software. At PTB we have realized a new DUV hybrid scatterometer which combines essential elements
of a radiometer, an ellipsometer, and a diffractometer.
These two systems are different both in terms of the measurement modes, the data evaluation method and the
Maxwell-solver used. Therefore we started to compare the performance of both systems to traditional metrology
system for CD metrology and phase measurement. For this purpose we performed first comparative
scatterometric measurements on a MoSi phase shifting mask.
Mask process monitoring with optical CD measurements for sub-50-nm
Show abstract
Process control of line width and etch depth on the photomask production is more important as the industry moves
toward 50nm node and beyond. In this paper, we report the ellipsometer-based scatterometry based metrology system
that provides line width and resist thickness measurements on sub 50 nm node test masks for a mask process monitoring.
Measurements were made with spectroscopic rotating compensator ellipsometer system. For analysis we made up
modeling libraries with a 200 nm half pitch and checked and applied them to ADI and ACI measurements of binary and
phase shift mask (PSM). We characterized the CD uniformity, linearity, thickness uniformity. Results show that linearity
measured from fixed-pitch, varying line/space ratio targets show good correlation to top-down CD-SEM with R2 of more
than 0.99. Resist thickness results show that depth bias is about 2nm between AFM and OCD in ADI step. The data
show that optical CD measurements provide a nondestructive way to monitor mask processes with relatively little time
loss from measurement step.
Improvement in metrology on new 3D-AFM platform
Show abstract
According to the 2007 edition of the ITRS roadmap, the requirement for CD uniformity of isolated lines on a binary or
attenuated phase shift mask is 2.1nm (3σ) in 2008 and requires improvement to1.3 nm (3σ) in 2010. In order to meet the
increasing demand for CD uniformity on photo masks, improved CD metrology is required. A next generation AFM,
InSightTM 3DAFM, has been developed to meet these increased requirements for advanced photo mask metrology. The
new system achieves 2X improvement in CD and depth precision on advanced photo masks features over the previous
generation 3D-AFM. This paper provides measurement data including depth, CD, and sidewall angle metrology. In
addition the unique capabilities of damage-free defect inspection and Nanoimprint characterization by 3D AFM are
presented.
Metrology for Placement and Optical Structure
Development of a 1.5D reference comparator for position and straightness metrology on photomasks
Show abstract
The so-called Nanometer Comparator is the PTB vacuum length comparator which has been developed for high precision
length metrology on measurement objects with micro- and nanostructured graduations, like e.g. line scales, incremental
encoders or photomasks. The Nanometer Comparator allows to achieve smallest measurement uncertainties in the
nm-range by use of vacuum laser interferometry for the displacement measurement. We will report on the achieved
measurement performance of this high precision vacuum length comparator and the already started developments to substantially
enhance its measurement capabilities by additional straightness measurement capabilities. The enhanced
Nanometer Comparator will provide traceability for photomask pattern placement measurements in industry, also facing
the challenges due to the increased requirements on registration metrology as set by the introduction of new lithography
techniques like double patterning methods.
Photomask registration and overlay metrology by means of 193 nm optics
Gerd Klose,
Norbert Kerwien,
Michael Arnz,
et al.
Show abstract
This paper reports on the current status of PROVETM - a new photomask registration and overlay metrology system
currently under development at Carl Zeiss. The scope of the project is to design and build a photomask pattern
placement metrology tool which is serving the 32 nm node. Performance specifications of the tool are actually driven by
double exposure/ double patterning approaches which will help to extend the 193 nm lithography platforms, while
keeping the semiconductor industry conform to ITRS roadmap requirements. A secondary requirement of pattern
placement metrology tools is the CD measurement option for design features of interest. Combining both registration
and CD measurement reduces the number of process operations a photomask has to encounter during manufacture.
Optical design considerations are discussed, which led to the tool being designed for 193 nm illumination corresponding
to at-wavelength metrology for most current and future photomask applications. The concept enables registration and
CD metrology by transmitted or reflected light. The short wavelength together with a NA of 0.6 also provides sufficient
resolution even at working distances compatible with the use of pellicles, hence enabling the tool for qualification of
final, production ready masks. Imaging simulations with a rigorous Maxwell solver prove our chosen optical concept to
be adequate for the various mask types (e.g. COG, MoSi, EUV) commonly used today and presumably in the future.
The open concept does enable a higher NA for future, pellicle free applications.
World wide matching of registration metrology tools of various generations
Show abstract
Turn around time/cycle time is a key success criterion in the semiconductor photomask business. Therefore, global mask
suppliers typically allocate work loads based on fab capability and utilization capacity. From a logistical point of view,
the manufacturing location of a photomask should be transparent to the customer (mask user).
Matching capability of production equipment and especially metrology tools is considered a key enabler to guarantee
cross site manufacturing flexibility. Toppan, with manufacturing sites in eight countries worldwide, has an on-going
program to match the registration metrology systems of all its production sites. This allows for manufacturing flexibility
and risk mitigation.In cooperation with Vistec Semiconductor Systems, Toppan has recently completed a program to
match the Vistec LMS IPRO systems at all production sites worldwide. Vistec has developed a new software feature
which allows for significantly improved matching of LMS IPRO(x) registration metrology tools of various generations.
We will report on the results of the global matching campaign of several of the leading Toppan sites.
Spectroscopic ellipsometry applications in photomask technology
Show abstract
Development and manufacture of advanced photomasks requires understanding the optical properties of mask
materials and the ability to carefully monitor and control the film thickness, refractive index, and absorption of each film
layer. Spectroscopic Ellipsometry (SE), a nondestructive optical analysis technique for determination of film thickness,
refractive index, absorption, and film microstructure has been applied to many applications in current and emerging
areas of photomask technology.
This work surveys a variety of applications including analysis of fused silica mask blanks, imprint lithography
templates, free-standing pellicles, deposited films of chromium, chromium oxide, MoSi, and multiple layers of these
materials.
For fused silica substrates we determine the optical properties (n & k) versus wavelength as well as the surface
roughness. The near-surface index and surface roughness are used as indicators of surface polishing quality, which is an
issue in the use of photomask substrates as template stamps in imprint lithography.
Pellicles are free-standing films stretched over a metal frame. Because these thin pellicles are much thinner
than the light coherence length, spectroscopic ellipsometry can determine the thickness, refractive index, and absorbance
of the pellicle versus wavelength via interference between light reflecting from the upper and lower surfaces of the film.
It is also possible to measure pellicles suspended over an underlying mask.
The optical constants (n & k) of MoSi films vary widely with deposition conditions due to both composition
and microstructure. Films optimized for 248 nm and 193 nm wavelengths have been analyzed. Spectroscopic
ellipsometry shows good sensitivity to surface roughness and index gradients through the MoSi films.
Multilayer masks such as NTAR have multiple absorbing layers such as chromium and chrome oxide. It is
possible to simultaneously analyze multiple data sets acquired from the front side, from the back side through the
substrate, and transmitted data through the stack. This increases the information content in the data, allowing more
details from the multilayer to be determined.
It is also possible to measure the birefringence in mask substrates and coated masks by using ellipsometry in
transmission mode. By establishing a known polarization state incident on the mask it is possible to analyze the
polarization after transmission to determine the phase difference, which is used to measure the birefringence of the
sample.
For patterned structures such as gratings it is possible to measure polarization-dependent diffraction effects
versus angle. Measurement can be made in either reflection or transmission mode. It is possible to independently
measure both s- and p-polarization components and compare to theory.
As photomasks become more complex, with increasing numbers of layers (such as multilayer mirrors for EUV
masks) in-situ ellipsometry shows great promise, providing the ultimate characterization of each film by allowing
measurement in real-time as each layer is added to the mask structure.
Poster Session: Mask Business
True reticle cost saving by multi level reticle approach
Show abstract
Today reticle costs become one of the main contributors in the cost of manufacturing of advanced logic products.
Especially for low volume projects as of product sampling as well as design and product verifications the saving of
reticle costs becomes worthwhile. Multi level reticles are the combination of more then one lithographical layer on one
physical reticle. Due to this approach the physical amount of reticles per tape out will be reduced and thereby also the
costs for reticles will be significantly decreased. The multi level reticle approach is implemented as standard option in
the INFINEON Technologies tape out flow for advanced logic products. This means dependent on forecasted volume
and chip size it could be decided to tape out a project on multi level- or single level reticle. Technical setup, reticle
layout, specification, CAD flow and experience in daily work using multi level reticles in different design nodes will be
shown. Reticle cost advantage versus reduced throughput will be discussed.
Technology interactions on reticle delivery
Show abstract
Reticle cost and cycle time to deliver new circuit designs to a wafer fab remain key focus areas for advanced
semiconductor manufacturing and new product development. Resolution enhancement techniques like optical proximity
correction as applied to critical layers have increased the burden on mask data preparation and reticle writing steps of the
mask making flow. The growing data volume and complexity of designs must be reduced to a perfect image on a reticle
in the shortest time possible against computer and machine constraints. Continued dependence on 193 nm wavelength
exposure in extremely low k1 lithography exacerbates the underlying trends.
Two important factors come together to drive the economics and performance of the reticle line: the complexity of the
designs and the productivity of e-beam writing tools. The designs, OPC methods, and writing tool capabilities continue
to evolve with each node of technology. The study builds on prior evaluations to look at fundamental pattern complexity
across 90nm, 65nm, and 45nm logic designs using the gate and metal-1 critical layers. The writing tool throughput
testing uses a range of standard patterns to establish shot limited performance as a calibration method for arbitrary
designs.
Node to node design and tool to tool generation comparisons highlight actual step changes in complexity and capability
by introducing new quantitative methods, benchmarking metrics, and testing strategies. The findings are projected into
the future using design complexity and writing tool trends to suggest implications about reticle cost, cycle time, or
possible gaps in technology development.
Poster Session: Advanced Mask Patterning
Deflection unit for multi-beam mask making
Show abstract
Two main challenges of future mask making are the decreasing throughput of the pattern generators and the insufficient
line edge roughness of the resist structures. The increasing design complexity with smaller feature sizes combined with
additional pattern elements of the Optical Proximity Correction generates huge data volumes which reduce
correspondingly the throughput of conventional single e-beam pattern generators. On the other hand the achievable line
edge roughness when using sensitive chemically amplified resists does not fulfill the future requirements. The
application of less sensitive resists may provide an improved roughness, however on account of throughput, as well. To
overcome this challenge a proton multi-beam pattern generator is developed [1]. Starting with a highly parallel broad
beam, an aperture-plate is used to generate thousands of separate spot beams. These beams pass through a blanking-plate
unit, based on a CMOS device for de-multiplexing the writing data and equipped with electrodes placed around the
apertures switching the beams "on" or "off", dependent on the desired pattern. The beam array is demagnified by a 200x
reduction optics and the exposure of the entire substrate is done by a continuous moving stage.
One major challenge is the fabrication of the required high aspect deflection electrodes and their connection to the
CMOS device. One approach is to combine a post-processed CMOS chip with a MEMS component containing the
deflection electrodes and to realize the electrical connection of both by vertical integration techniques. For the evaluation
and assessment of this considered scheme and fabrication technique, a proof-of-concept deflection unit has been realized
and tested. Our design is based on the generation of the deflection electrodes in a silicon membrane by etching trenches
and oxide filling afterwards. In a 5mm x 5mm area 43,000 apertures with the corresponding electrodes have been
structured and wired individually or in groups with aluminum lines. The aperture-plate for shaping the beams has been
aligned and mounted on top of the blanking-plate. Afterwards this sandwich has been fixed on a base-plate with a pin
plug as interface. The electrical connection has been performed with a standard chip bonding process to the aluminum
pads on the blanking-plate. Finally, the proof-of-concept deflection unit was evaluated in a test bench. The results of
electrical- and exposure tests are presented and discussed in detail.
Mask patterning for the 22nm node using a proton multi-beam projection pattern generator
Show abstract
Decreasing throughput of high-end pattern generators and insufficient line edge roughness (LER) of chemically
amplified resists (CAR) might become limitations for future mask making. An alternative could be the introduction of
less sensitive resists, linked to a turning away from today's electron beam pattern generators. Moderate exposure doses
of around 25μC/cm2 could be achieved for non-CAR materials like HSQ by the use of 10keV protons. Targeting
optimized absorber performance, Shin-Etsu has developed an Opaque-molybdenum-over-glass (OMOG) material,
designed for 32mn mask technology and beyond. This hard mask concept allows using thin resist layers, as required by
an ion beam exposure. Goal of this work was to assess a HSQ based non-CAR process using a multiple ion beam pattern
generator including subsequent transfer into the absorber by dry etch processes. Proton exposures have been done on the
IMS Nanofabrication proof of concept tool which is designed for 40,000 programmable ion beams. For comparison, an
electron based reference process has been set up in parallel to the proton multi-beam approach. Hard mask opening and
subsequent absorber etching have been accomplished in a state of the art mask etcher. Assessment of the process flow
has been done in terms of feature profile, LER and resolution capability.
High accuracy jog CD control on OPC pattern by advanced laser writer Sigma7500
Show abstract
With the progress of mask writer technology, 50 KV electron beam writers always perform with better pattern fidelity
and critical dimension (CD) control than traditional laser raster-scan writers because laser spot size is confined by the
laser longer wavelength relative to electron beam. As far as Optical Proximity Correction (OPC) pattern fidelity is
concerned, critical masks with OPC process have to choose Variable-Shape-Beam (VSB) electron beam writer presently.
However, the over-aggressive OPC fragmentation induces data volume abrupt explosion, longer writing time, higher
mask cost and even mask quality degradation 1.
Micronic Sigma7500 laser writer introduces a novel imaging system combining partial coherent light and DUV spatial
light modulation (SLM) to generate a high-quality pattern image 2. The benefit of raster-scan laser writer is high
throughput with consistent writing time regardless of pattern geometry, complexity and data size. However, pattern CD
accuracy still needs improvement. This study is to evaluate jog CD control capability of Sigma7500 on OPC typical
line-and-space test patterns with different orientations of 0°, 90°, 45° and 135°. In addition, mask CD uniformity and
OPC jog height linearity will also be demonstrated.
Poster Session: Advanced Mask Processing and Materials
70nm DRAM intra-field CDU improvement by dose modulation on mask transmittance
Show abstract
DRAM intra-field CD uniformity (CDU) demand becomes more crucial with pattern size shrink and wafer die or
memory size expanding. Intra-field CDU error mainly comes from mask CD error, scanner exposure and wafer process.
This study makes use of a method to extract systematic CDU error from multi-field CDU results. Based on the
information of the systematic CDU error, localized mask transmittance modulation is implemented to compensate the
intra-field systematic CDU error on wafer. A focused ultrafast laser beam forms shading elements in mask quartz
substrate. Mask transmittance modulation is controlled by the shading element density variation. This study will
demonstrate the intra-field CDU improvement result, CD modulation calibration validity, CD proximity variation result
and mask inspection result etc.
The study of CD behavior due to transmission control position change within photomask substrate
Show abstract
As design rule of memory device is smaller and smaller, the CD uniformity of a photomask become the most
important factor to satisfy wafer exposure performance. Once the photomask is made, CD uniformity of the mask
can't be changed and if CD uniformity of the mask is not good to use for wafer exposure, we must reject it and
make another one again. But, after applying transmission control tool for CD uniformity, we have an extra chance
to control mask CD uniformity in one mask and this is very effective for wafer printing result.
In this paper, we are going to evaluate the behavior of wafer CD due to transmission control position change
within photomask substrate and find the optimum control position for better wafer result.
Effects of photo resist erosion in development on critical dimension performance for 45nm node and below
Show abstract
In previous study, it has been reported that photo resist erosion after development gets severe as patterns size decreases.
The 60nm feature requiring for SRAF(Sub Resolution Assistant Feature) of 45nm technology node, the photo resist
erosion after develop on unexposed area was almost 400Å. It will be a serious problem to degrade not only the resist
thickness margin for thinner resist to enhance resolution and pattern collapse, but also CD(Critical Dimension)
performance capability such as CD linearity and SRAF resolution capability by proceeding dry etching.
In this paper, the effects of photo resist erosion by pattern size on CD linearity performance were studied. The photo
resist erosion by pattern size was simulated with the Gaussian blur model before dry etching. The effects of dosage,
PEB(Post Exposure Bake) temperature and development conditions were evaluated to reduce blur value before dry
etching.
Poster Session: Metrology
Novel CD measurement and precise pattern size extraction method for optical images
Show abstract
A new method for accurate CD measurement and precise pattern size extraction from optical images is proposed. The
approach is based on the underlying field theory of optical image generation. The method demonstrates superior
precision compared with traditional edge detection schemes based on the image and not on the field nature of image
creation. The proposed method presents accuracy parallel to that achieved by SEM imaging. Therefore it provides an
alternative to electronic microscopy measurements in certain cases. This new method may be implemented for
applications of accurate mask-CD measurement, as well as for retrieving the mask model from an optical image for a die
to model application.
Poster Session: Inspection and Repair
A novel approach to mask defect inspection
Show abstract
Memory chips, now constituting a major part of semiconductor market, posit a special challenge for
inspection, as they are generally produced with the smallest half-pitch available with today's
technology. This is true, in particular, to photomasks of advanced memory devices, which are at the
forefront of the "low-k1" regime. In this paper we present a novel photomask inspection approach,
that is particularly suitable for low-k1 layers of advanced memory chips, owing to their typical dense
and periodic structure. The method we present can produce a very strong signal for small mask
defects, by suppression of the modulation of the pattern's image. Unlike dark-field detection,
however, here a single diffraction order associated with the pattern generates a constant "gray"
background image, that is used for signal enhancement. We define the theoretical basis for the new
detection technique, and show, both analytically and numerically, that it can easily achieve a
detection line past the printability spec, and that in cases it is at least as sensitive as high-resolution
based detection. We also demonstrate this claim experimentally on a customer mask, using the
platform of Applied Material's newly released Aera2TM mask inspection tool. The high sensitivity
demonstrates the important and often overlooked concept that resolution is not synonymous with
sensitivity. The novel detection method is advantageous in several other aspects, such as the very
simple implementation, the high throughput, and the relatively simple pre- and post-processing
algorithms required for signal extraction. These features, and in particular the very high sensitivity,
make this novel detection method an attractive inspection option for advanced memory devices.
Automated reticle inspection data analysis for wafer fabs
Show abstract
To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection
system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced
operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or
fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer
defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer
basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a
very tedious and time-consuming task and may cause extended manufacturing line-down situations.
Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports
to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation
errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be
spent working on other more productive activities.
This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a
format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical
charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or
entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle
defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing
reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.
Results from the KLA-Tencor TeraScanXR reticle inspection tool
Show abstract
The new TeraScanXR reticle inspection system extends the capability of the previous TeraScanHR platform to advanced
32nm logic and 40nm Half Pitch (HP) memory technology nodes. The TeraScanXR has been designed to provide a
significant improvement in image quality, defect sensitivity and throughput relative to the HR platform. Defect
sensitivity is increased via a combination of improved Die-to-Die (D:D) and Die-to-Database (D:DB) algorithms, as well
as enhancements to the image auto-focus (IAF). Modifications to system optics and the introduction of a more powerful
image processing computer have enabled a ~2X faster inspection mode. In this paper, we describe the key features of the
TeraScanXR platform and present preliminary data that illustrate the capability of this tool. TeraScanHR tools currently
at customer sites are field-upgradeable to the TeraScanXR configuration.
Layout driven DNIR
Show abstract
With the shrinking of devices, aggressive OPC is becoming imperative. Generally, OPC must be kept within photomask
manufacturing limits, but at process and OPC development stages, patterns exceeding photomask manufacturing and
inspection limits are often included. To resolve this issue, MRC (Mask Rule Checking) is executed as a method to verify
patterns exceeding photomask manufacturing and inspection limits. Two options are available in MRC to solve errors:
(1) repair layout (or OPC) of corresponding areas; or (2) manufacture photomask including corresponding areas but with
no inspection. Option (1) is generally extremely time-consuming, and if lithographically feasible, (2) would be selected.
However, if detected error flags become massive, it is nearly beyond human control to take care of configurations of
DNIR(Do Not Inspect Region). In addition, massive amounts of DNIR will augment inspection tool setup time almost
factorial. Further, inspection tools have limitations in DNIR setup method, and DNIR settings that do not meet criteria
will be considered as setting violations. Therefore, we developed TLDD (Toppan Layout Driven DNIRs), a tool that
automatically generates DNIR based on detected by MRC. This tool has the following features: (1) applies limitations to
the number of DNIRs; (2) follows DNIR limitations of inspection tools; and (3) follows both (1) and (2) upon which
DNIR area is minimized as much as possible. By utilizing this tool, difficult-to-inspect regions can be automatically set
as DNIR independent of DNIR rules of inspection tools or individual operator skills, while enabling inspection of
important areas at high sensitivity.
Improving cost of ownership on KLA-Tencor wafer fab reticle inspections by implementing pixel migration via new STARlight2+ capability
Show abstract
In the ever-changing semiconductor industry, wafer fabs and mask shops alike are adding low
cost of ownership (CoO) to the list of requirements for inspections tools. KLA-Tencor has
developed and introduced STARlight2+ (SL2+) to satisfy this need. This new software
algorithm is available on all TeraScanHR and TeraFab models. KLA-Tencor has cooperated
with United Microelectronics Corporation (UMC) to demonstrate and improve SL2+, including
its ability to lower CoO, on 65nm and below photomasks.
These improvements are built on the rich history of STARlight. Over the years, STARlight has
become one of the industry standards for reticle inspection. Like its predecessors, SL2+ uses
only transmitted and reflected light images from a reticle to identify defects on the reticle. These
images along with plate-specific information are then processed by SL2+ to generate reference
images of how the patterns on the reticle should appear. These reference images are then
compared with the initial optical images to identify the defects.
The new and improved SL2+ generates more accurate reference images. These images reduce
background noise and increase the usable sensitivity. With the results from controlled
engineering tests, a fab or mask shop can then decide to inspect reticles at a given technology
node with a large pixel; this is sometimes referred to as pixel migration. The larger pixel with
SL2+ can then perform the inspections at similar sensitivity settings and higher throughput, thus
lowering CoO.
Poster Session: Contamination Control and Cleaning
An effective haze monitoring method
Show abstract
Monitoring and controlling of haze defect is becoming important more than ever before [1]. Regular and frequent mask
inspection is expected to reduce the risk of defect print on wafer [2]. However, such frequent inspection requires longer
inspection time and additional cost, which should lead to worsening of productivity.
It is known that haze defect grows from non-killer defect at its infant stage to killer defect as time advances. And such
haze growth process is dependent on the haze size in its infant stage, location of haze generation and such. If the haze
inspection procedure were customized in a most suited way to optimally monitor the growth characteristics of haze, the
inspection throughput would become higher without sacrificing the performance and reliability of mask inspection itself.
For such a purpose, we have studied an effective haze monitoring method that ensures both sensitivity and throughput
high enough. We will show that a variable scan method using a DUV mask inspection tool is quite effective in cutting
down inspection time and cost.
Results of new mask contamination inspection capability STARlight2+ 72nm pixel with cell-to-cell HiRes5 for qualifying memory masks in wafer fabs
Show abstract
As the industry embarks on sub 50nm half pitch design nodes, higher resolution and advanced
photomask inspection algorithm are needed to resolve shrinking features and find critical yield limiting
defects. In this paper, we evaluate the detection capability of STARlight2+ 72nm pixel on sub-50nm
memory masks.
The mask sets targeted for this evaluation were focused on critical layers. Although memory mask
sets are dominated by multi-die layout, single die layout masks were also inspected because of their
significance during research and development. Inspection results demonstrated the performance of
STARlight2+ based on its sensitivity to contamination defects and the inspectability of masks with this
detection method. The most common plan of record for mask inspection in a wafer fab is die-to-die
transmitted pattern inspection modes, which limits the inspection area to the die region only and cannot be
used for single-die reticle inspections. However, STARlight2+ has single die inspection capability, which
is also needed in order to inspect scribe-lines and frame areas.
The primary defects of interest are photo induced crystal defects or haze. Haze continues to be the
primary reason for mask returns at 193nm exposure across the industry. The objective of this paper is to
demonstrate STARlight2+ 72nm capability to support memory wafer fab mask qualification requirements.
SL2+: H5 use case
Show abstract
Photomask contamination inspections, whether performed at maskshops as an outgoing
inspection or at wafer fabs for incoming shipping and handling or progressive defect monitoring,
have been performed by KLA-Tencor STARlight systems for a number of design nodes.
STARlight has evolved since it first appeared on the 3xx generation of KLA-Tencor mask
inspection tools. It was improved with the TeraStar (also known as SLF) based tools with the
SL1 algorithm. SL2 first appeared on the TeraScan systems (also known as 5xx) and has been
widely adopted in both mask shops and wafer fabs.
Design rules continue to advance as do inspection challenges. Advances in computer processing
power have enabled more complex and powerful algorithms to be developed and applied to the
STARlight technology. The current generation of STARlight, which is known as SL2+,
implements improved modeling fidelity as well as a completely new paradigm to the existing
STARlight technology known as HiRes5, or simply "H5". H5 is integrated seamlessly within
SL2+ and provides die-to-die-like performance in both transmitted and reflected light, in addition
to the STARlight detection, in unit time. It achieves this by automatically identifying repeating
structures in both X and Y directions and applying image alignment and difference threshold.
A leading mask shop partnered with KLA-Tencor in order to evaluate SL2+ at its facility. SL2+
demonstrated a high level of sensitivity on all test reticles, with good inspectability on advanced
production reticles. High sensitivity settings were used for 45 nm HP and smaller design rule
masks and low false detections were achieved. H5 provided additional sensitivity on production
plates, demonstrating the ability to extend the use of SL2+ to cover 32 nm DR plate inspections.
This paper reports the findings and results of this evaluation.
Poster Session: EUV Mask Processing and Substrates
Evaluation of backside particle contamination and electrostatic chuck design on the cleanliness of EUV reticle mask blanks in a multilayer Mo/Si ion beam deposition system
Show abstract
A key requirement for the success of EUV lithography is a high volume supply of defect-free Mo/Si multilayer (ML)-
coated mask blanks. The process of fabricating mask blanks is particularly sensitive to particle contamination because
decoration by the deposition of the reflective stack on sub-lithographic (< 22 nm) particles can create larger, printable
defects.
One possible source of added defects is the mask substrate fixturing method, which, in the Veeco ion beam deposition
(IBD) system used to deposit our ML coatings, must allow tilt and rotation of a vertically oriented substrate. As
commonly practiced, an electrostatic chuck (ESC) is used instead of a mechanical clamping fixture to avoid transferring
particles to the front surface of the mask by mechanical clamping and declamping operations. However, a large number
of particles can be introduced to the backside of the mask by electrostatic clamping. Up to now, there has been little
concern about such backside particles, except for relatively large particles (> 1 micron) that may affect out-of-plane
distortion of the mask in an EUV lithography tool. As the cleanliness of the EUV masks and mask blank fabrication
approaches perfection, however, there is more concern that particles transferred from the backside to the frontside of the
mask may be a significant issue. Such transfer may occur in the deposition chamber, in the substrate cassette, or in the
transfer module and may be indirect.
In this paper, we present data from characterizing the amount, size, shape, composition, and location of the backside
particle defects generated by electrostatic clamping, using a particle counter and scanning electron microscope (SEM),
and compare results for a pin-type e-chuck, which has a small contact area, with the standard flat e-chuck. The key
result is a 10X to 30X reduction in the total number of backside particles for the pin chuck. Also, preliminary data
indicates that the pin chuck stays cleaner under service conditions than the flat chuck. The exact elemental composition
of the defects is sensitive to the clamping method and type of backside Cr coating. In general, for the flat chuck, Al
defects, attributed to particles from the alumina chuck surface, are dominant. For the pin chuck, Si,Cr,N,O defects from
the mask surface are mainly observed.
Poster Session: Nano-Imprint
UV NIL template making and imprint evaluation
Show abstract
UV NIL shows excellent resolution capability with remarkable low line edge roughness, and has been attracting
pioneers in the industry who were searching for the finest patterns.
We have been focused on the resolution improvement in NIL template making with a 100keV acceleration voltage
spot beam EB writer process, and have established a template making process to meet the requirements of the pioneers.
Usually such templates needed just a small field (several hundred microns square or so).
Now, for several semiconductor devices, the UV NIL is considered not only as a patterning solution for R&D
purpose but eventually as a potential candidate for production, and instead of a small field, a full chip field mask is
required. Although the 100kV EB writers have excellent resolution capability, they are adopting spot beams (SB) to
generate the pattern and have a fatally low throughput if we need full chip writing.
In this paper, we are focusing on the 50keV variable shaped beam (VSB) EB writers, which are used in current 4X
photomask manufacturing. The 50keV VSB writers can generate full chip pattern in a reasonable time, and by choosing
the right patterning material and process, we achieved resolution down to 28nm.
Development status of back-end process for UV-NIL template fabrication
Show abstract
Nano-imprint lithography (NIL) is eminently suitable for low cost patterning for nanostructures. As feature
sizes of the UV-NIL templates are the same as the wafer patterns, there are enormous challenges such as writing and
inspecting smaller patterns for NIL template fabrication. In our previous works, we achieved less than 16nm resolution
with a 100keV spot beam writer and non CAR. We also reported optimization of metrology for NIL templates and the
characterization of anti-sticking layers with scanning probe microscopies.
Normally the template is made from a 6025 photomask blank. After the blank undergoes a process similar to
the photomask process, it is diced into 65 mm x 65 mm size and four pieces, and then each piece is polished into its final
shape. Therefore it becomes difficult to inspect and clean them, because 65 mm substrates are unfamiliar in photomask
industry. In order to reach the step for mass-production of the templates, the development of "back-end process", which
includes not only cleaning and inspection but also repair, dicing, polishing, and coating anti-sticking layers, is essential.
Especially keeping low contamination level during dicing and polishing processes is one of the critical issues.
In this paper, we report our development status of "back-end process" for NIL templates. Especially, we focus
on the techniques of reducing adder defects during dicing process and improving cleaning capability.
Poster Session: DFM
Non-uniform yield optimization for integrated circuit layout considering global interactions
Show abstract
In a previous work we have shown a yield optimization metric and a technique that considers the effects of several
types of yield enhancement methods for a given layout. Those findings suggested that it is important to consider two
types of yield tradeoffs, local tradeoffs where addressing one yield loss mechanism degrades others in the immediate
vicinity of the correction (local optimization window), and global tradeoffs where the net effect of the correction can be
fully accounted only when considering neighboring optimization windows. Such conclusion was derived from the fact
that the locally optimized layouts did not completely realize the theoretically optimal yield, which was obtained from
the assumption that global tradeoffs could be fully resolved. This work focuses in the contribution that such global
tradeoffs have on the final yield score when accounted properly during the optimization.
While the previous work focused only in selecting the corrections that locally improved the yield score1, this work
evaluates the global interactions before and after a change, and the correction is only accepted if it improves the global
score. While the global optimization requires a more expensive computational process, the intention of this work is to
determine how close the optimal layout can be from its theoretical limit. Since the optimization is performed and
evaluated under four different types of processes in which the failure mechanisms vary in relative importance, it is
possible to derive conclusions as to the need of considering global effects when trading off runtime requirements with
quality of the correction.
Fast and simple modeling of non-rectangular transistors
Show abstract
As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability are
emerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactured
despite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregular
gates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangular
geometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed and
smoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methods
either model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; or
they are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simple
solution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of the
equivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulation
experiments, we demonstrate that our model can accurately capture both on and off currents of the modeled nonrectangular
gate device. The average error of our modeling approach is 1.6% for Ion and 7.5% for Ioff.
Study of influence to transistor properties on the change of OPC pattern
Show abstract
Slight change of OPC pattern shape may influence transistor characteristics. So inputting the result of Litho-
Simulation, Contour, to SPICE-simulator, we investigated the change of the transistor characteristic. First of all, we
investigated the sensitivity of the transistor characteristics to OPC pattern change. We found that the difference of shape
with Isolated, Dense pattern, and a different OPC tool caused difference after SPICE-simulation. In this investigation, we
report focusing on the transient and DC analysis of transistor characteristics. Contour data was measured and averaged
before input to SPICE and a change of transistor characteristic was able to be detected. We came to the conclusion that
this investigation method is effective to check the influence of the transistor characteristics due to OPC pattern change.
And we can adopt this method as one technique for deciding the applicability of the OPC tool and its upgrade, which
were issues for MASK data processing.
Mask data prioritization based on design intent
Show abstract
MaskD2I and STARC have been working together to build efficient data flow based on the information transition from the
design to the manufacturing level. By converting design level information called as "Design Intent" to the priority
information of mask manufacturing data called as "Mask Data Rank (MDR)", MDP or manufacturing process based on the
importance of reticle patterns is possible. Our main purpose is to build a novel data flow with the priority information of
mask patterns extracted from the design intent.
In EMCL2008, we introduced the idea of MDR and showed its potential effectiveness. Then we addressed an additional
idea called DIF(Design Intent File) instead of RAF (Rank Assign File) in PMJ2008. Since DIF contains all the coordinate
information necessary for mask data prioritization, it has been proved that mask engineers do not need to access the design
information any more. Recently the necessity of information linkage between mask processes and wafer processes has been
pointed out and we have started to build a new flow to share the mask data priority information.
In this presentation, we will address two new progresses of MaskD2I. One is a new rank assignment method to inspection
tools and the other is information feed forward to wafer process.
Poster Session: Simulation and Modeling
Extracting mask error function from intensity slices
Show abstract
A new method to calculate Mask Error Enhancement Function, or MEEF, from the intensity slope of the unperturbed
geometry and intensity offset of the perturbed mask is derived. In the limit of small perturbations, the intensity slope
technique is predicted to be the same as MEEF values calculated from the ratio of wafer to mask CD differences scaled
by the magnification. Full chip process window simulations were done to compare the accuracy of this new approach
for 45 to 90nm mask designs for line, space and contact features. The standard deviation was less than 0.11 and the
largest deviation was only 12% for over 5200 MEEF calculations. Below MEEF values of 20, the standard deviation
was less 0.065 and all simulations were within ±0.5.
A significant discovery in this work is the inverse relationship between image intensity slope rather than NILS or ILS at
the location of the printed feature edge and MEEF. Since the image slope decreases closer to the intensity extrema, high
MEEF regions are predicted to be those that print closest to the minimum and maximum intensities.
Focus blur model to enhance lithography model for optical proximity correction
Show abstract
The concept of focus blur encompasses the effect of laser bandwidth longitudinal chromatic
aberration and scanner stage vertical vibration. The finite bandwidth of excimer laser source
causes a corresponding finite distribution of focal planes in a range of 100nm or larger for the
optical lithography system. Similarly, scanner vertical stage vibration puts the wafer in a finite
distribution of focal planes. Both chromatic aberration and vertical stage vibration could
introduce significant CD errors, hence can no longer be ignored in current lithography processes
development and OPC development that require CD control within a few nanometers. We
developed several methodologies to model the laser chromatic aberration and vertical stage
vibration in OPC (Optical Proximity Correction) modeling tool. Extensive simulations were done
to calculate chromatic aberration and vertical stage vibration focus blur's impact on lithography
patterning for a variety of test structures. Chromatic aberration and vertical stage vibration focus
blur effect was further included as an regression term in experimental OPC model calibration to
capture its impact on litho patterning, and significant benefit to OPC model calibration was
observed.
Poster Session: RET and OPC/ORC
32nm design rule and process exploration flow
Show abstract
Semiconductor manufacturers spend hundreds of millions of dollars and years of development time to create a new
manufacturing process and to design frontrunner products to work on the new process. A considerable percentage of this
large investment is aimed at producing the process design rules and related lithography technology to pattern the new
products successfully. Significant additional cost and time is needed in both process and design development if the
design rules or lithography strategy must be modified. Therefore, early and accurate prediction of both process design
rules and lithography options is necessary for minimizing cost and timing in semiconductor development.
This paper describes a methodology to determine the optimum design rules and lithography conditions with high
accuracy early in the development lifecycle. We present results from the 32nm logic node but the methodology can be
extended to the 22nm node or any other node. This work involves: automated generation of extended realistic logic test
layouts utilizing programmed teststructures for a variety of design rules; determining a range of optical illumination and
process conditions to test for each critical design layer; using these illumination conditions to create a extrapolatable
process window OPC model which is matched to rigorous TCAD lithography focus-exposure full chemically amplified
resist models; creating reticle enhancement technique (RET) recipes which are flexible enough to be used over a variety
of design rule and illumination conditions; OPC recipes which are flexible enough to be used over a variety of design
rule and illumination conditions; and OPC verification to find, categorize and report all patterning issues found in the
different design and illumination variations. In this work we describe in detail the individual steps in the methodology,
and provide results of its use for 32nm node design rule and process optimization.
Accelerate OPC convergence with new iteration control methodology
Show abstract
A dilemmatic trade-off that all OPC engineers are facing everyday is the convergence of the OPC result and
the control of the OPC iteration times. Theoretically, infinite times of OPC iterations are needed to achieve a
convergent and stable correction result. But actually there should always be a cut-off for the iteration time, for turnaround-
time is always an important criteria for IC fabs. But considering the design layout becomes more complicated
and pattern density becomes higher with the shrinkage of the critical dimension, fragmentation control during the
OPC procedure is also becoming more and more sophisticated. Thus, to achieve a convergent correction result for all
OPC fragments within limited correction iteration times now becomes a big challenge to OPC engineers. This work
presents our study in a new OPC iteration control methodology. It can help to find an algorithm that always
converges, and reduce the excessive use of parameter setting, commands and other involvement by the user. With
this, we can reduce the run time required to obtain a convergent OPC solution.
Enhanced DCT2-based inverse mask synthesis with initial SRAF insertion
Show abstract
Inverse mask synthesis, or Inverse Lithography Technology, as a next generation resolution enhancement technology,
is drawing pretty much attention after years of development. However, the existing optimized mask usually
is too complex such that the pattern simplifying procedures have to be applied as a post processing step. But
the post processing step may lead to pattern degradation and unwanted side lobe printing. In this paper, we
first implement a new inverse mask synthesis system using two dimensional discrete cosine transform(DCT2)
of the target mask, where the low frequency components are used in the optimization. As the high frequency
components are discarded, the resulted optimal pattern is similar in shape to that of using the level set method
in the published papers. Moreover, as inverse mask synthesis is an ill-posed problem, there are some local minimum
locations. Previous algorithms usually use the desired pattern as an initial iteration point, in the sense
that optimized pattern shall be a perturbation of the desired pattern. A common fact is that initial solution
is critical to the optimization procedure and final result. In this paper, we apply an initial SRAF insertion
around the main features before starting the existing inverse engine. The SRAF insertion does not need to be
as accurate as that in the traditional SRAF+main feature OPC flow. Therefore, it does not add higher time
burden on the whole mask synthesis flow. We implement the SRAF insertion based on computed mask electric
field distribution. The experimental results show that using the initial fast SRAF insertion, the inverse engine
is able to take advantage of a better initial high contrast image distribution, and the optimized pattern can be
much simpler while the pattern fidelity is still in good control. We also observe that better optimized patterns
can be achieved with fewer iterations.
Empirical study of OPC metrology requirements for 32-nm node logic
Show abstract
We evaluate the relationship between the number of measurements used to create each data point in an OPC model data
set and resulting model quality for target 32-nm logic node applications. Generated data sets will range from singlemeasurement,
unfiltered data sets to many-measurement averages based on filtered results. Intermediate measurementcount
averages will also be evaluated in an attempt to quantify the tradeoff between raw measurements per data point
and resulting model quality. Finally, other variations will also be considered, such as automated versus manual data
filtering. The auto-fitted OPC models will be compared to identify metrology recommendations for 32-nm logic node
modeling.
Adaptive automatic fragmentation
Show abstract
As more aggressive Resolution Enhancement Techniques (RET) are applied, the problem of correctly
fragmenting edges of an OPC mask is becoming more complex. OPC recipes contain more lines devoted to
control of fragmentation than anything else. This paper introduces a new Automatic Adaptive Fragmentation
method that decreases the complexity of OPC recipes while providing the same or better quality of results. The
adaptive fragmentation is guided by just a few simple rules that provide flexible fragmentation while adhering to
mask manufacturing rule constraints.
Enhancing OPC model stability and predictability using SEM image contours
Show abstract
The process model is a major factor affecting the quality of the Model Based Optical Proximity Correction
(OPC). Better process model directly leads to better OPC, hence better yield and more profit. While the
traditional way in calibrating these process models is using CD measurements at sample locations in the test chip,
however, the use of Scanning Electron Microscope (SEM) image contours for process model calibration and
optimization has been recently introduced in trial to build more predictable models. In this study, we characterize
the traditional flow models versus the contour calibrated models and study the effect of using different
combinations and weighting schemes on the quality of the resulting process models, its stability and its ability to
correctly predict the process.
Characterizing OPC model accuracy versus lens induced polarization effects in hyper NA immersion lithography
Show abstract
Immersion lithography is extending the lifetime of optical lithography by enabling numerical aperture (NA) greater than
unity. Along with scanner hardware improvements, modeling of hyper-NA lithography systems for optical proximity
correction (OPC) is also continuing to be necessary in improving photolithography capability. With the use of hyper-NA
immersion lithography and polarized illumination, the assumption of scalar optical pupil in optical system modeling may
no longer be valid. To fully describe the transmission of any polarization state through the optical system, Jones matrix is
necessary. It has been shown that Jones matrix can be described as a combination of apodization loss, birefringence,
diattenuation, scalar phase aberrations, and rotation effects. In this work, the impact of such effects on calibration and
accuracy of OPC models is characterized in terms of the model fit quality, model predictability, and changes to OPC
results.
Toward faster OPC convergence: advanced analysis for OPC iterations and simulation environment
Show abstract
Achieving faster Turn-Around-Time (TAT) is one of the most attractive objectives for the silicon wafer
manufacturers despite the technology node they are processing. This is valid for all the active technology
nodes from 130nm till the cutting edge technologies. There have been several approaches adopted to cut
down the OPC simulation runtime without sacrificing the OPC output quality, among them is using
stronger CPU power and Hardware acceleration which is a good usage for the advancing powerful
processing technology. Another favorable approach for cutting down the runtime is to look deeper inside
the used OPC algorithm and the implemented OPC recipe. The OPC algorithm includes the convergence
iterations and simulation sites distribution, and the OPC recipe is in definition how to smartly tune the OPC
knobs to efficiently use the implemented algorithm. Many previous works were exposed to monitoring the
OPC convergence through iterations and analyze the size of the shift per iteration, similarly several works
tried to calculate the amount of simulation capacity needed for all these iterations and how to optimize it
for less amount.
The scope of the work presented here is an attempt to decrease the number of optical simulations by
reducing the number of control points per site and without affecting OPC accuracy. The concept is proved
by many simulation results and analysis. Implementing this flow illustrated the achievable simulation
runtime reduction which is reflected in faster TAT. For its application, it is not just runtime optimization,
additionally it puts some more intelligence in the sparse OPC engine by eliminating the headache of
specifying the optimum simulation site length.
OPC cycle time reduction and accuracy improvement by early access to advanced Tachyon modeling of TWINSCAN XT:1900i scanner
Show abstract
Double Patterning (DP), Spacers and other advanced Litho technologies require an enormous amount of CD and tool
data collection and development time for Optical Proximity Correction (OPC) modeling. Unfortunately this process
could be started typically only when the Litho and Etch process development for the OPC'ed layer is done. This leads to
significant (a month and more) delays with the mask tape-outs and final chip readiness for production.
In this paper we discussed a way to reduce the overall OPC and MDP preparation and product-to-market time and
increase the OPC accuracy by early collection of the OPC measurements, automatic CD-SEM recipe generation and CD
data analysis and model calibration with Tachyon software.
We reviewed the design of the OPC test chip, OPC exposures, data analysis and OPC modeling on the advanced and
accurate Tachyon T2.0 OPC platform and ways to improve modeling cycle time.
Another critical parameter of the OPC modeling is accuracy as one of the main parts of the CD error budget. We
investigated approaches to OPC modeling accuracy and achieved RMS below 1nm for critical features by using module
data of the respective ASML TWINSCAN XT:1900i scanner and advanced Tachyon software.
Sizing algorithm with continuous customizable clipping
Show abstract
Polygon sizing is required during Mask Data Preparation in order to generate derived layers
and as process bias to account for edge effects of etching. Two main features are required for
polygon sizing algorithms to be useful in Mask Data Preparation software: correctness to avoid data
corruption and clipping of the projection of acute angle vertices to limit connectivity modifications.
However, current available solutions are either based on heuristics, producing corrupted results for
certain input, or based on algorithms which may fail to maintain original design's connectivity for
certain input. A novel algorithm including customizable clipping is presented.