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Proceedings of SPIE Volume 6590

VLSI Circuits and Systems III
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Volume Details

Volume Number: 6590
Date Published: 10 May 2007
Softcover: 58 papers (598) pages
ISBN: 9780819467188

Table of Contents
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Front Matter: Volume 6590
Author(s): Proceedings of SPIE
High-level power estimation for digital system
Author(s): Yaseer A. Durrani; Ana Abril; Teresa Riesgo
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Partitioning and characterization of high speed adder structures in deep-submicron technologies
Author(s): Adrián Estrada; Gashaw Sassaw; Carlos J. Jiménez; Manuel Valencia
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Power-driven FPGA to ASIC conversion
Author(s): WenHai Fang; Lambert Spaanenburg
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Low-cost VLSI architecture design for forward quantization of H.264/AVC
Author(s): G. A. Ruiz; J. A. Michell
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Toward the implementation of a baseline H.264/AVC decoder onto a reconfigurable architecture
Author(s): S. López; A. Kanstein; J. F. López; M. Berekovic; R. Sarmiento; J.-Y. Mignolet
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Accelerating a MPEG-4 video decoder through custom software/hardware co-design
Author(s): Jorge L. Díaz; Dacil Barreto; Luz García; Gustavo Marrero; Pedro P. Carballo; Antonio Núñez
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Optimizing coarse-grain reconfigurable hardware utilization through multiprocessing: an H.264/AVC decoder example
Author(s): Andreas Kanstein; Sebastian López Suárez; Bjorn De Sutter
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Low-voltage low-power reference circuits for an autonomous robot: I-SWARM
Author(s): J. Colomer; A. Saiz-Vela; P. Miribel-Català; M. Puig-Vidal; J. Samitier
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Low-voltage CMOS variable preamplifier for fiber-based gigabit ethernet
Author(s): J. M. García del Pozo; S. Celma; C. Aldea; J. P. Alegre; D. Digón
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Design of clock recovery circuits for optical clocking in DSM CMOS
Author(s): Charles Thangaraj; Kevin Stephenson; Tom Chen; Kevin Lear; Abdul Matheen Raza
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A study of mismatch in adaptive programmable CMOS sensor compensation circuits
Author(s): G. Zatorre; N. Medrano; M. T. Sanz; P. A. Martínez; S. Celma; J. M. Garcia-del-Pozo
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Architectural design for a low cost FPGA-based traffic signal detection system in vehicles
Author(s): Ignacio López; Rubén Salvador; Jaime Alarcón; Félix Moreno
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Hand veins feature extraction using DT-CNNS
Author(s): Suleyman Malki; Lambert Spaanenburg
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Real-time lane detector hardware system
Author(s): Pedro Cobos Arribas; Felipe Jiménez Alonso
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Exploring system interconnection architectures with VIPACES: from direct connections to NoCs
Author(s): Armando Sánchez-Peña; Pedro P. Carballo; Antonio Núñez
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Automatic synthesis of zero-aliasing space compactors with application to testing of embedded IP cores
Author(s): José M. Solana; Javier Frechoso
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Design automation techniques for high-resolution current folding and interpolating CMOS A/D converters
Author(s): D. Gevaert
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Toward systematic design of multi-standard converters
Author(s): V. J. Rivas; R. Castro-López; A. Morgado; O. Guerra; E. Roca; R. del Río; J. M. de la Rosa; F. V. Fernández
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Crosscoupling power optimal wire spacing in quasilinear runtime
Author(s): Paul Zuber; Thomas Ilnseher; Walter Stechele
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A methodology for switching noise estimation at gate level
Author(s): Javier Castro; Pilar Parra; Antonio J. Acosta
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Multiformat decoder for a DSP-based IP set-top box
Author(s): F. Pescador; M. J. Garrido; C. Sanz; E. Juárez; D. Samper; R. Antoniello
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MPEG-4 ASP SoC receiver with novel image enhancement techniques for DAB networks
Author(s): D. Barreto; A. Quintana; L. García; G. M. Callicó; A. Núñez
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High parallel-pipeline integer-pel and fractional-pel motion estimation VLSI architectures for H.264/AVC
Author(s): Armando Mora-Campos; Francisco J. Ballester-Merelo; Marcos A. Martínez-Peiró; José A. Canals-Esteve
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H.264 video stream statistical analysis for post-compression improvements
Author(s): J. Hugo Pérez Casanova; Francisco J. Ballester Merelo; Marcos A. Martínez Peiró; Josep Canals Esteve
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Variable length packet scheduler algorithm with QoS support
Author(s): R. Arteaga; F. Tobajas; R. Esper-Chaín; M. A. Monzón; R. Regidor; V. De Armas; R. Sarmiento
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Integrated hardware interfaces for modular sensor networks
Author(s): J. Portilla; A. de Castro; A. Abril; T. Riesgo
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Design of a 0.13-um CMOS cascade expandable ΣΔ modulator for multi-standard RF telecom systems
Author(s): Alonso Morgado; Rocío del Río; José M. de la Rosa
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A design tool for high-resolution high-frequency cascade continuous-time ΣΔ modulators
Author(s): R. Tortosa; R. Castro-López; J. M. de la Rosa; A. Rodríguez-Vázquez; F. V. Fernández
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A highly linear fast-settling envelope detector
Author(s): Juan Pablo Alegre; Santiago Celma; Jose María García del Pozo; Pedro Martínez
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Behavioral modeling and simulation of multi-standard RF receivers using MATLAB/SIMULINK
Author(s): Alonso Morgado; Rocío del Río; José M. de la Rosa
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Low power considerations and design for CMOS VCOs applied for direct conversion receivers at 5GHz
Author(s): Iñigo Adin; Carlos Quemada; Hector Solar; Beatriz Sedano; Iñigo Gutierrez
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Test measures evaluation for VCO and charge pump blocks in RF PLLs
Author(s): Anna Asquini; Jean-Louis Carbonero; Salvador Mir
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A low-voltage fully balanced CMFF transconductor with improved linearity
Author(s): B. Calvo; S. Celma; J. P. Alegre; M. T. Sanz
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Powerline LonTalk protocol performance analysis in SystemC
Author(s): Salvatore Isaia; Massimo Conti; Giovanni B. Vece; Simone Orcioni
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Mixed signal SystemC modelling of a SoC architecture with Dynamic Voltage Scaling
Author(s): G. Leoce; R. D'Aparo; G. B. Vece; G. Biagetti; S. Orcioni; M. Conti
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Efficient hardware implementation of 3X for radix-8 encoding
Author(s): G. A. Ruiz; Mercedes Granda
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Dynamic power management of a system on chip based on AMBA AHB bus
Author(s): Simone Marinelli; Massimo Conti
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Implementation of a parametrizable router architecture for networks-on-chip (NoC) with quality of service (QoS) support
Author(s): R. Regidor; F. Tobajas; V. De Armas; J. M. Rivero; R. Sarmiento
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A SoC for studying multi-agent software/algorithms on a real swarm of mm3-sized microrobots
Author(s): R. Casanova; A. Diéguez; A. Arbat; A. Sanuy; O. Alonso; J. Canals; M. Puig; J. Samitier
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New FPSoC-based architecture for efficient FSBM motion estimation processing in video standards
Author(s): J. A. Canals; M. A. Martínez; F. J. Ballester; A. Mora
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The electrical origin of the 1/f electrical noise in solid-state devices and integrated circuits
Author(s): José-Ignacio Izpura
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A stochastic model of digital switching noise
Author(s): Giorgio Boselli; Gabriella Trucco; Valentino Liberali
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Temperature impact on multiple-input CMOS gates delay
Author(s): C. de Benito; S. Bota; J. L. Rosselló; J. Segura
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Ultra low power switched current finite impulse response filter banks realized in CMOS 0.18 um technology
Author(s): Rafał Długosz
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Synchronous and asynchronous multiplexer circuits for medical imaging realized in CMOS 0.18um technology
Author(s): R. Długosz; K. Iniewski
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Resizing methodology for CMOS analog circuits
Author(s): Timothée Levi; Jean Tomas; Noëlle Lewis; Pascal Fouillat
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IP-based design reuse for analog systems
Author(s): Timothée Levi; Jean Tomas; Noëlle Lewis; Pascal Fouillat
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A study of stacked and miniature 3-D inductor performance for radio frequency integrated circuit design
Author(s): A. Goñi Iturri; F. J. del Pino; S. L. Khemchandani; J. García; B. González; A. Hernández
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A fully integrated VCO with a wide tuning range for DVB-H
Author(s): S. L. Khemchandani; G. Betancort; Javier del Pino Suarez; Unai Alvarado; Amaya Goni-Iturri; Antonio Hernandez
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FPGA realization of a split radix FFT processor
Author(s): Jesús García; Juan A. Michell; Gustavo Ruiz; Angel M. Burón
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A fully integrated folded mixer in CMOS 0.35 µm technology for 802.11a WIFI applications
Author(s): J. del Pino; R. Díaz; M. Afonso; F. Cabrera; A. Iturri; S. L. Khemchandani
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Influence of the diffusion geometry on PN integrated varactors
Author(s): J. García; B. González; M. Marrero-Martin; I. Aldea; J. del Pino; A. Hernández
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Enhanced instrumentation system to characterize the electric behavior of AFLC displays
Author(s): José M. S. Pena; José I. Santos; Juan C. Torres; Noemí Gaona; Carmen Vázquez; David Quesada
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A 3-10 GHz ultra-wideband SiGe LNA with wideband LC matching network
Author(s): J. del Pino; S. L. Khemchandani; H. García; R. Pulido; A. Goñi; A. Hernández
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Automatic logic synthesis for parallel alternating latches clocking schemes
Author(s): D. Guerrero; M. Bellido; J. Juan; A. Millan; P. Ruiz; E. Ostua; J. Viejo
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Effects of buffer insertion on the average/peak power ratio in CMOS VLSI digital circuits
Author(s): Antonio J. Acosta; José M. Mora; Javier Castro; Pilar Parra
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Flexible and low power binary-tree current mode min/max nonlinear filters realized in CMOS technology
Author(s): R. Długosz; T. Talaśka
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HEAPAN: a high-level computer architecture analysis tool
Author(s): Dionisio D. Peñalosa; Carlos J. Jiménez; Manolo Valencia
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