Share Email Print
cover

Proceedings of SPIE Volume 6521

Design for Manufacturability through Design-Process Integration
Format Member Price Non-Member Price
Softcover $105.00 * $105.00 *

*Available as a photocopy reprint only. Allow two weeks reprinting time plus standard delivery time. No discounts or returns apply.


Volume Details

Volume Number: 6521
Date Published: 15 March 2007
Softcover: 63 papers (588) pages
ISBN: 9780819466402

Table of Contents
show all abstracts | hide all abstracts
Front Matter: Volume 6521
Author(s): Proceedings of SPIE
Collaborative platform, tool-kit, and physical models for DfM
Author(s): Andy Neureuther; Wojtek Poppe; Juliet Holwill; Eric Chin; Lynn Wang; Jae-Seok Yang; Marshal Miller; Dan Ceperley; Chris Clifford; Koji Kikuchi; Jihong Choi; Dave Dornfeld; Paul Friedberg; Costas Spanos; John Hoang; Jane Chang; Jerry Hsu; David Graves; Alan C. F. Wu; Mike Lieberman
Show Abstract
Lithography simulation in DfM: achievable accuracy versus requirements
Author(s): Scott Mansfield; Ioana Graur; Geng Han; Jason Meiring; Lars Liebmann; Dureseti Chidambarrao
Show Abstract
Structural failure prediction using simplified lithography simulation models
Author(s): P. Niedermaier; T. Roessler
Show Abstract
Unified process-aware system for circuit layout verification
Author(s): J. Andres Torres; Fedor G. Pikus
Show Abstract
Double patterning design split implementation and validation for the 32nm node
Author(s): Martin Drapeau; Vincent Wiaux; Eric Hendrickx; Staf Verhaegen; Takahiro Machida
Show Abstract
DRC Plus: augmenting standard DRC with pattern matching on 2D geometries
Author(s): Vito Dai; Jie Yang; Norma Rodriguez; Luigi Capodieci
Show Abstract
Process window aware layout optimization using hot spot fixing system
Author(s): Sachiko Kobayashi; Suigen Kyoh; Toshiya Kotani; Soichi Inoue
Show Abstract
Automated full-chip hotspot detection and removal flow for interconnect layers of cell-based designs
Author(s): Ed Roseboom; Mark Rossman; Fang-Cheng Chang; Philippe Hurat
Show Abstract
Model-assisted routing for improved lithography robustness
Author(s): Tim Kong; Hardy Leung; Vivek Raghavan; Alfred K. Wong; Sarah Xu
Show Abstract
Model-based approach for design verification and co-optimization of catastrophic and parametric-related defects due to systematic manufacturing variations
Author(s): Dan Perry; Mark Nakamoto; Nishath Verghese; Philippe Hurat; Rich Rouse
Show Abstract
Context-specific leakage and delay analysis of a 65nm standard cell library for lithography-induced variability
Author(s): Darsun Tsien; Chien Kuo Wang; Yajun Ran; Philippe Hurat; Nishath Verghese
Show Abstract
Patterning effect and correlated electrical model of post-OPC MOSFET devices
Author(s): Y. C. Cheng; T. H. Ou; M. H. Wu; W. L. Wang; J. H. Feng; W. C. Huang; C. M. Lai; R. G. Liu; Y. C. Ku
Show Abstract
Coupling-aware mixed dummy metal insertion for lithography
Author(s): Liang Deng; Martin D. F. Wong; Kai-Yuan Chao; Hua Xiang
Show Abstract
Prediction of interconnect delay variations using pattern matching
Author(s): Eric Y. Chin; Juliet A. Holwill; Andrew R. Neureuther
Show Abstract
OPC to reduce variability of transistor properties
Author(s): Kaoru Koike; Kohichi Nakayama; Kazuhisa Ogawa; Hidetoshi Ohnuma
Show Abstract
Improving the power-performance of multicore processors through optimization of lithography and thermal processing
Author(s): A. H. Gabor; T. Brunner; S. Bukofsky; S. Butt; F. Clougherty; S. Deshpande; T. Faure; O. Gluschenkov; K. Greene; J. Johnson; N. Le; P. Lindo; A. P. Mahorowala; H-J. Nam; D. Onsongo; D. Poindexter; J. Rankin; N. Rohrer; S. Stiffler; A. Thomas; H. Utomo
Show Abstract
Cost-performance tradeoff between design and manufacturing: DfM or MfD?
Author(s): A. Balasinski; J. Cetin; L. Karklin
Show Abstract
Hardware verification of litho-friendly design (LfD) methodologies
Author(s): Reinhard März; Kai Peter; Sonja Gröndahl; Klaus Keiner; Byoung Il Choi; Shyue Fong Quek; Mei Chun Yeo; Nan Shu Chen; Soo Muay Goh
Show Abstract
Lithography and yield sensitivity analysis of SRAM scaling for the 32nm node
Author(s): Axel Nackaerts; Staf Verhaegen; Mircea Dusa; Hans Kattouw; Frank van Bilsen; Serge Biesemans; Geert Vandenberghe
Show Abstract
Model-based assist feature generation
Author(s): Bayram Yenikaya; Apo Sezginer
Show Abstract
Three-dimensional mask effect approximate modeling for sub-50-nm node device OPC
Author(s): Sungsoo Suh; SukJoo Lee; Kyoung-yoon Back; Sook Lee; Youngchang Kim; Sangwook Kim; Yong-Jin Chun
Show Abstract
Litho aware method for circuit timing/power analysis through process
Author(s): R. S. Fathy; M. Al-Imam; H. Diab; M. M. Fakhry; J. A. Torres; B. Graupp; J. M. Brunet; M. S. Bahnas
Show Abstract
Circuit size optimization with multiple sources of variation and position dependant correlation
Author(s): Qian Ying Tang; Paul Friedberg; George Cheng; Costas J. Spanos
Show Abstract
Multidimensional physical design optimization for systematic and parametric yield loss reduction
Author(s): L. N. Karklin; A. Arkhipov; Y. Belenky; C. Decoin; D. Lay; V. Manuylov; C. Zelnik; B. W. Watson; J. Willekens
Show Abstract
Highly accurate model-based verification using SEM image calibration method
Author(s): Byung-ug Cho; Dae-jin Park; Dong-suk Chang; Jae-seung Choi; Cheol-Kyun Kim; DongGyu Yim; Ju-Byung Kim
Show Abstract
The study for increasing efficiency of OPC verification by reducing false errors from bending pattern by using different size of CD error non-checking area with various corner lengths
Author(s): Sang-Uk Lee; Yong-Suk Lee; Jeahee Kim; Keeho Kim
Show Abstract
DFM flow by using combination between design-based metrology system and model-based verification at sub-50nm memory device
Author(s): Cheol-kyun Kim; Jungchan Kim; Jaeseung Choi; Hyunjo Yang; Donggyu Yim; Jinwoong Kim
Show Abstract
Application of enhanced dynamic fragmentation to minimize false error from post OPC verification
Author(s): Jae-Hyun Kang; Sang uk Lee; Jeahee Kim; Keeho Kim
Show Abstract
Pattern decomposition for double patterning from photomask viewpoint
Author(s): Nobuhito Toyama; Takashi Adachi; Yuichi Inazuki; Takanori Sutou; Yasutaka Morikawa; Hiroshi Mohri; Naoya Hayashi
Show Abstract
Impacts of optical proximity correction settings on electrical performances
Author(s): Meng-Fu You; Philip C. W. Ng; Yi-Sheng Su; Kuen-Yu Tsai; Yi-Chang Lu
Show Abstract
Lithography enhanced manufacturability analysis by using multilevel simulated contours
Author(s): Beom-Seok Seo; Woon-Hyuk Choi; Jong-Woon Park; Soung-Su Woo; Sung-Ho Lee
Show Abstract
Scanner-characteristics-aware OPC modeling and correction
Author(s): Jacek K. Tyminski; Qiaolin Zhang; Kevin Lucas; Laurent Depre; Paul VanAdrichem
Show Abstract
Wire sizing and spacing for lithographic printability optimization
Author(s): Ke Cao; Jiang Hu; Mosong Cheng
Show Abstract
A rigorous method to determine printability of a target layout
Author(s): Bayram Yenikaya; Apo Sezginer
Show Abstract
Double patterning technology: process-window analysis in a many-dimensional space
Author(s): Apo Sezginer; Bayram Yenikaya
Show Abstract
Novel technique to separate systematic and random defects during 65nm and 45nm process development
Author(s): J. H. Yeh; Allen Park
Show Abstract
Intelligent fill pattern and extraction methodology for sensitive RF/analog or SoC products
Author(s): A. Balasinski; J. Cetin; A. Kahng
Show Abstract
Scanner parameter sensitivity analysis for OPE
Author(s): Tomoyuki Matsuyama; Toshiharu Nakashima; Tomoharu Fujiwara; Yuki Ishii
Show Abstract
OPC and design verification for DFM using die-to-database inspection
Author(s): JungChan Kim; HyunJo Yang; JooKyoung Song; DongGgyu Yim; JinWoong Kim; Toshiaki Hasebe; Masahiro Yamamoto
Show Abstract
Self-assembled dummy patterns for lithography process margin enhancement
Author(s): James Moon; Byoung-Sub Nam; Joo-Hong Jeong; Byung-Ho Nam; Dong Gyu Yim
Show Abstract
Modeling spatial gate length variation in the 0.2µm to 1.15mm separation range
Author(s): Paul Friedberg; Willy Cheung; George Cheng; Qian Ying Tang; Costas J. Spanos
Show Abstract
Novel method for quality assurance of two-dimensional pattern fidelity
Author(s): Shimon Maeda; Ryuji Ogawa; Seiji Shibazaki; Tadashi Nakajima
Show Abstract
A systematic approach for capturing interconnects hot spots
Author(s): Mohamed Al-Imam; H. Y. Liao; Jochen Schacht; Te Hung Wu; Chia Wei Huang; Shen Yuan Huang; Pei Ru Tsai; Chuen Huei Yang
Show Abstract
Ensuring production-worthy OPC recipes using large test structure arrays
Author(s): Christopher Cork; Rainer Zimmermann; Xin Mei; Alexander Shahin
Show Abstract
Intelligent visualization of lithography violations
Author(s): David Ziger
Show Abstract
Production-worthy OPC verification methods for protecting against process variability
Author(s): James A. Bruce; Norman Chen; Vinay Chinta; Ramon De La Cruz; Yea-Sen Lin
Show Abstract
Automatic OPC mask shape repair
Author(s): James Word; Dragos Dudau; Nick Cobb
Show Abstract
SOFT: smooth OPC fixing technique for ECO process
Author(s): Hongbo Zhang; Zheng Shi
Show Abstract
The accuracy of a calibrated PROLITH physical resist model across illumination conditions
Author(s): John J. Biafore; Stewart A. Robertson; Mark D. Smith; Chris Sallee
Show Abstract
Feedback flow to improve model-based OPC calibration test patterns
Author(s): Walid A. Tawfic; Mohamed Al-Imam; Karim Madkour; Rami Fathy; Ir Kusnadi; George E. Bailey
Show Abstract
Double pattern EDA solutions for 32nm HP and beyond
Author(s): George E. Bailey; Alexander Tritchkov; Jea-Woo Park; Le Hong; Vincent Wiaux; Eric Hendrickx; Staf Verhaegen; Peng Xie; Janko Versluijs
Show Abstract
Optimizing gate layer OPC correction and SRAF placement for maximum design manufacturability
Author(s): Travis Brist; Le Hong; Ayman Yehia; Tamer Tawfik; Shumay Shang; Kyohei Sakajiri; John L. Sturtevant
Show Abstract
Assist features for modeling three-dimensional mask effects in optical proximity correction
Author(s): Qiliang Yan; Zhijie Deng; James Shiely; Lawrence Melvin
Show Abstract
Circuit-based SEM contour OPC model calibration
Author(s): Kyle Patterson; Jim Vasek; Chi Min Yuan; George E. Bailey; Ir Kusnadi; Thuy Do; John L. Sturtevant
Show Abstract
Boundary-based cellwise OPC for standard-cell layouts
Author(s): David M. Pawlowski; Liang Deng; Martin D. F. Wong
Show Abstract
Statistical analysis of gate CD variation for yield optimization
Author(s): Juliet Holwill; Jongwook Kye; Yi Zou
Show Abstract
Minimizing poly end cap pull back by application of DFM and advanced etch approaches for 65nm and 45nm technologies
Author(s): Russell Callahan; Gunter Grasshoff; Stefan Roling; Joseph Shannon; Asuka Nomura; Sarah N. McGowan; Cyrus E. Tabery; Karla Romero
Show Abstract
Real-time VT5 model coverage calculations during OPC simulations
Author(s): Ioana Graur; Scott Mansfield; Moahmed Gheith; Mohamed Al-Imam
Show Abstract
A simple and practical approach for building lithography simulation models using a limited set of CD data and SEM pictures
Author(s): Yan Wang; Jonathan Ho; Benjamin Lin; C.-L. Lin; Y.-C. Sheng; Yoyi Gong; Steven Hsu; Kechih Wu
Show Abstract
More on accelerating physical verification using STPRL: a novel language for test pattern generation
Author(s): Ahmed Nouh
Show Abstract
DRC and mask friendly pattern and probe aberration monitors
Author(s): Juliet Holwill; Andrew R. Neureuther
Show Abstract
Mask manufacturing rules checking (MRC) as a DFM strategy
Author(s): Peter Buck; Richard Gladhill; Joseph Straub
Show Abstract
Design for manufacturing approach to second level alternating phase shift mask patterning
Author(s): Sven Henrichs; Mahesh Chandramouli; Min Chun Tsai
Show Abstract

© SPIE. Terms of Use
Back to Top