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Proceedings of SPIE Volume 6156

Design and Process Integration for Microelectronic Manufacturing IV
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Volume Details

Volume Number: 6156
Date Published: 10 March 2006
Softcover: 52 papers (526) pages
ISBN: 9780819461995

Table of Contents
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Layout rule trends and effect upon CPU design
Author(s): Clair Webb
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Through-process modeling in a DfM environment
Author(s): Scott Mansfield; Geng Han; Mohamed Al-Imam; Rami Fathy
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A genuine design manufacturability check for designers
Author(s): Philippe Hurat; Michel Cote; Chi-Ming Tsai; Joe Brandenburg
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Annotated layout optimization
Author(s): Jörg Thiele; Roderick Köhle
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Silicon IP reuse standards for design for manufacturability
Author(s): Juan Antonio Carballo; Savithri Sundareswaran
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Call for an industry standard for pattern transfer models for usage in OPC and design for manufacturability
Author(s): Thomas Roessler; Wolfgang Grimm; Jörg Thiele
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A heuristic method for statistical digital circuit sizing
Author(s): Stephen Boyd; Seung-Jean Kim; Dinesh Patil; Mark Horowitz
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Layout verification and optimization based on flexible design rules
Author(s): Jie Yang; Luigi Capodieci; Dennis Sylvester
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Self-compensating design for reduction of timing and leakage sensitivity to systematic pattern dependent variation
Author(s): Puneet Gupta; Andrew B. Kahng; Youngmin Kim; Dennis Sylvester
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DFM: a practical layout optimization procedure for the improved process window for an existing 90-nm product
Author(s): Jonathan Ho; Yan Wang; Ya-Ching Hou; Benjamin Szu-Min Lin; Chun Chi Yu; Kechih Wu; Cliff Ma
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CD analysis of advanced photolithography and its impact on critical design structures
Author(s): Karla A. Romero; Rolf Seltmann; Gert Burbach; Rolf Stephan; Joerg Paufler; David Greenlaw
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Platform for collaborative DFM
Author(s): Wojtek J. Poppe; Luigi Capodieci; Andrew Neureuther
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Lithography oriented DfM for 65 nm and beyond
Author(s): S. Kyoh; T. Kotani; S. Kobayashi; A. Ikeuchi; S. Inoue
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DFM requirements and solution roadmaps: the multilayer approach
Author(s): Juan Antonio Carballo; Sani Nassif
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The nanotech impact on IC processing: near and long term
Author(s): John N. Randall; Richard Stallcup; Taylor Cavanah
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Maximization of layout printability/manufacturability by extreme layout regularity
Author(s): Tejas Jhaveri; Larry Pileggi; Vyacheslav Rovner; Andrzej J. Strojwas
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Reducing DfM to practice: the lithography manufacturability assessor
Author(s): Lars Liebmann; Scott Mansfield; Geng Han; James Culp; Jason Hibbeler; Roger Tsai
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Design-friendly DFM rule
Author(s): Morimi Osawa; Takayoshi Minami; Hiroki Futatsuya; Satoru Asai
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Toward DFM: process worthy design and OPC through verification method using MEEF, TF-MEEF, and MTT
Author(s): In-Sung Kim; Sungsoo Suh; Sunggon Jung; Eunmi Lee; Young-Seog Kang; Sukjoo Lee; Sang-Gyun Woo; HanKu Cho
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Sequential PPC and process-window-aware mask layout synthesis
Author(s): Apo Sezginer; Franz X. Zach; Bayram Yenikaya; Jesus Carrero; Hsu-Ting Huang
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Meeting critical gate linewidth control needs at the 65 nm node
Author(s): Arpan Mahorowala; Scott Halle; Allen Gabor; William Chu; Alexandra Barberet; Donald Samuels; Amr Abdo; Len Tsou; Wendy Yan; Seiji Iseda; Kaushal Patel; Bachir Dirahoui; Asuka Nomura; Ishtiaq Ahsan; Faisal Azam; Gary Berg; Andrew Brendler; Jeffrey Zimmerman; Tom Faure
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Hot spot management in ultra-low k<sub>1</sub> lithography
Author(s): Kohji Hashimoto; Satoshi Usui; Shigeki Nojima; Satoshi Tanaka; Eiji Yamanaka; Soichi Inoue
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Experimental verification of improved printability for litho-driven designs
Author(s): Johannes van Wingerden; Laurent Le Cam; Rene Wientjes; Michael Benndorf; Yorick Trouiller; Jerome Belledent; Rob Morton; Yuri Aksenov
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From poly line to transistor: building BSIM models for non-rectangular transistors
Author(s): Wojtek J. Poppe; Luigi Capodieci; Joanne Wu; Andrew Neureuther
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Patterning with spacer for expanding the resolution limit of current lithography tool
Author(s): Woo-Yung Jung; Choi-Dong Kim; Jae-Doo Eom; Sung-Yoon Cho; Sung-Min Jeon; Jong-Hoon Kim; Jae-In Moon; Byung-Seok Lee; Sung-Ki Park
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OPC to improve lithographic process window
Author(s): James Word; Kyohei Sakajiri
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Lithography window check before mask tape-out in sub-0.18um technology
Author(s): Mark Lu; Dion King; Flora Li; Zhibiao Mao; Curtis Liang; Lawrence S. Melvin
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Improving model-based OPC performance for sub-60nm devices using real source optical model
Author(s): Sunggon Jung; In-Sung Kim; Young-Seog Kang; Gi-Sung Yeo; Sang-Gyun Woo; HanKu Cho; Joo-Tae Moon
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Full-chip lithography manufacturability check for yield improvement
Author(s): Yongfa Huang; Edward Tseng; Benjamin Szu-Min Lin; Chun Chi Yu; Chien-Ming Wang; Hua-Yu Liu
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Optimal segmentation of polygon edges
Author(s): Apo Sezginer; Bayram Yenikaya; Hsu-Ting Huang; Vishnu Kamat; Yung-Tin Chen
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The use of optical proximity correction to compensate for reflectivity differences in N type and P type poly-silicon
Author(s): Lawrence S. Melvin; Jensheng Huang
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RET for the wiring layer of a 3D memory
Author(s): Yung-Tin Chen; Paul Poon; Chris Petti; Vishnu Kamat; Apo Sezginer; Hsu-Ting Huang
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Considerations of model-based OPC verification for sub-70nm memory device
Author(s): Cheol-Kyun Kim; Jae-Seung Choi; Byung-Ho Nam; DongGyu Yim
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Simple method to verify OPC data based on exposure condition
Author(s): James Moon; Young-Bae Ahn; Sey-Young Oh; Byung-Ho Nam; Dong Gyu Yim
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Using design intent to qualify and control lithography manufacturing
Author(s): Jim Vasek; Bill Wilkinson; Al Reich; Cesar Garza; Joyce Zhao; Jim Wiley; Moshe Poyastro; Brian Troy; Youval Nehmadi; Zamir Abraham
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Highly accurate hybrid-OPC method for sub-60nm memory device
Author(s): Hyoung-Soon Yune; Cheol-Kyun Kim; Yeong-Bae Ahn; Byung-Ho Nam; Donggyu Yim
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The use of process models to enhance device performance through semiconductor design
Author(s): Lawrence S. Melvin; Daniel Zhang
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Across field CD control improvement for critical level imaging: new applications for layout correction and optimization
Author(s): Franz Zach; Gökhan Percin; Apo Sezginer
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The influence of calibration pattern coverage for lumped parameter resist models on OPC convergence
Author(s): Martin Niehoff; Shumay Shang; Olivier Toublan
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Development of hot spot fixer (HSF)
Author(s): Toshiya Kotani; Suigen Kyoh; Sachiko Kobayashi; Takatoshi Inazu; Atsuhiko Ikeuchi; Yukihiro Urakawa; Soichi Inoue; Etsuya Morita; Simon Klaver; Takumi Horiuchi; Johan Peeters; Satoshi Kuramoto
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Modeling of non-uniform device geometries for post-lithography circuit analysis
Author(s): Puneet Gupta; Andrew Kahng; Youngmin Kim; Saumil Shah; Dennis Sylvester
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Fast lithography simulation under focus variations for OPC and layout optimizations
Author(s): Peng Yu; David Z. Pan; Chris A. Mack
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Lithography simulation-based full-chip design analyses
Author(s): Puneet Gupta; Andrew B. Kahng; Sam Nakagawa; Saumil Shah; Puneet Sharma
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Modeling edge placement error distribution in standard cell library
Author(s): Puneet Gupta; Andrew B. Kahng; Swamy V. Muddu; Sam Nakagawa
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Reticle enhancement verification for the 65nm and 45nm nodes
Author(s): Kevin Lucas; Kyle Patterson; Robert Boone; Corinne Miramond; Amandine Borjon; Jerome Belledent; Olivier Toublan; Jorge Entradas; Yorick Trouiller
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Challenges and solutions for trench lithography beyond 65nm node
Author(s): Zhijian Lu; Chi-Chien Ho; Mark Mason; Andrew Anderson; Randy Mckee; Ricky Jackson; Cynthia Zhu; Mark Terry
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A high aspect ratio Si-fin FinFET fabricated with 193nm scanner photolithography and thermal oxide hard mask etching techniques
Author(s): Wen-Shiang Liao
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Improving asymmetric printing and low margin using custom illumination for contact hole lithography
Author(s): Scott Jessen; Mark Terry; Mark Mason; Sean O'Brien; Robert Soper; Willie Yarbrough; Thomas Wolf
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Implementation of adaptive site optimization in model-based OPC for minimizing ripples
Author(s): M. Bahnas; M. Al-Imam; A. Seoud; P. LaCour; H. F. Ragai
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Impact of process variation on 65nm across-chip linewidth variation
Author(s): Le Hong; Travis Brist; Pat LaCour; John Sturtevant; Martin Niehoff; Philipp Niedermaier
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Accurate OPC model generation through use of a streamlined data flow incorporating automated test-structure layout and CD-SEM recipe generation
Author(s): Mary Coles; Lewis Flanagin; Ben Rathsack; Steve Prins; James Blatchford
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Diblock copolymer directed self-assembly for CMOS device fabrication
Author(s): Li-Wen Chang; H.-S. Philip Wong
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