Semiconductor devices are making important role in our life. Many semiconductor chips will be used to every thing, and we will receive the various services anywhere anytime through a digital network. There are so many applications using semiconductor products that support such a ubiquitous era, and it is expected that mobile, automobile and PC/AV applications will have the great growth from now on. In this paper, we describe the lithography technology trend and requirements for mask technology from the view point of SOC and FLASH memory trend. From the device development trend, it is expected that FLASH memory become driving force of lithography technology. To realize hp45nm node and beyond, the installation of hyper-NA ArF-immersion tools with low-k1 technique is the key issue. With this, DFM (Design For Manufacturability) is the key technology and a continuous approach of systematic DFM technique is important in order to reduce chip cost. Also, Mask DFM is needed to realize cost-effective low-k1 process and it drives reasonable mask cost and TAT. In order to reduce mask cost in device development and small volume production, we expect greatly that maskless lithography (ML2) become a leading tool in lithography.

The goal of the present study was to investigate and quantify reticle stress birefringence in exposure conditions. Birefringence can arise in fused silica photomask substrates due to their state of stress, and cause optical effects such as phase front distortion, ray bifurcation, and polarization changes. These effects potentially produce image blurring and illumination non-uniformity, leading to lower resolution and CD variations, respectively. The main sources of substrate stress studied were the absorber stack, the mounting of a pellicle, and the impact of initial reticle bow when chucking in an exposure tool. Jones calculus was used to relate birefringence at discrete locations in the reticle, derived from the state of stress, to the net birefringence experienced by light passing through the mask. Experimentally-obtained birefringence data as well as analytical calculations of stress birefringence caused by known states of stress were used to validate the models. These results can then be compared to photomask birefringence specifications or employed in optical simulations to determine the precise impact of this substrate stress birefringence.

The importance of advanced e-beam writing system and chemically amplified resist (CAR) coated blank is increasing gradually in high-end grade photomask manufacture according to CD embodiment of 90 nm and beyond technology node requiring because of the shrinkage of design rule in the semiconductor industry. However, many studies have been reported that CAR has several troubles and especially, CAR sensitivity change is occurred by airborne molecular contamination (AMC). So, the storage life of CAR coated blank is shortened. This problem may cause the difficulty of high-end grade photomask manufacture because it is hard to secure stable mean to target (MTT) and CD uniformity by sensitivity change, T-top profile and footing profile. Therefore, the purpose of this paper is to investigate the storage life extension for high performance CAR coated blank through improvement of the packing materials. Firstly, a variety of packing materials were collected and the selected packing materials were analyzed by Automatic Thermal Desorption Gas Chromatograph/Mass Spectrometer (ATD GC/MS) and Ion Chromatograph (IC) to examine AMC generated from the packing materials. As a result, molecular condensables such as alcohols, hydrocarbons and fatty acids were detected and molecular acids and molecular bases those are NH₄+, Cl^-, NO_x^- and SO_x^- were also detected from the packing materials, respectively. From the above results, we selected the best packing materials which generated the least AMC and the worst packing materials which generated the most AMC. Additionally, we verified photomask process with CAR coated blanks which were packed with those packing materials with post coating delay (PCD) by 50 kV e-beam writing system. In consequence, dose to clear (DTC) showed 4.6 μC/cm² at 0 day PCD for both of the best and the worst packing materials of CAR coated blank. After 90 days PCD, DTC variation was only 0.4 μC/cm² for the best packing materials, but DTC variation of 4.0 μC/cm² showed in the worst packing materials. There was 10 times difference in DTC variation between the best and the worst packing materials. As well as, the CD variation at 0.5 μm dense line presented less than 5 nm movement for 90 days PCD.

FEP-171 resist is commonly used both together with 50 keV VSB and DUV laser mask writers. To improve resolution and other lithographic parameters, the industry has strived towards thinner resist and absorber films on the mask blank. The chrome thickness and etch resistance limit how thin the resist can be. The NTAR7 (730Å) chrome was optimized for binary masks for 193 nm lithography, while NTAR5 (590Å) chrome is used for attenuated PSM blanks with a MoSi absorber beneath the chrome film. Resolution and lithographic performance can be improved further by integrating improved processes, including PEB, development and dry-etch. Micronic has in a series of papers described improvements to the FEP-171 process in combination with different chrome films and the SLM-based DUV (248 nm) Sigma7300 mask writer. The thickness of FEP-171 for Sigma7300 has been optimized for NTAR7 chrome and improvements have been described for the PEB and dry-etch process of the FEP-171/NTAR7 blanks. In this paper we describe the FEP-171 process development further. We have investigated improvements to the develop process for FEP-171/NTAR7 blanks using Design of Experiments (DOE) and a Steag Hamatech ASP-5000. Improved performance on mask, especially for CD linearity and clear-field/dark-field deviation, was achieved using the resulting development recipe together with the Sigma7300. Better than 5 nm (range) CD linearity in chrome was demonstrated for isolated spaces in the range 200-1400 nm. This work also covers a process study of FEP-171 on NTAR5 chrome. The resist thickness was optimized to 3200Å for the Sigma7300 and the performance was tested in terms of resolution, resist profile, CD linearity and CD uniformity. Resolution of 120 nm isolated lines and 140 nm isolated spaces was demonstrated, as well as 4 nm (range/2) global CD uniformity.

We have observed that increasing the thickness of the resist can improve the critical dimension uniformity (CDU) in electron beam lithography. This is our first experimental demonstration that increasing the acid generation in the resist by incident electrons is a pathway to reduce the effect of shot noise on CDU. The measurements were made with our Quadra raster shaped beam lithography system. The resist was REAP 200, a chemically amplified resist. The thicknesses were 200, 300 and 600 nm. The phenomenon is consistent with our model prediction that there would be a reduction of the shot-noise-induced CDU as the number of acid molecules generated in the chemically amplified resist increased with the resist thickness. We used the model to estimate the acid generation efficiency and the resist blur. We have also observed deviations from this trend in the thick resist (600 nm) suggesting complexity that may not be explained by the model. We are continuing our investigation to confirm these preliminary results.

In order to reduce mask making costs and improve wafer printability it is advantageous to determine machine parameters that will create highest probability of successful mask yield and mask image at CD and inspection. Proper simulation of actual product database helps to define the optimum e-beam machine settings for maximum probable yield and best mask pattern including OPC structures. In this paper we study the basic capability of the Nu-Flare E-beam mask writer emulation taking into account mask processing effects such as PEB. Analysis of how well software emulates the actual PEC corrections applied in the mask writer is necessary in predicting proper initial and subsequent machine settings for optimum yield and OPC structure fidelity. Comparisons of the Nu-Flare PEC emulation against actual mask PEC patterns on chrome masks are presented. Excellent agreement is found to experimental data when the PEC algorithm is modified to keep dose to the dense line pattern constant for any given setting of the eta PEC parameter.

In this paper, an Energy Intensity Distribution (EID) model considering dose latitude for Variable Shaped Beam (VSB) has been developed. η values (i.e. back-scattering ratio) versus dose and process threshold have been investigated by using the EID model. Additionally, a new procedure to find optimum PEC values (η) taking into account of the process threshold is proposed through simulation. For fogging effect correction, we have adopted a Gauss model and created a new simulation algorithm to find the most suitable parameters regarding η value, process threshold, dose and the EID model.

Predicting variations of critical dimensions (CDs) during a dry etching process is highly desirable in order to reduce cost and shorten fabrication time. Microloading and macroloading effects contribute to CD variation. Variation of pattern density and plasma distribution over the photomask are the main reasons for variation of etch rates. Pattern dependent error is the most important. TRAVIT is a dry etch simulation tool that has been developed to simulate etch profiles, etched linewidths, and CD variations resulting from dry etching. The software takes a GDSII pattern and determines if the CD variation is within the prescribed tolerance or if the pattern needs additional correction, and to what degree. In this way, an expensive writing of a high end mask, its dry etch, and metrology can be replaced by a simulation to avoid actual fabrication of a mask. Examples of simulations including variable ICP power, physical and chemical etch components, and optimization of a sidewall, bias, and CD variation are presented.

Photomask lifetime has become a challenge since the introduction of high volume manufacturing 193nm photolithograph. Photomask lifetime is being impacted by a broad range of environmental and process factors resulting in inorganics crystals and organic contaminants formation as well as pellicle lifetime issues. Extensive work has been published on strategies for reduction of inorganic crystals photoinduced defects formation mainly focusing on photomask clean process improvements. This paper will focus on identifying root causes for photoinduced contaminants forming within the pellicle space area as well as identify environmental factors which have the potential of impacting pellicle membrane longevity. Outgasing experiments coupled with 193nm laser exposure tests were conducted to decouple and rank reticle/pellicle storage materials as well as pellicle outgasing contributors to photoinduced defects and identify factors impacting pellicle membrance longevity. Analytical test were conducted to compare the relative levels of reticle storage materials and pellicle outgasing contaminants. Experiments aimed at quantifying the fab environment contribution to photoinduced defects formation and impact on pellicle membrane lifetime will be discussed. Environmental conditions minimizing external contributing factors impacting photomask front side photoinduced defects formation and pellicle membrance longevity will be suggested.

CD(Critical Dimension) Non-Uniformity on a mask is normally separable into global and local CD errors by means of their error sources. In general a global CD error trend on a mask shows the properties of each process. On the other hand, local CD errors on a mask are pretty much random and caused from mainly measurement errors, LER(Line Edge Roughness), and litho-shot errors. However, because of its difficulty to pin point the sources of errors and correct them, the local CD errors are required more attention. A Global CD error trend on a mask can be classified into several groups. One originating from vacuum delay, lithography error, bake and etch process will cause a side error trend on a mask. Others are fogging, radial trends of develop, and etch loading. In order to classify all those global CD errors and local CD errors, the proper monitoring mask must be required. The works on this paper mainly focalize on minimizing global CD error trends on a mask by separating and analyzing error components with proper monitoring system of each process. We therefore, provide a monitoring mask designed for efficiently representing global and local CD errors in more detailed fashion which can analyze CD errors of each process and make feed-back to each process in order to improve each process of mask manufacturing.

This paper describes the mechanism and cleaning results of a dry cleaning technology using CO₂ cryogenic aerosols. The cleaning mechanism relies on momentum transfer from the aerosol particles to overcome the force of adhesion of the contaminant particles on the surface. Particle removal is possible without degradation or etching of underlying film or the need for drying with IPA as in wet cleaning. A theoretical model of particle removal based on momentum transfer is described, predicting higher removal efficiency for sub-micron particles compared to larger particles. Experimental results with Si₃N₄ particles on silicon wafers show that removal of sub-micron particles is 10% higher than larger particles up to 30 μm, as predicted by the model. The paper also shows experimental results of various types of contaminant particle removal in photomask cleaning. Results of post mechanical repair cleaning of photomasks show effective removal of the quartz particles without damage to the adjacent chrome lines. Inorganic contaminants such as ammonium sulphate, commonly known as "haze", is removed by cryogenic aerosol cleaning with 99% efficiency as seen using optical inspection tool. The effect of cleaning on the phase and transmission of the mask is measured with multiple cleaning. The results show that over 16 cleaning cycles, the change in transmission is 0.04% an the change in phase is 0.37°. Thus a non-invasive cleaning for sub-micron particles from photomasks is possible with CO₂ cryogenic aerosols.

Progressive mask defect problems such as crystal growth or haze are key yield limiters at DUV lithography, especially in 300mm fabs. With the high energy photons involved in DUV lithography and large wafer size requiring longer continuous exposure of masks, chances of photochemical reaction increases significantly on the masks. Most of the work published on this subject so far has been focused on defect growth on clear area (on the pattern surface) and on the back-glass of the mask. But there is a new generation of growing defects: crystals that grow on the half-tone (MoSi) film or on the chrome film, on the pattern side of the mask. It is believed that the formation mechanisms and rates are different for these new types of crystals. In light of this instability of masks in volume production, it becomes more important to understand the nature of such defects. The purpose of this investigation is to characterize the nature of these new defect growths and to understand the possible formation mechanisms involved in such problems.

Resist designing for mask-making has been carried out basically using Si-wafers or chrome-coated Si-wafers, and its baking has been done for 60 to 90 seconds which was used for the wafers generally. There is a definite difference that 6025 mask-substrates (6025s) require 7.5 minutes or over to achieve 150deg.C and such, depending on a baking system configuration though, while the wafers require only 30 seconds or less, due to differences in thermal properties and in thickness between the two substrates. Resist baking conversion, by the way, is generally accomplished by adjusting the 6025s surface temperature to the wafers. Meanwhile, resist baking conversion in time, including ramping up and cooling down speed (or slope), seems not to be considered carefully between the two substrates so far. Recently, we experienced a difficulty that an essential performance of a newly designed trial resist of a low activation energy type CAR, which had been designed and developed using the wafers as usual, was not shown on the 6025s due to deteriorating in contrast, i.e. gamma value as well as remaining resist thickness in un-exposed area (dark erosion). This seemed to be due to a particular long baking for 10min. This report describes a trial and its results to convert the baking condition from the wafers to the 6025 mask-substrates, and also brings up some issues found in the resist baking conversion or adjustment.

As the design rule with wafer is tightening to sub-100nm, the specification of Mask CD uniformity is steeply tightened too. For instance, according to 2004 ITRS Roadmap updated, the specification of DRAM's CD uniformity requires less then 7nm on 80nm nodes in Yr. 2005. In order to satisfy that specification, it is important to analyze various factors such as e-beam machine error, heating effect, fogging effect, proximity effect, and process errors which cause CD non-uniformity in the mask. In this paper, a simulation method will be introduced to calculate the local and global heating effect by applying DP(Distributed Processing). First, experiments were performed to see heating effects on mask CD uniformity. In case of the ZEP process with 50KeV exposure, the CD error caused by heating effect amounted to 45nm in worst case. Second, heating effect was simulated using DP. Recently, most simulators have been required high accuracy. However, it is inevitable to spend more calculation time. To improve that problem, DP has been adopted in many softwares. In this paper, MPI(Message Passing Interface) library was applied to simulate heating effect. Finally, the experiment and simulated results were compared. As a result, simulation results could explain the CD errors investigated on our experiment. In our experiment, 2D simulation is sufficient to expect CD errors caused by resist heating effect.

CAR(Chemically amplified resist) is widely used in 50keV VSB (Variable Shaped Beam) e-beam process in photomask manufacturing due to its advantage of high sensitivity which gives to reduced writing time compared to non-CAR. The 10kV raster e-beam system, however, is spread out already worldwide and plays a important role till now in middle grade mask-making. Conventionally the non-CAR like ZEP7000 has been applied to the 10kV raster e-beam system and it gives good performance for raster scan e-beam system. In mass production, sometimes, maintaining two kinds of resist simultaneously of CAR and non-CAR are inefficient strategy to the mask house which has limited resources. This situation makes the authors to apply CAR to the 10kV raster e-beam process. Generally, the grid of 10kV raster e-beam(MEBES) is large and limited compared to the current VSB grid. Historically, many layout data is designed already based on the large limited grid and this gives to limited sizing value. Moreover, it is difficult to control exposure dose in raster e-beam system and control bias with develop time in CAR process. These situations make more difficult CAR application to raster e-beam system under the simple mask data preparation strategy. In this paper, some critical problems will be discussed in isofocal process making for raster scan e-beam system. Advantage and disadvantage will be also discussed through the comparison of basic parameters such as dose margin, develop margin, and the fogging effect between the CAR and non-CAR process in 10kV raster e-beam process.

The quartz dry etch is a critical step in the manufacture of Alternating Aperture Phase Shift masks (alt-APSM). In order to maintain uniform phase shift across the mask, the etch depth uniformity has to be strictly controlled. Both the radial and linear components of non-uniformity have to be minimized. The Mask Etcher IV developed at Unaxis USA reduces both the components of non-uniformity using unique hardware adjustments. Using a fluorocarbon based chemistry, etch depth variations between different feature sizes is also minimized. With good etch depth linearity, phase shift does not vary with feature size. To achieve this, etched quartz structures need to have good selectivity to resist / chrome and vertical sidewalls. Etch depth uniformity was measured using an n&k1700 RT and etch depth linearity was measured using an AFM. Etched quartz structure morphologies are observed using a SEM. After preliminary screening experiments, an optimized hardware suite and process conditions that produce good etch depth uniformity, linearity and quartz profiles with vertical sidewalls and minimum microtrenching is determined.

To improve Critical Dimension (CD) uniformity is an important task in 65nm generation photomask and the beyond. It is known the develop process generates the CD variation. This study is focused on develop process. We initiated new type developer nozzle in this study to improve the CD uniformity. We devoted to improve the CD uniformity during develop process by optimizing the develop parameter through a Design of Experiment (DOE). In the first step, we chose 11 parameters (Scan speed, Dispense flow rate, Develop time, Gap between photomask surface and slit nozzle edge) for L12 test to make sure which can control process. After the L12 test we selected 3 parameters (During develop dry/not, During develop rinse/not and scan times) for L4 test to optimized this experiment. Dependence on the L12 and L4 result, we get the best recipe. With the best recipe from L12 and L4, we verified CD uniformity in our production pattern. The CD target was 0.36um and CD uniformity was 6.8nm (range). We also studied about the relation of CD uniformity and process bias with the parameter.

Recently, the design of integrated circuits has become more and more complicated due to higher circuit densities. In particular for logic applications, the design is no longer uniform but combines different kinds of circuits into one mask layout resulting in stringent criteria for both wafer and photomask manufacturing. Photomask CD uniformity control and defectivity are two key criteria in manufacturing today’s high-end reticles, and they are both strongly impacted by the mask developing process. A new photomask develop tool (ACT-M) designed by Tokyo Electron Limited (TEL) has been installed at the Advanced Mask Technology Center (AMTC) in Dresden, Germany. This ACT-M develop tool is equipped with a standard NLD nozzle as well as an SH nozzle which are both widely used in wafer developing applications. The AMTC and TEL used the ACT-M develop tool to adapt wafer puddle develop technology to photomask manufacturing, in an attempt to capture the same optimum CD control enjoyed by the wafer industry. In this study we used the ACT-M develop tool to examine CD uniformity, local loading and defect control on P-CAR and N-CAR photomasks exposed with 50keV e-beam pattern generators. Results with both nozzle types are reported. CD uniformity, loading, and defectivity results were sufficient to meet 65-nm technology node requirements with these nozzles and tailored made develop recipes for photomask processing.

We have proposed and modified a model of drying process of polymer solution coated on a flat substrate for flat polymer film fabrication and have presented the fruits through Photomask Japan 2002, 2003, 2004 and so on. And for example numerical simulation of the model qualitatively reappears a typical thickness profile of the polymer film formed after drying, that is, the profile that the edge of the film is thicker and just the region next to the edge’s bump is thinner. Then we have clarified dependence of distribution of polymer molecules on a flat substrate on a various parameters based on analysis of many numerical simulations. But above fruits are wholly based on theoretical and numerical studies and verification of the modified model by experiment has not sufficiently done yet except for one by the experiments of dependence of polymer molecule’s distribution on vaporization rate. In this paper, we verify the modified model by a few kinds of experiments. At first, we verify the dependence of polymer molecule’s distribution on intrinsic viscosity by experiment. In the concrete, we verify the characteristics that the smaller intrinsic viscosity is, the lower height of the edge’s bump is, the shallower depth of the valley next to the edge’s bump is and the more flat profile of polymer molecule’s distribution is at central region. Then we verify the dependence of polymer molecule’s distribution on the ratio of molar volume of solute to one of solvent by experiment.

For the new Schott EAPSM Material, comprising a Ta/SiO₂/Cr stack, a patterning process has been developed. The material offers the advantage of an independent adjustment of phase shift and transmission and is applicable for different wavelengths. Because of very homogenous Ta and SiO₂ films and perfect etch selectivities it has been achieved a phase shift uniformity of 1.1° and a tight transmission deviation of 0.34% (absolute) across the entire mask. First dry etch process development has been focused on profiles and selectivities. The influence of process parameters on sidewall angle, profile bow, resist loss and Cr loss of the three patterning steps are shown. We have achieved excellent selectivities and a final sidewall angle of > 88°. The aerial image contrast of the first test plate is comparable to known attenuated phase shift material.

An increasingly tighter set of mask specifications requires new equipment, process improvements, and improved e-beam resist materials. Resist profiles, footing behavior and line edge roughness (LER) have strong impacts on CD-uniformity, process bias and defect control. Additionally, the CD stability of e-beam resists in vacuum contributes to the final CD-uniformity as a systematic error. The resolution capability of the resist process is becoming increasingly important for slot contact like features, which are expected to be applied as clear assist features in contact hole layers at the sub 100nm technology node (1x)¹. Three e-beam sensitive pCAR resists from different vendors were investigated in terms of resolution and pattern quality, PED stability, PEB sensitivity, dose latitude, CD-uniformity and line edge roughness. As reported here, all three pCARs showed improvements in all of these areas. Future work with these pCAR resists will focus on defect density, PCD, and CD uniformity.

The second level exposure of Alternating Phase Shift Mask has to be accomplished by e-beam lithography. However, e-beam writing on structured open chrome layers may induce severe charging and yields to deteriorate overlay accuracy. In case of charging problems, applying of conductive top coats on resists help to reduce the distortion of the second layer. ESPACER makes the conductive layer on the e-beam resist and prevent a positioning error during e-beam writing by its shield effect. However, ESPACER required removal of its topcoat before post-exposure bake (PEB) because of the undesirable effect to the resist, due to the acid diffusion from the ESPACER film to high sensitive Chemical Amplified Resists (CARs). Our investigations were focused on the combination of the representative positive tone CAR: FUJIFILM ELECTRONIC MATERIALS CO., LTD and the new-type ESPACER called ESPACER 300F. ESPACER 300F was possible to use the PEB process before its removal, improved by exchanging a lower mobility surfactant than before. This material also had a good wettability, a low resist-thickness losses and kept good pattern shapes of the resist. Additionally, ESPACER 300F have little influence in both overlay accuracy at the variety of pattern density and sensitivity of the resist, therefore it would be the good material for making reticles for 65nm node and beyond.

Knowledge of particle removal during the mask cleaning was transferred to the blank cleaning and vice versa. The experiments are focusing on a variety of blank substrates (glass substrates, chrome on glass blanks and phase shift mask blanks substrates). The principal equipment concept and the process optimization strategies for cleaning of those different kinds of blank substrates are presented. With a fixed process flow, including UV-treatment, Fulljet and MegaSonic treatment, Rinse and Dry, process parameters are varied to define the optimum process conditions. Criteria for an optimum process are particle removal efficiency in general and optical integrity for phase shift mask blanks in particular. The particle removal efficiency for all investigated blank types is within a range of 96-100%. Especially for Ta/SiO₂ phase shift mask blanks we demonstrate that during the cleaning process the optical properties only change by 0.07° phase loss and 0.01% transmission loss per cleaning cycle, respectively.

We have chosen a combination of thermal treatment and hot D.I water rinsing as a part of methodologies to remove chemical residuals on mask surface. A new step of thermal treatment has been inserted in our standard manufacturing procedure for EAPSM. After thermal treatment, Ion Chromatography (IC) methods are used to confirm the surface cleanliness. As a result of our study, thermal treatment can considerably reduce residuals (e.g. ammonium, sulfuric and others) on mask surface. So, it could be suggested that the thermal treatment is an effective way to minimize residual ions. Also, in order to understand on haze source and mechanism, we investigated on artificial acceleration method for haze formation. We preceded haze acceleration test by using modified haze acceleration system (UV 172nm light). From the acceleration test, we found that humidity, irradiation energy, concentration of chemical residuals are dominant factors of haze formation.

Today, the industry is suffering from the consequences of residue and contaminants on the mask surface as they significantly affect the printing quality of the reticle. Thus a good control of the mask cleanliness via its optical properties is becoming essential to minimize this impact. The AUV5500 is specifically addressing organic contaminants. The principle of the tool set-up, its process functionality is presented. Preliminary data on the impact of organic contaminants on binary and embedded phase shift masks optical properties and the tool cleaning capability are analyzed and discussed.

In lithography systems, the need for increased resolution requires larger numerical apertures and shorter illumination wavelengths. Both of these requirements cause a reduction in the system’s depth of focus resulting in the need for flatter photomasks with specifications under 0.5 micron. Currently the mask blank substrates are measured after polishing, and all subsequent process steps are assumed to have little or no impact on the final mask flatness. With today’s ever tightening flatness requirements, this assumption can no longer be taken for granted. This paper investigates the distortions seen at the reticle surface induced by the mounting of a standard optical pellicle frame to the photomask and relates these distortions to the pellicle frame flatness. The experiment involves using a set of mask blanks that are better than 0.5 micron flatness with similar form errors before attaching the pellicle. Two groups of pellicles are used to create two distinct frame flatness populations: one set assumed to be within specification as purchased; and a second set of pellicles that are intentionally distorted. Mask flatness is compared before and after mounting the pellicles, and all frames are measured for flatness. Correlation between the frame flatness and form to the measured distortion on the reticle surface are made and discussed, and a practical guideline for selecting an appropriate blank flatness and pellicle flatness to achieve the desired reticle flatness is suggested.

Progressive mask defect problems such as crystal growth or haze are key yield limiters for DUV lithography, especially in 300mm fabs. Even if the incoming mask quality is good, there is no guarantee that the mask will remain clean during its production usage in the wafer fab. These progressive defects must be caught in advance during production in the fabs. The ideal reticle quality control goal should be to detect any nascent progressive defects before they become yield limiting. So, a high-resolution mask inspection is absolutely needed, but the big question is: “how often do fabs need to re-inspect their masks”? This re-inspection frequency should ideally be the most cost-effective frequency at which there is minimum threat for a yield loss. Previous work towards finding a cost effective mask re-qualification frequency was done prior to the above mentioned progressive defect problem that industry started to see at a much higher rate during just the last few years. Other related recent work was done 2004 BACUS conference which is dedicated to DRAM fab data. In this paper a realistic mask re-qualification frequency model has been developed based on a large volume of data from an advanced logic fab. This work will compliment previous work in this area done with the data from a DRAM fab. Statistical methods are used to analyze mask inspection and product data, which are combined in a stochastic model.

Defect is a killing factor in photomask fabrications. For 65nm node photomask fabrication, even smaller than 1 um particle can cause hard-to-repair defect. And it is not easy to find the defect source and solve it. For this reason, the process monitoring system that shows us current defect trend rapidly and effectively is highly required. At the same time, this system can be used for verifying the process stability and detecting unusual signals in process.

In the field, each customer uses their owned designed reticle case as for shipping, storage. To modify the case is so expensive that it is very difficult to improve, especially in time respect. At the blank suppliers, they ship their mask blanks packing into their owned designed multiple shipper, however the market needs single shipper with next generation blanks to prevent from particle and outgas of case material damage. At the mask shops, most of them use MP567 (Trade mark of Dainichi Shoji K.K.) single case which was designed about 15 years ago to ship their products to their customers. It is not designed for robot handling, so contamination from manual handling makes reticle damaged. Adhesive tape is also required to seal it, so chemical contamination will be occurred on quartz glass, i.e. haze. At the IC fabs, scanner case such as Nikon, Canon and ASML case is the most common in their process. However these cases are not airtight, so they cannot be handled under class 10000 circumstances. RSP (Reticle SMIF Pod) is airtight case and has a capability of automatic transportation, however it is very expensive compared to other cases. We develop new mask case named Universal Reticle Pod (URP) at affordable price so as to be used as shipping, storage and process case, so we would like to report its performance in this paper.

We investigated the specifications of scanning electron microscope required for the lithography simulation based on the edge data extracted from an actual reticle pattern in the assurance of reticle pattern in which two-dimensional optical proximity correction is applied. Impacts of field of view, positioning error and image distortion on a lithography simulation were studied experimentally. For the reticle pattern assurance in hp90, the field of view of larger than 16 μm squares, the positioning error within +/- 1 μm and the magnification error of less than 0.3% are needed. Under these conditions, wafer image can be predicted with sufficient accuracy by the simulation.

With the exponential increase in output database size due to the aggressive optical proximity correction (OPC) and resolution enhancement technique (RET) required for deep sub-wavelength process nodes, the CPU time required for mask tape-out continues to increase significantly. For integrated device manufacturers (IDMs), this can impact the time-to-market for their products where even a few days delay could have a huge commercial impact and loss of market window opportunity. For foundries, a shorter turnaround time provides a competitive advantage in their demanding market, too slow could mean customers looking elsewhere for these services; while a fast turnaround may even command a higher price. With FAB turnaround of a mature, plain-vanilla CMOS process of around 20-30 days, a delay of several days in mask tapeout would contribute a significant fraction to the total time to deliver prototypes. Unlike silicon processing, masks tape-out time can be decreased by simply purchasing extra computing resources and software licenses. Mask tape-out groups are taking advantage of the ever-decreasing hardware cost and increasing power of commodity processors. The significant distributability inherent in some commercial Mask Synthesis software can be leveraged to address this critical business issue. Different implementations have different fractions of the code that cannot be parallelized and this affects the efficiency with which it scales, as is described by Amdahl’s law. Very few are efficient enough to allow the effective use of 1000’s of processors, enabling run times to drop from days to only minutes. What follows is a cost aware methodology to quantify the scalability of this class of software, and thus act as a guide to estimating the optimal investment in terms of hardware and software licenses.

The continuous drive of the semiconductor industry towards smaller features sizes requires mask manufacturers to achieve ever tighter tolerances for the most critical dimensions on the mask. CD uniformity requires particularly tight control. Equipment manufacturers and process engineers target their development to support these requirements. But as numerous publications indicate, more sophisticated data correction methods are still employed to compensate for shortcomings in equipment and process or to account for the boundary conditions in some layouts that contribute to process deviations. Among the corrected effects are proximity and linearity effects, fogging and etch effects, and pattern fidelity. Different designs vary by pattern size distribution as well as by pattern density distribution. As the implementation of corrections for optical proximity effects in wafer lithography has shown, breaking up the original polygons in the design layout for selective and environment-aware correction yields increased data volumes and can have an impact on the data quality of the mask writing data. The paper investigates the effect of various correction algorithms specifically deployed for mask process effects on top of wafer process related corrections. The impact of MPC flows such as rule-based linearity and proximity correction and density-based long range effect correction on the metrics for data preparation and mask making is analyzed. Experimental data on file size, shot count and data quality indicators including small figure counts are presented for different correction approaches and a variety of correction parameters.

Application of DFM (Design for Manufacturability) techniques to the design of random logic metal-layers with million nodes is indispensable for manufacturing semiconductor devices with the node of 90 nm and the bellow. Critical dimension lines corresponding to minimum design rules do not have sufficient process margin due to the presence of focus variation of ArF scanner. This often induces resist-line narrowing, which causes circuit-speed degradations and Cu opens, finally leading to serious yield losses. There are numerous studies on techniques to expand the process margin, such as the placement of dummy and assist patterns. However such techniques can not sometimes be applied due to restrictions of design rule. We note that the presence of such augmented patterns increases the wire capacitance and mask TAT (turn around time). We have developed an automatic layout-pattern generation method which extends the line-end of patterns adjacent to isolated patterns. This resulted in a significant improvement of the process margin of isolated patterns.

Resolution enhancement techniques (RETs) such as optical proximity correction (OPC), phase-shifting masks (PSM), sub-resolution assist features (SRAF) have become essential components in the sub-90nm silicon manufacturing process. For the 65nm generation, alternating phase shift masks (Alt-PSM) is recognized as a proven wafer imaging technique. The large process window and hence stable process control is one of the key properties which make it the most viable approach for 65nm production compared with other RET approaches. On the mask making side, the good mask error enhancement factor (MEEF) performance of the Alt-PSM is a big plus as it makes the wafer CD control less susceptible for CD errors on the mask. Even though the benefits of Alt-PSM are well known, the reticle cost and manufacturing challenges have impeded its extensive adoption. In this work, we explore a methodology to reduce the Alt-PSM mask write time vis-a-vis cost, through certain data optimization techniques.

Contact and via layers are becoming more critical than before from lithography point of view due to the fact that the contact and via sizes for advanced devices are falling into deep sub-wavelength ranges. In this study, we will demonstrate several different methodologies for contact and via CD variation check and contact/metal overlay checks on the post-opc data using a model based verification software platform. Our study reveals that the full chip verification for the contact and via layers is necessary achievable to guarantee the mask data quality and to prevent catastrophic pattern errors resulting from improper OPC corrections. Good scalability of the software methodology and platform makes it possible to do the full chip verification with reasonable turn around time.

Model based full-chip lithography verification has been proven as a mask sign off solution to prevent patterning failures caused by design/OPC (Optical Proximity Correction) before mask data tape out. Furthermore, as the fast turn around time is achieved through scalable distributed processing for very large data after mask synthesis conversion such as assist feature and OPC, model-based full-chip verification can take advantages of RET (Resolution Enhancement Technique)/OPC recipe development. In previous studies, we introduced the full-chip verification methodologies for mask sign off flow in production and for RET/OPC optimization flow in process development stage for sub-wavelength lithography processes in general. In this paper, we demonstrated the layer-specific verifications for critical layers for 65nm lithography process development. For poly layer, we performed various types of checks such as fatal pinch/bridge hotspots, CD variations, line-end/space-end errors, assist feature printability, MMEF (Mask Error Enhancement Factor) and geometrical (Mask Rule/structural) checks considering the mask manufacturing constraints. We compared hyper NA (Numerical Aperture)illumination using immersion lithography with the double expose alternating PSM (Phase Shift Mask) lithography. For metal layer, various full-process window coverage verification methodologies were discussed.

The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman et al. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.

It has been demonstrated that the write time for 50keV E-beam masks is a function of layout complexity including figure count, vertex count and total line edge. This study is aimed to improve model fitting by utilizing all the variables generated from CATS. A better correlation of R² = 0.99 was achieved by including quadratic and interaction terms. The vertex model was then applied to estimate write time of various nano-imprint templates. Accuracy of the vertex model is much better than the numbers generated from E-beam tool software. A 90nm test layout was treated with a mask optimization (MO) algorithm. A 26% write time reduction was observed through shot count reduction. The advanced features of the new generation E-beam writing tool combined with mask layout optimization, allows the same level of mask cost even though the capital cost of the new tool set increased 25%.

OASIS(Open Artwork System Interchange Standard) format was investigated for various logic device datas. In this investigation, the change in the processing time of the confirmation of the content of compression in OASIS and the mask data processing were confirmed. OASIS format has higher data compressibility than other methods, and its compressibility is independent on the data size. It is very effective in a advanced technology device according to the above-nentioned investigations. In data storage and data handling, applying after OPC processing is quite effective.

OASIS (Open Artwork System Interchange Standard) is the new stream format to replace conventional GDSII and has become a SEMI standard 2003. Also, some EDA software tools already support OASIS. OASIS can apply not only layout design field but also photomask industory. OASIS is effective to reduce data volume even if it is a fractured data, therefore it is expected to solve file size explosion problem. From mask manufacturer's perspective, it is also necessary to consider mask layout information. In present, there are various kinds of layout information and jobdeck formats. These circumstances require complicated data handling and preparation process at the mask manufacturers. Computerized automatic process needs to be more utilized to eradicate mistakes and miscommunications at the planning department. SEMI standard P10 (Specification of Data Structures for Photomask Orders) is one of the solutions. P10 is basically intended to communicate about mask order data which include layout information. This paper reports the result of evaluation of mask data preparation unified with two SEMI standards: P39 (OASIS) and P10. We have developed a reticle pattern viewer (HOTSCOPE) which can view photomask data with combined OASIS with P10. Figure 1 shows connection between mask data formats, which include OASIS and P10 format with our reticle pattern viewer. HOTSCOPE provides reviewing mask data as a photomask image. It will interface between device manufacturers and mask manufacturers.

We have been developing intellectual properties (IP) protection software using OASIS format. In the Photomask Technology 2004 we presented that by taking advantage of repetition presentation of OASIS, it becomes possible to express arrayed patterns without any generation of new cells, which also brings less overhead and further compaction of the result file. As a result, we could rebuild the hierarchy without cell generation and reduce the output file size. In this paper, additionally we have applied a unique compression function CBLOCK defined in OASIS format. CBLOCK can compress any part of OASIS file. The experimental results show that there are no redundant cells generated and the file size has become approximately 20 times smaller than conventional methods.

Recently, photomask pattern feature have become different from LSI layout pattern feature by the OPC process and CMP DUMMY pattern insertion. And then, photomask pattern data volume is very large compared with LSI layout pattern data volume. Therefore, in the usual JOBDECK pattern viewer software, it is difficult to draw those huge pattern data smoothly and quickly. Moreover, various proposals of RET (Resolution Enhancement Technology) are made from various companies and organizations, and it is discussed by various societies. According to the RET, mask pattern feature and structure have been more complicated than the present pattern, and mask difficulty and mask cost might be going to increase and will have great anxiety. Photomask pattern viewer, HOTSCOPE which we developed isn't an only high speed photomask pattern viewer and analyzer, but also can superpose and observe some other mask format pattern and GDS2 format pattern by changing pattern magnification and mirror processing by itself. And HOTSCOPE is the tool which fully incorporated the function required for mask manufactures, such as a plan of a mask, preparation of JOBDECK, and the mask pattern analysis purpose.

Cost control of new product mask sets for the sub-100 nm technology nodes is one of the great challenges of IC manufacturing. Attempts to reduce the mask expenses include placing multiple design layers on one reticle plate (N layers per plate, NLPP). This approach cuts the cost of a full product mask set by up to N times compared to the standard one where each design layer uses a separate mask (one layer per plate, 1LPP), but is often met with resistance from Manufacturing as it limits fab throughput. The throughput reduction is due to the N-times larger number of exposures per wafer and the resulting longer tool (stepper) time. In addition, the multi-layer masks may compromise overlay and degrade alignment yield. This work helps understand manufacturing challenges, cost models, and technical issues related to the NLPP scenarios.

Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k₁ lithography manufacturing. The manufacturing implementation of SB so far has been mainly based on rule-based approach. While this has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML Technology from ASML MaskTools. In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Interference Mapping Lithography (IML) is the latest innovation to extend optical imaging solutions to contact hole printing. This approach optimizes the placement of assist features to enhance the process window of the contact hole layer. However, the printing of assist features is a concern of the IML technology. This study presents a checking scheme to analyze the assist feature printing using the aerial image simulation. If the checking method confirms the assist feature printing, the adjustment algorithm optimizes the assist feature design. An example of a 5×5 array pattern is employed to demonstrate the methodologies; which avoid assist feature printing yet still improve the process window by adding the appropriate assist feature design.

Using a commercialized product Calibre OPC platform, optical and process models were built that accurately predict wafer-level phenomena for a sub-90nm poly process. The model fidelity relative to nominal wafer data demonstrates excellent result, with EPE errors in the range of ±2nm for pitch features and ±7 for line-end features. Furthermore, these models accurately predict defocus and off-dose wafer data. Overlaying SEM images with model-predicted print images for critical structures shows that the models are stable and accurate, even in areas especially prone to pinching or bridging. In addition, process window ORC is shown to identify potential failure points within some representative designs, allowing the mask preparation shop to easily identify these areas within the fractured data. And finally, the data and images of mask hotspots will be shown and compared down to wafer level.

An accurate process model is the linchpin of model-based Optical Proximity Correction (OPC) and Resolution Enhancement Technique (RET) synthesis. The accuracy of the resulting mask layout can be no better than that of the model. Relatively good, first-principle mathematical models exist for some process steps, such as aerial image formation, but resulting silicon is a combination of many effects, including those less well understood. Accuracy can be assured only with models anchored to observed phenomena. Process models are usually a combination of first principle elements and phenomenological components with the “right” degrees to freedom to fit the overall process. The key challenge in generating accurate models is to capture all process behavior over all conditions with a minimum number of empirical measurements. This means that models must extrapolate accurately from the specifics measured, and should be largely immune to empirical measurement noise. In this paper we describe a methodology in which to test model performance with respect to these criteria.

In this paper, we distinguish between sparse and dense simulation. We give a background on known sparse and dense simulation techniques. We propose a new “semi-dense” OPC technique which is between standard sparse, and fully dense OPC. We also discuss a fully dense OPC algorithm, in which full image grids are used to control the OPC corrections. Finally, we discuss dense verification to ensure good printing behavior through process window on the full image.

As a promising technology for sub-65nm node optical lithography, CLM(Chrome-Less Mask) technology among RETs(Resolution Enhancement Techniques) for low k₁ has been researched worldwide in recent years. CLM has several advantages, such as relatively simple manufacturing process and competitive performance compared to phase-edge PSM's. For the low-k₁ lithography, we have researched CLM technique as a good solution especially for sub-65nm node. As a step for developing the sub-65nm node optical lithography, we have applied CLM technology in 80nm-node lithography with mesa and trench method. From the analysis of the CLM technology in the 80nm lithography, we found that there is the optimal shutter size for best performance in the technique, the increment of wafer ADI CD varied with pattern's pitch, and a limitation in patterning various shapes and size by OPC dead-zone - OPC dead-zone in CLM technique is the specific region of shutter size that dose not make the wafer CD increased more than a specific size. And also small patterns are easily broken, while fabricating the CLM mask in mesa method. Generally, trench method has better optical performance than mesa. These issues have so far restricted the application of CLM technology to a small field. We approached these issues with 3-D topographic simulation tool and found that the issues could be overcome by applying phase grating in trench-type CLM. With the simulation data, we made some test masks which had many kinds of patterns with many different conditions and analyzed their performance through AIMS fab 193 and exposure on wafer. Finally, we have developed the CLM technology which is free of OPC dead-zone and pattern broken in fabrication process. Therefore, we can apply the CLM technique into sub-65nm node optical lithography including logic devices.

As K1 approaching close to 0.3, it will require combinations of all the possible resolution enhancement techniques to achieve acceptable process window. In this study, we have explored the printability of 0.11μm half pitch with 0.7NA KrF lithography. We have designed several phase shifting masks to test the feasibility of printing 0.11μm half pitch line/space and dense post structures. Line and space patterns can be printed with attenuating phase shifting mask with sufficient process window. Post printing is more challenging due to its 2D optical interference effect. Chrome-less phase shifting mask is used for post printing due to its higher contrast. We have optimized mask bias and resist process in order to gain an acceptable process window. Negative KrF resist was also explored for its post printing capability. Our current study shows that the chrome-less phase shifting mask technology is capable of pushing K1 factor close to 0.3 for post printing.

The Cr-less Phase Shift Mask (CLPSM) has been considered as one of the most practical resolution enhancement techniques (RET) solution providing low Mask Error Enhancement Factor (MEEF) for low k1 geometries for memory and logic semiconductor devices. There are several papers that show the advantages of the CLPSM compared to the other types of RET. Also the required design changes have been widely studied. Manufacturing of CLPSM requires quartz etching additionally to the COG mask process. Contrary to CLPSM, the required characteristics of the quartz etching process for altPSM are well specified. However, the required quality of the etching process for the CLPSM has not been sufficiently evaluated yet. In this paper, the impact of imperfections of the mask manufacturing process, like the effect of quartz sidewall profile, etch depth deviation and quartz trenching during quartz dry etching on mask imaging performance is investigated. Simulations were performed using Solid-CTM to investigate these effects for both mesa and trench type CLPSM for different pitches. A CLPSM mask was manufactured at AMTC to confirm the validity of the simulation through comparing the contrast deviation on various mesa and trench sizes. AIMS measurements have been performed for this purpose.

The demands on photomask pattern transfer become tighter with every advancing technology node. Transferring patterns with feature sizes below 200nm threaten to limit lithography capabilities and prohibit the extension of current 248nm and 193nm lithography techniques. One demand that jeopardizes the current technology is the degradation of line resolution at the smaller features sizes. Transferring patterns smaller than the lithography wavelength can distort the image at the wafer. One of the resolution enhancement techniques (RET) for improving this performance and extending the lifetime of current lithography methodology is chromeless phase lithography (CPL). In this work chromeless phase lithography masks have been etched using the Tetra II Photomask Etch System. Process development of the CPL etch process is discussed with emphasis on etch depth uniformity and CD profile. Effects of varying process parameters on etch performance are discussed for a typical low load patterned mask showing excellent etch uniformity range and reactive ion etch (RIE) lag. The requirements for uniformity range and RIE lag performance (both typically < 1%) require Z-depth precision on the order of the 0.25nm provided by the SNP. Non destructive CD profiling capability of the SNP is used to show the vertical sidewall etch performance. The ability to eliminate micro-trenching while maintaining excellent phase range and RIE lag is demonstrated. The capability of the Tetra II Photomask etch system to undercut the chrome hard mask during quartz etch is also demonstrated.

With ever decreasing feature sizes, the control of mask CD errors is becoming increasingly critical in order to realize a good lithographic performance. In our previous study, mask CD errors were classified on the basis of spatial frequency into the following three categories: local CD error, global CD error, and line edge roughness (LER). If the period of a mask CD error exceeds the optical proximity effect (OPE) range, the mask CD error is classified as a global CD error. If the period is almost equal to the OPE range, the mask CD error is classified as a local CD error. As compared with the OPE range, the LER has very small spatial frequency. Introducing the concept of mask enhancement factor (MEF) for local and global CD errors, we examined the ratio of local MEF to global MEF for 1-dimensional dense and isolated line patterns. In this paper, we build on our previous study, dealing with 2-dimensional rectangular patterns. In addition, we introduce the “local MEF matrix,” which reflects the characteristics of a pattern layout and aids the estimation of local CD errors. Furthermore, we discuss the required mask specifications of 2D patterns for low-k1 lithography.

MEEF (Mask Error Enhancement Factor) is the most representative index which CD (Critical Dimension) variation in wafer is amplified by real specific mask CD variation. Already, as it was announced through other papers, MEEF is increased by small k₁ or pattern pitch. Illumination system, just like lens aberration or stage defocus affects directly MEEF value, but the leveling or species of substrate and the resist performance are also deeply related to MEEF value. Actually, when the engineers set up the photo process of shrink structure in current device makers, they established minimum shot uniformity target such as MEEF value within wafer uniformity and wafer to wafer uniformity, besides UDOF (Usable Depth of Focus) or EL (Exposure Latitude) margin. We examined MEEF reduction by checking the difference in resist parameters and tried to correlate the results between experiment and simulation. Solid-C was used for simulation tool. The target node was dense L/S (Line/Space) of sub-80 nm and we fix the same illumination conditions. We calculated MEEF values by comparing to original mask uniformity through the optical parameters of each resist type. NILS (Normalized Image Log Slope) shows us some points of the saturation value with pupil mesh points and the aberration was not considered. We used four different type resists and changed resist optical properties (i.e. n, k refractive index; A, B, and C Dill exposure parameters). It was very difficult to measure the kinetic phenomenon, so we choose Fickian model in PEB (Post Exposure Bake) and Weiss model in development. In this paper, we tried to suggest another direction of photoresist improvement by comparing the resist parameters to MEEF value of different pitches.

Mask Error Enhancement Factor(MEEF) has recently become an important topic in determining requirements of process. MEEF is the ratio of the CD range on the wafer and the expected CD range due to the mask. It indicates that mask CD errors are in effect magnified during the optical transfer to the wafer. The resolution capability of a optical system is given by Rayleigh’s criterions: Resolution=k1*λ/NA, where λ is the wavelength of the light used and NA is defined as the sine of the maximum half angle(α) of diffracted light which can enter the lens. The k1 resolution-scaling factor (k1=CD*NA/λ) is a practical measure for expressing imaging feasibility of a given optical system. It is a important parameter and direct proportion to resolution requirement. For driving critical CD dimension contraction bellow 0.11μm, lower k1 factor is needed. In this work we use strong OAI (Quasar 90° ) to push k1 reach 0.29 by KrF exposure tool and analysis the MEEF value on 90nm generation. The simulation result shows the predicted MEEF value is close to 9 while using KrF to 90nm resolution and real MEEF value from exposuring Line/Space pattern on wafer data is 6.2. In such high MEEF process, it is very important to control mask CD accuracy. We bring up a test pattern of serial combinations with different Line/Space dimension with the same pitch size to reduce the mask array CD variation. Finally, we compare the process window (PW) between equal and nonequal Line/Space situation. The process window can be improved 18% while line width extends from 90nm to 95nm at fixed pitch 180nm.

The semiconductor industry is aggressively pushed to produce smaller and smaller feature sizes from their existing base of lithography systems. With the line-width of integrate circuit (IC) narrowing and ArF immersion lithography technology arising, the mask error factor (MEF) becomes a significant problem because it consumes a large anticipated portion of the CD tolerance budget. This paper discusses the mask error’s impact on the CDs of butting feature using an ArF immersion lithography system. On 65nm node, the variation of image contrast, NILS (Nominal Image Log-Slope), line width and gap width, which results from mask errors, is calculated. The mask errors include puncture, burr, blotch, and mask bias, etc. The rules of mask error’s impact on image contrast, NILS, line width and gap width are concluded. The puncture errors enlarge the gap width, while, the burr and blotch errors reduce the gap width. All mask errors can magnify the resist CD error and result in the FE windows shrinking. The relations of exposure dose and gap width according to butting pattern are presented. The variation of gap width is compensated by exposure dose’s tuning. The relations of polarization state and gap width are discussed. By adjusting polarization state, the variation of gap width, which results from mask errors, can be compensated. After polarization state adjusted, the image contrast, NILS, line width and gap width are calculated again. By comparing the image contrast, NILS, line width and gap width of butting pattern before and after compensated, the merits of adjusting the exposure dose and polarization state to compensate the impact of mask errors are presented.

For state of the art technologies, rule based optical proximity correction (OPC) together with conventional illumination is commonly used for contact layers, because it is simple to handle and processing times are short. However, as geometries are getting smaller it becomes more difficult to accurately control critical dimension (CD) variations influenced by nearby pattern. This applies in particular for irregularly arranged contact holes. Here simulation based OPC is more effective. We present a procedure for application of simulation based OPC for a 193 nm lithography contact hole layer with rectangular contact holes of different sizes in different proximities, using attenuated phase shift masks. In order to further improve the accuracy of the simulation based OPC process, characteristics of the mask, like mask corner rounding are incorporated in the OPC process. We build an OPC model, use it for OPC processing of DRAM design data and investigate the process window of the printing contacts. The results show an overlapping process window for length and width of isolated and dense small contact holes of different length and width, which is sufficient for volume production.

Leading resist calibration for sub-0.3 k₁ lithography demands accuracy <2nm for CD through pitch. An accurately calibrated resist process is the prerequisite for establishing production-worthy manufacturing under extreme low k₁. From an integrated imaging point of view, the following key components must be simultaneously considered during the calibration - high numerical aperture (NA>0.8) imaging characteristics, customized illuminations (measured vs. modeled pupil profiles), resolution enhancement technology (RET) mask with OPC, reticle metrology, and resist thin film substrate. For imaging at NA approaching unity, polarized illumination can impact significantly the contrast formation in the resist film stack, and therefore it is an important factor to consider in the CD-based resist calibration. For aggressive DRAM memory core designs at k₁<0.3, pattern-specific illumination optimization has proven to be critical for achieving the required imaging performance. Various optimization techniques from source profile optimization with fixed mask design to the combined source and mask optimization have been considered for customer designs and available imaging capabilities. For successful low-k₁ process development, verification of the optimization results can only be made with a sufficiently tunable resist model that can predicate the wafer printing accurately under various optimized process settings. We have developed, for resist patterning under aggressive low-k₁ conditions, a novel 3D diffusion model equipped with double-Gaussian convolution in each dimension. Resist calibration with the new diffusion model has demonstrated a fitness and CD predication accuracy that rival or outperform the traditional 3D physical resist models. In this work, we describe our empirical approach to achieving the nm-scale precision for advanced lithography process calibrations, using either measured 1D CD through-pitch or 2D memory core patterns. We show that for ArF imaging, the current resist development and diffusion modeling can readily achieve ~1-2nm max CD errors for common 1D through-pitch and aggressive 2D memory core resist patterns. Sensitivities of the calibrated models to various process parameters are analyzed, including the comparison between the measured and modeled (Gaussian or GRAIL) pupil profiles. We also report our preliminary calibration results under selected polarized illumination conditions.

Using a polarized illumination source is a promising RET technique for improvement of wafer printability for features of 65 nm and below. Polarization effects could be considered in several different stages of lithography modeling and simulation. For example, light propagation in thin films, wave superstition and interference in the thin film stack, and mask-induced polarization all deserve special attention and delicate treatment because TE and TM waves have different behaviors through these stages. In this paper we consider effects of polarized illumination in photo resist, using the Kirchhoff approximation for masks. We discuss some theoretical aspects of our vector modeling methods and show an example of simulation for polarized illumination effects.

Lithographic methods of imaging in resist can be extended with the addition of immersion fluid. The higher index of refraction fluid can be used to print smaller features by increasing the numerical aperture beyond the limits of dry lithography. Alternately, an immersion optical system can achieve a larger depth of focus at the same numerical aperture as the equivalent dry lithography system. When numerical apertures are significantly greater than 1.0, polarization effects start to impact resolution seriously. Special illumination conditions will be used to extend resolution limits. Additional factors that affect imaging in resist need to be included if we are to achieve new resolution limits using high index of refraction materials to increase numerical apertures. In addition to material inhomogeneities, birefringence and optical surface effects, material absorption, coatings and index differences at boundaries will have a larger impact on image resolution as ray angles in the imaging system continue to increase with numerical aperture. Aerial and resist imaging effects that material characteristics have on polarization, uniformity and aberrations in the lens pupil will be studied.

As promising technologies for ArF optical lithography, CLM(Chrome-Less Mask) and alternating phase shift mask(PSM) technologies among RETs(Resolution Enhancement Techniques) for low k₁ have been researched worldwide for a couple of decades. Quartz dry etching has become more critical to manufacture the mask with those technologies in the ArF lithography. Alternating PSM and CLM require the formation of 180-degree phase difference by quartz dry etch. There are many error factors, which can influence CD uniformities on mask and wafers, in dry etch step such as micro-trench, depth uniformity, sidewall angle, and morphology. Furthermore, quartz depth is hard to control because there is no stopping layer for quartz etch. Micro-trench, one of the important factors on quartz etch, can drop light intensity on wafer. Therefore, micro-trench can deteriorate the RET. We investigated characteristics of micro-trench during quartz dry etch process and the influences on resolution, which can be improved by dry etch parameters.

Immersion lithography has been accepted as the major breakthrough for enabling next generation deep subwavelength chip production. As it extends the resolution capability of optical lithography to the next technology node, it brings fresh challenges to resolution enhancement techniques (RET). Accurate lithography modeling becomes even more critical for RET at the sub-65nm nodes. On the other hand, immersion models need to be fully compatible within the context of existing optical proximity correction (OPC) flow. With the hyper NA approach, modeling of immersion lithography requires full vector treatment of the electric fields in the propagating light wave. We developed a comprehensive vector model that considers not only the plane wave decomposition from the mask to the wafer plane, but also the light propagation through a thin film stack on the wafer. With the integration of this model into Synopsys OPC modeling tool ProGen, we have simulated and demonstrated several important enhancements introduced by immersion. In the mean time, the modeling and correction flow for immersion is completely compatible with the current OPC infrastructure.

To extend the application of ArF exposure tool, CPL is one of the most powerful technologies for the resolution enhancement. From previous study, the 2nd level writing by E-Beam writer has been developed to ensure the manufacturability of CPL process. To fulfill the application of CPL Mask, we implemented this technology for 65nm DRAM patterning. First we studied the performance and characteristics of CPL mask with optimized exposure illumination setting for the desired pattern and dimension of 65nm DRAM. Then the mask data for CPL mask manufacture has been generated by modeled pattern decomposition approach together with rule and modeled OPC. This was accomplished by using an engine named MaskWeaver. For the manufacture of CPL mask, we used a binary mask and the Qz was etched for the 180 degrees phase difference. We utilized a 2nd level writing by an E-Beam writer to make the zebra pattern that was generated by the engine for the optimized patterning performance. The exposure tool we utilized for the verification of wafer patterning is an advanced 193nm exposure system. The process performance indexes such as MEEF, process window, CD uniformity were collected to show the capability of CPL process. Also, simulation and empirical data were compared to verify the performance of CPL technology. So by using an optimized CPL technology included mask data generation skill, mask making specifications, and ArF illumination optimization, we can meet the manufacture requirement of 65nm DRAM.

Depth of focus is the major contributor to lithographic process margin. One of the major causes of focus variation is imperfect planarization of fabrication layers. Presently, OPC (Optical Proximity Correction) methods are oblivious to the predictable nature of focus variation arising from wafer topography. As a result, designers suffer from manufacturing yield loss, as well as loss of design quality through unnecessary guardbanding. In this work, we propose a novel flow and method to drive OPC with a topography map of the layout that is generated by CMP simulation. The wafer topography variations result in local defocus, which we explicitly model in our OPC insertion and verification flows. Our experimental validation uses 90nm foundry libraries and industry-strength OPC and scattering bar recipes. We find that the proposed topography-aware OPC can yield up to 90% reduction in edge placement errors at the cost of little increase in mask cost.

EUV lithography has become the leading candidate for pattern replication at the 32-nm technology node, but several important issues remain unresolved. In particular, the availability of defect-free masks is a critical concern. An intensive investigation of defect repair methods for EUVL mask blanks is required because the mitigation of defects has turned out to be much more difficult than anticipated. So, we investigated the effectiveness of several defect repair methods through accurate simulations employing the FDTD method. We calculated aerial images from masks with structural changes due to repair and compared them with those of a perfect mask. All the methods were found to suppress the degradation in light intensity caused by defects. At the same time, each repair method has some limitations and factors that require special attention. Thus, it is important to choose the most suitable repair method for a given defect.

Nano-machining repair technique is relatively new technology for photomask repairing. The advantages of this technique are low substrate damage, precise edge placement accuracy and improved Z height accuracy comparison with Laser zapper or FIB GAE repair techniques. In this work, we have evaluated nano-machining technique capability for EUV mask repair. To get good wafer print results, additional side etch(X bias) and depth etch (Z bias) were needed. Defect repaired region was evaluated using CD-SEM, AFM and wafer print test. Good repair profile and good wafer print results were successfully obtained.

Although EUVL is widely considered to be used from the node of hp32nm, there are serious problems. One of them is the defect problem at the mask blank. The defect concentration increases rapidly as its size becomes smaller, but the current defect level of around 0.1/cm²(>100nm) is orders of greater than the required level of 0.005/cm²(>32nm). Also the present defect detection limit of around 50nm is much greater than the required defect size of 23nm for hp32nm and 16nm for hp22nm. Therefore 8X mask, having double-larger patterns, is helpful because of its double-larger size for the required minimum defect. Moreover the double-larger patterns have much fewer killer particles, which is also helpful for the no-pellicle mask. However changing the mask magnification to 8X has been reported to decrease the exposure-tool throughput to around 40% of that of 4X. Since this decreased throughput was estimated for KrF/ArF, and not for EUVL, throughputs of an 8X EUVL scanner are calculated. The calculated results have cleared that an 8X scanner can give around 64% of the 4X throughput, and that a 9” 8X scanner and a double-long 8X scanner can give 89-98% of the 4X throughput at the resist sensitivity of 5mJ/cm². This is due to a double-higher scan speed obtained by 8X. Another advantage by changing to 8X is the smaller line edge shift by the shadowing effect to 1/2-1/3 because of the higher magnification and the possibility of decreasing the illumination incident angle. Similarly the mask surface flatness requirement can be loosened by 2-3 times.

Stencil masks for electron projection lithography (EPL) require peculiar patterns as perforations in a thin membrane. The stencil pattern accuracy of a conventional mask with 1-mm subfields and a new geometry mask with 4-mm subfields was evaluated and compared. No significant influence of the mask geometry on most of critical dimension (CD) specifications was observed. The stencil patterns in both geometry masks had vertical sidewalls ~ 90° with angle range less than 0.3° and CD uniformity of ~12 nm (3σ) across the mask. CD linearity is also similar for both geometry masks. On the other hand, enlarging the membrane windows considerably increased CD deterioration and image placement (IP) distortion within individual membranes. A practical 4 mm-window mask requires solution to this issue. The stencil pattern accuracy is, however, acceptable level for not only the 1 mm-window mask but also the 4 mm-window mask at current EPL development status. According to the evaluation of the stencil pattern accuracy, pattern specification of the EPL mask for 45-nm node would be achieved with further process optimization despite of its peculiarity in pattern structure.

Electron projection lithography (EPL) has high-resolution capability of meeting the 45-nm technology node, especially for the “hole” process. A first-generation EPL has been developed and improved at Nikon and Selete. Defect free mask is indispensable for successful introduction of this technology into the production stage. However, an EPL mask is considerably different from today's optical photomask, especially due to its 3-D structure. Hence the conventional methods of quality assurance used for optical photomask are not applicable for EPL mask. Selete is now developing a series of defect inspection and repair systems for an EPL stencil mask infrastructure. In our previous work we verified a number of defect inspection and repair systems through a sequential process. We confirmed good sensitivity for ”hole” inspection, and accuracy of consistent template repair method through the various hole-defect types. Based on our previous work, here in this work we focus on Gas Assisted Etching (GAE) because the majority of the defects are black type defects in smaller features, especially at 45-nm node. The motivation here is to investigate on GAE repair for real usage at 45-nm node. In this paper we verified the capability of repair technology for isolated holes including smaller features. Moreover, we confirmed that the problems encountered in dense hole forming can be resolved.

We have developed PCARs for LEEPL mask making that has high resolution, good CD uniformity and process stability. The proper choice of resists and the process optimization enabled to form 60nm hole patterns and achieved the local CDU<4.0nm at 80nm hole patterns using the current 50 keV VSB exposure system. The results of the examination about PEB temperature and CD revealed that the CD of small hole patterns was controlled by the quencher diffusion rather than the generated acid diffusion. Defocus issue was also investigated and the sensitivity control of a resist was effectively method against CD error. These results in this report clearly indicate the strategy of the resist development for resolve less than 100nm feature size using EB exposure system.

Large window-size membranes for stencil masks are required to increase the throughput of electron projection lithography (EPL) and low-energy electron projection lithography (LEEPL). In this paper, image placement (IP) accuracy and methodology for correcting stress-induced distortions on 4 X EPL masks are addressed. Although the average of local IP errors (| mean | + 3σ) for reference features across an entire 1mm-window EPL mask is 13.4 nm, the average of errors across an entire 4mm-window EPL mask increases to 20.4 nm, which could be reduced to the required budget with further study on EB writing accuracy or IP corrections. In addition we evaluate local IP errors on 4mm-window mask due to pattern gradients by measuring the placement errors at the edge of dense hole arrays. Applying the correction for stress-induced distortions to EB data, we can reduce the placement errors for dense features to 4.6 nm, which is less than the 10 nm budget allocated for 4mm-window EPL mask at the half-pitch features of 45 nm node. For the global IP, only the measurement repeatability of 7.8 nm contributes to the global IP budget measuring all the global position over an entire 4mm-window EPL mask. And we can meet the required global IP budget. Finally, IP accuracy for a single membrane is also presented, showing the IP error is 24.5 nm (| mean | + 3σ), which compares with that of COSMOS type LEEPL mask. Methodology of measuring the position data on a single membrane, however, remains to be developed.

We have fabricated seven masks with different patterns on a 27 mm x 34 mm single-membrane for Low Energy Electron-beam Proximity Lithography (LEEPL) by the wafer-flow process. We have examined the membrane flatness and image placement (IP) accuracy, which are essential qualities to be assured. We summarize the results as follows: Masks with membranes of 13 MP and 20MPa stress satisfy the membrane flatness requirement of less than 2 μm while a mask with a 6 MPa membrane does not. Maps of the distortion induced by the wafer-flow process are obtained for the masks with 13 MPa and 20 MPa membranes and their performance is explained in terms of the contraction of the mask substrate. The out-of-plane distortion for a 3 mm x 3 mm block of dense hole patterns with an opening ratio, ranging from 10% to 40%, has been evaluated. The distortion induced by the block has been evaluated and the effect of the local magnification correction on the IP error is examined. Maps of the distortion induced by the wafer-flow process and 4 x 4 blocks of 10% and 20% opening are obtained for a mask with 13 MPa membrane and the distortion induced by the blocks is estimated in 3σ. The uncorrectable IP error for the mask with the blocks of 10% opening is estimated to be 10 nm (in 3σ), which satisfies the specification for LEEPL masks.

The process of inspection and repair for LEEPL masks is increasingly required. A stencil mask inspection system EBScanner (Tokyo Seimitsu), using transmission electron beam, was investigated defect inspection capability on LEEPL masks. We fabricated a defect standard mask (DSM) in which programmed defects were formed, to estimate the performance of the inspection system. We performed experiments on printability of the DSM and Area MEEF (Mask Error Enhancement Factor) of LEEPL. As a result, correlation between area of pattern on mask and that on wafer is excellent, and Area MEEF is 1.19. The killer defect was defined based on the printing result on wafer. The defect size is measured by pattern shape analysis tool MaskEXPRESS (Toppan Printing). We checked the detection rate of killer defects and the number of false or real defects other than programmed defects by optimizing sensitivity of EBScanner. In case that a lot of false defect and very small defect (not crucial) are detected due to the non-uniformity of the pattern size, it takes too much time for defect review and practical classification. For reducing this work, we studied some solutions. And thus, we will discuss the analysis of EBScanner’s inspection image, including the defect classification.

We are developing a NGL data conversion system for EPL, for LEEPL, and for EBDW, which is based on our established photomask data conversion system, PATACON PC-cluster. For EPL data conversion, it has SF division, Complementary division, Stitching, Proximity effect correction, Alignment mark insertion, EB stepper control data creation, and Mask inspection data creation. For LEEPL data conversion, it has Pattern checking, Complementary division, Stitching, Stress distortion correction, Alignment mark insertion, and Mask inspection data creation. For EB direct-writing data conversion, it has Proximity effect correction and Extraction of aperture pattern for cell projection exposure.

For leading mask technologies the mask inspection for finding critical defects is always a difficult task. With the introduction of chrome-less, high-transmission and alternating mask types, new absorber material and the possibility of quartz defects the defect inspection and -classification becomes even more challenging. To decide whether a defect is critical or a repair is successful, the Zeiss AIMS tool is used to classify defects. For conventional imaging the optical settings are usually chosen such that resolution is maximized, for example a dipole illumination is used for imaging a dense line-space array at an optimum contrast. In this paper we will do the opposite and reduce the optical resolution, such that we can filter out the array pattern and study the resulting defect image. This technique allows using a simple threshold detector to find and classify defects.

The paper presents a description of a new modular automatic reticle defect inspection platform and also a description of one of the main elements of this platform - a defect detection sub-system. This platform is currently under active development at Planar Concern. This paper presents the results of the use of the object-oriented approach which was used in the development of the defect detection algorithms for the die-to-database reticle inspection system. Furthermore, the paper presents briefly the architecture and technology of the new modular automatic reticle inspection platform.

Application of long wavelength in lithography process has a great benefit for cost of ownerships (COO) of semiconductor manufacturers, however there’s a trade off of reducing process margins due to the low k1 condition, and all the efforts in order to obtain large process windows on wafer connect directly to chip production management. In this paper, the authors used 248 nm wavelength lithography with alternating phase shift mask (alt-PSM) to develop 90 nm line and space patterns in 90 nm half pitch on wafer, and thoroughly investigated printability of defects and defect-repairs on alt-PSM. Sensitivity analysis of photomask defect inspection tools was implemented and it showed that existing inspection tools satisfied requirements for detection of chrome (Cr) and quartz (Qz) defects, which had impacts on wafer. Printability of Cr and Qz defect repairs was evaluated focusing on through-defocus behavior, and conditions of defect repair were optimized to reduce variation of critical dimension (CD) on wafer. The repair conditions were also optimized by estimation of overlaps of process windows of defect-repaired area on that of non-defective references. Process windows were analyzed based on both wafer and aerial image measurements. In the last section of this paper, we discussed managing process windows of defect repairs by controls of biases and Qz heights as parameters on defect-repaired areas and suggested that total topography control around defective area was required in addition to the prospected parameters in order to maximize process margins.

The Geometry Verification System NGR2100 enables verification of the entire die, on a resist or an after-etch wafer, by comparing images of a die with corresponding target CAD data. The system detects systematic defects by variable criteria setting for allowable deformation quantities and obtains a CD distribution diagram. The result of systematic defects can then be used to make root cause analysis. The CD distribution diagram can achieve stepper aberration analysis, process windows extraction, macro-loading effect analysis, FEM measurement, and trend analysis more efficiently. Consequently, the Geometry Verification System NGR2100 will contribute to quicker TAT for DFM in Design, Lithography and Mask production.

The 65nm photomasks have to meet tight specifications and improve the production yield due to high production cost. The 65nm optical lithography was thought to have two candidates, 157nm and 193nm. However, at the advent of immersion lithography, it is certain that 193nm lithography will be adopted. Therefore, we decided to develop the FIB machine, SIR7000FIB, proior to the EB machine. We optimized repair conditions of FIB system, SIR7000FIB, and evaluated this system. First, we demonstrated minute defect repair using about 15nm defect mask. Then, we confirmed that the repeatability of repair accuracy was below 7nm on a MoSi HT mask patterned 360nm and 260nm L&S patterns with opaque and clear defects by AFM. Consequently, we have achieved the target specifications of this system.

Current generation photomasks use optical enhancements such as phase shifting and aggressive OPC in an effort to maintain image contrast as CDs shrink. The result is non-intuitive complex shapes with jogs and multiple levels with different materials. The mask repair engineer is challenged to work with defects that occur in ever tightening spaces on these complex masks. Prior established nanomachining technology allows nanometer level control of material removal. To date, the challenge in developing repair strategies that will meet transmission specifications as well as maintaining aerial image contrast through focus has been mainly an empirical exercise where the mask repair is attempted and aerial image measurement among other tests are used to verify the result. This approach can be streamlined by the use of lithography simulation which rigorously models the effects of mask defects on the aerial image at the wafer. Once the topography of the defect is measured by the nanomachining mask repair tool, lithography simulation can be proactively used to develop a repair strategy for the nanomachining process. Following this repair, the simulation software can then provide immediate feedback to confirm the post repair 3-D topology from AFM surface measurements for either approval or immediate rework. This integration is initially validated using a significant set of repairs with subsequent aerial image measurements compared to some of the more common evaluative analyses.

Laser lithography tools have been a staple in the photomask industry for second level printing for several years. This paper explores the overlay capabilities of the Alta4300D Deep UV (DUV) lithography system. The tool is manufactured by ETEC Systems, a part of the Mask Business Group of Applied Materials. The tool demonstrates good overlay performance, and an improved data path ensures the ability to handle large file sizes without an adverse impact on writing time. In addition to actual performance data on product masks, a simple analysis of the maximum total edge placement error of a hypothetical two level alt-PSM process is presented. The results show the tool is capable for many advanced phase shift overlay applications.

This paper is a review of different gray scaling techniques used in mask making. It shows that high address resolution and high throughput can be combined with the lithographic performance necessary for the most advanced applications. In the semiconductor industry, the demand for better performance in terms of clock-frequency and circuit density continues to push Moore’s law. One effect is shrinking design grids to cope with the tighter requirements on resolution, CD control, and aggressive OPC. For mask making this means that the address resolution of the mask writing equipment must be improved for every tool generation. The address resolution in the mask writer can be increased in two ways; either by decreasing the physical grid, or by introducing a virtual grid, here referred to as gray scaling. A decreased physical grid puts a high penalty on throughput, a performance parameter of utmost importance for reasonable mask costs and cycle times. With gray scaling, a fine address grid is created, while keeping a large physical grid for high throughput. In earlier publications, a single pass gray scaling technique has been shown to reduce image quality in terms of image log-slope. This paper shows that the effects are smaller when using other approaches to gray scaling and that it is kept to a minimum in the SLM-based DUV Sigma7300 mask writer, which uses partial coherent imaging and multiple writing passes. Analysis shows that for this combination of SLM and partially coherent light, the reduction in image log-slope due to gray scaling is less than 8%. In addition, the systematic averaging of four displaced writing passes makes the loss isotropic and independent of grid position. A detailed error analysis shows that a small address grid is more important for composite CD uniformity than the loss in image log-slope.

For the manufacturing of 65nm technology devices, many exposure techniques that have been used in previous technology nodes cannot offer enough process window anymore. Alternating Aperture Phase Shift Mask (Alt-PSM) is one of the few remaining technologies that still offer enough resolution to enable 65nm production. While setting up a 65nm Alt-PSM based resolution enhancement technique (RET) flow many of the mask manufacturability challenges need to be considered and addressed. At the same time OPC complexity is one of the main factors for increased data volume and high mask costs. In this work, logic and embedded memory cells are designed, and based on the specific geometries a manufacturable RET flow is developed. Data complexity reduction and lower mask cost are the primary motives in setting up this RET flow.

Lithography simulation is an integral part of semiconductor manufacturing. It is not only required in lithography process development, but also in RET design, RET verification, and process latitude analysis, from library cells to full-chip tape out. Two RET design checking flows are examined and compared. In the first flow, an image contour is simulated from post-OPC, GDSII data at best focus and exposure conditions. RET design defects are identified by comparing the calculated contours with the pre-OPC design data. To check lithography manufacturability across the typical IC process window, the second RET verification flow simulates image contours at multiple focus and exposure conditions. These RET design checking flows are implemented on new platform that combines a hardware accelerated computational engine with a new analysis method to numerically evaluate the lithographic printing and mask manufacturing challenges for a given design layout. The algorithm approach in this new system is based on image processing which is fundamentally different from conventional edge-based analysis. Specific examples of a mask aware RET verification flow leveraging this new platform and method will be provided with speed and accuracy benchmarks. Through the high speed computation of lithographic images from full chip data, many opportunities for novel and cost effective post layout lithography verification options become available. By combining the new platform with analysis steps relevant in leading edge photomask manufacturing, it may become possible to reduce the risks inherent in advanced technology tape outs while improving layout to mask fabrication cycle time and cost.

The lithography verification of critical dimension variation, pinching, and bridging becomes indispensable in synthesizing mask data for the photolithography process. In handling IC layout data, the software usually use the hierarchical information of the design to reduce execution time and to overcome peak memory usage. However, the layout data become flattened by resolution enhancement techniques, such as optical proximity correction, assist features insertion, and dummy pattern insertion. Consequently, the lithography verification software should take burden of processing the flattened data. This paper describes the hierarchy restructuring and artificial neural networks methods in developing a rapid lithography verification system. The hierarchy restructuring method is applied on layout patterns so that the lithography verification on the flattened layout data can attain the speed of hierarchical processing. Artificial neural networks are employed to replace lithography simulation. We define input parameters, which is major factors in determining patterns width, for the artificial neural network system. We also introduce a learning technique in the neural networks to achieve accuracy comparable to an existing lithography verification system. Failure detection with artificial neural networks outperforms the methods that use the convolution-based simulation. The proposed system shows 10 times better performance than a widely accepted system while it achieves the same predictability on lithography failures.

Today's design-manufacturing interface lacks essential mechanisms to link disparate disciplines and tool sets. In this paper, we describe three specific mechanisms for improving OPC quality via interactions within the design-to-manufacturing flow. Our studies of these improvements have yielded promising results.

The 65nm and 45nm device generations will be used to manufacture large designs using complex patterning processes in combination with exotic model-based or rule-based RETs’ scenarios. The lithography for these generations will operate in the low k1 regime value resulting in small process window and tight overlay requirements. Therefore, the potential for having yield limiting errors due to RET-process-design interactions is significantly higher than with the 130nm generation. Additionally, the high cost of reticles and the large number of process layers make it quite important to catch these costly errors. Optical Rule Checking (ORC) is an effective way to predict failure on wafer shapes. Used in addition to Optical Proximity Correction, it can help to reduce failures affecting yield in manufacturing. Thus, due to the inter-layer complexity of processes and RET, the necessity to check accurately particular areas which could generate costly errors is growing: Here are some examples: 1) Low metal-contact or metal-via overlaps, 2) Small poly extension past active area, 3) Low overlap between poly and contact layers, and 4) Dual exposure techniques for single layer patterning. The main difficulty in current implementation of multiple layer RET verification is the trade off between accuracy vs. runtime vs. fault coverage. In this paper we will demonstrate how based on this trade off we can enhance our final printed results by accurately targeting the most likely failure mechanism on multiple layer processes check in a production environment (90nm node product layout). Finally we will show how ORC in a multiple layer check is going to help detect faults and overlay sensitive areas so as to secure process weakness areas. We will compare several softwares where such a methodology is applied and attend to propose a post OPC verification strategy to obtain a more robust manufacturing process.

We have developed a unified mask data format named “OASIS.VSB” for Variable-Shaped-Beam (VSB) EB writers. OASIS.VSB is the mask data format based on OASIS released as a successive format to GDSII by SEMI. We have defined restrictions on OASIS for VSB EB writers to input OASIS.VSB data directly to VSB EB writers just like the native EB data. We confirmed there was no large problem in OASIS.VSB as the unified mask data format through the evaluation results. The latest version of OASIS.VSB specification has been disclosed to the public in 2005.

EB direct writing technology for small-volume fabrication LSIs is cost-effective compared to optical lithography. The new standard cell layout technique called “Character-Build cell” is developed in order to increase the utilization ratio of character projection (CP) mask. The various kinds of standard cells can be composed by the combination of "character” cells. The 86% of 223 standard cells can be composed by 17 “character” cell using this technique. It is estimated that the great portion of random logic area can be exposed by about 50 CP mask. Therefore the throughput of EB direct write using this layout technique will be greatly higher than that of the conventional layout.

With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Today’s advanced lithography for DRAM/Flash is operating at k₁ close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k₁=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k₁ lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k₁ factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OAI). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k₁ barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution

In this paper, a method for improving the process window is described by simultaneous source mask optimization (SMO). The method optimizes the source and mask of a critical pattern by optimizing the mask in the frequency domain. The minimum image log slope (ILS) is maximized at fragmentation points in the critical pattern while simultaneously maintaining the printing fidelity. The mask optimized in the frequency domain is then converted into a chromeless phase lithography (CPL) mask. The process window with the optimized source and optimized CPL mask doubles the aerial image contrast in comparison to an attenuating PSM with source optimization only. After optimizing the mask and source for a critical pattern, the remaining parts of the full-chip design are optimized with interference mapping. Another technique for optimizing the source for a full chip is presented in which the source is optimized by using the pitch frequency of the design. From the pitch frequency, the source is optimized by solving an integral equation for the first eigenfunction in which the first eigenfunction is calculated from the sum of coherent system (SOCS) representation of the transfer cross coefficient (TCC).

In the process of discussion of possible mask-types for the 5x nm node (half-pitch) and below, the alternating phase-shifting mask (AltPSM) is a potential candidate to be screened. The current scenario suggests using 193 nm immersion lithography with NA values of up to 1.2 and above. New optical effects from oblique incident angles, mask-induced polarization of the transmitted light and birefringence from the substrate need to be taken into account when the optical performance of a mask is evaluated. This paper addresses mask induced polarization effects from dense lines-and-space structures on a real mask. Measurements of the polarization dependent diffraction efficiencies have been performed on AltPSM masks. Experimental results show good agreement with simulations. A comparison with Binary Masks is made.

Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows. For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.

Alternating aperture phase shift masks (AAPSM) continue to offer high contrast imaging for 65nm half-pitch using conventional 193nm illumination. The transition to high NA lithography systems including immersion lithography, and the ever-decreasing feature sizes have made the topography of the photomask a significant issue in the final resist image. Therefore, the influence of the alternating phase shift depth, the trench profile, and the critical dimension control through variable feature width must be considered and understood for optimized wafer imaging. This paper will examine the impact on imaging based on three photomasks, each employing different quartz etch chemistries. The three methods used to define the well structures include two all dry and a partial wet etch approach. As the photomask features continue to decrease, slight changes in the quartz etched trench profile and depth can severely affect the wafer prints, as the effective 180 degree phase shift for imaging is not achieved. In this work we correlate the imaging performance through pitch to a systematic evaluation of the photomask topography using complementary photomask metrology techniques. The actual depth and profile of the structures is obtained on a FEI Stylus nano-profilometer (SNP-XT) and from destructive cross sections. The CD linearity is measured on a top-down reticle CD SEM (KLA 8100XR). Based on photomask metrology data, rigorous electro-magnetic field (EMF) simulations of the various topographic profiles are performed. As a first printing performance estimate the photomasks are evaluated on a Zeiss AIMSfab193. Comparisons between the different evaluations will be made against wafer prints, obtained on an ASML PAS5500/1100 ArF scanner working with a 0.75NA projection lens. This study will lead to an understanding of the impact of possible limitations of the current quartz etching processes on the imaging performance of alternating phase-shift masks for 65nm half-pitch.

The phase shift mask (PSM) is one of the most effective approaches to improve ArF lithography performance. Recently, the quartz dry etching technology plays an important role to fabricate the PSM, such as space bias type Alternating (Alt.) PSM and chrome-less phase lithography (CPL) mask. The quartz etching profiles seems to be affected the lithography performance. In this paper, preliminary, we evaluate the nominal influences of quartz profile by rigorous electromagnetic field simulation. Then influence of the quartz profile is investigated by measuring the real masks. In this experiment, we intentionally fabricate Alt. PSM and CPL masks with the tapered side-wall and deeper micro-trench. Lithography performances of the real masks are measured by the aerial image measurement system (AIMS fab193). We compare the result of AIMS with simulation. We investigate the AIMS measurement well corresponds to the simulation. Side-wall angle and corner rounding strongly affect the lithography performance. However, micro-trench doesn’t affect a lot.

Mask distortion due to thermal loading during exposure contributes significantly to the overlay error budget and poses significant challenges for extending optical lithography to the sub-100nm regime. In this paper, we model the thermal mask distortion during the scanning exposure in 193nm lithography, and investigate its dependency on the distribution of the local pattern density on the mask. Several numerical simulation methods are investigated for accurately predicting the transient and steady-state thermal and distortion response of the mask during exposure. In particular, we find that simulating an “effective” continuous illumination power has the same thermal and distortion impact as the actual pulsed laser power delivery to the mask during IC production. This approach dramatically reduces computational cost. Our parametric analysis demonstrates that the magnitude of the thermal and distortion responses are closely related to the global pattern density and exposure dose. Furthermore, thermal mask distortion is found to be significantly dependent on the distribution of the local pattern density on the mask. Given that often the mask pattern layout can be manipulated at some level of abstraction, we conducted Monte Carlo simulation which verifies the existence of optimal pattern density distributions minimizing the mask thermal distortion, and highlights the opportunity to optimize mask pattern layout with respect to mask thermal distortion.

As the feature sizes on the wafer continue to shrink, the dimensions on the mask also scale down, which makes the mask topography more important. The impact of the absorber thickness of a Binary Intensity Mask (BIM) and an Alternating Aperture Phase-Shifting Mask (AAPSM) on the imaging performance of ArF lithography is investigated by using a rigorous electro-magnetic field simulator, an NA0.85 immersion scanner, and an NA0.93 conventional scanner. The simulation at NA0.85 dipole illumination for BIM shows that the mask-error enhancement factor (MEEF) for 130-nm-pitch lines and spaces increases to 3.1 from 2.5 by reducing the absorber thickness from 104 nm to 56 nm. Lower aerial-image contrast at the thinner absorber, which causes the larger MEEF, is attributed to the lower interference efficiency due to increase of transverse-magnetic component and decrease of the intensity balance between 0th- and 1st-order diffracted light. In AAPSM, the image-placement errors caused by intensity imbalance between 0 and π phase-shifting spaces are influenced by the absorber thickness. It was demonstrated by the increase of dose sensitivity from 5.2 to 6.5 nm/(mJ/cm²) and line edge roughness increase from 7.1 to 8.2 nm of 150-nm-pitch lines and spaces made by using immersion process that thinning the BIM absorber from 103 to 59 nm degraded the aerial image of NA0.85 annular illumination. The conventional dry exposures by using NA0.93 dipole lithography supported the image degradation due to thinning the BIM absorber by showing that the line edge roughness of 125-nm-pitch lines and spaces increased by 1.2 nm using un-polarized illumination. The aerial-image contrast of the thicker absorber keeps better up to NA1.40, which suggests that we need to balance the merits and demerits of using the thinner absorber by giving attention to the mask topography effects.

There are many challenges ahead to use ArF for printing 45nm node device. High numerical aperture (NA) exposure tool and double exposure technique (DET) are the promising methods to extend ArF lithography manufacturing to 45nm node at k₁ factor below 0.35. Scattering bars (SB) have already become indispensable as chipmakers move to production in low k₁ factor. The optimum SB width is approximately (0.20 to 0.25)*(λ/NA). When SB width becomes less than the exposure wavelength, the Kirchhoff scalar theory is no longer accurate. When the optical weight of the SB increases, they become more easily printable. In order to ensure more robust lithography, both foundry and IDM prefer to choose higher NA exposure tool to maintain higher k₁ (>0.35). The chipmaker is currently using 0.85 NA, ArF, scanners for 65nm development and early device qualification. With immersion, the NA can be greater than 1.0. Under such a hyper NA (>1) condition, SB scalability and optical weight control are becoming even more challenging. Double exposure methods using either ternary 6% attenuated PSM (AttPSM) for DDL, or applying CPL mask with DDL, are good imaging solutions that can go beyond 45nm node. Today DDL with binary chrome mask is capable of printing 65 nm device patterns. Transmission tuning combined with OAI can achieve best-known imaging contrast for low k₁ lithography. In this work, we investigate the use of DDL with 6% ternary AttPSM to target 45nm node features. SB scalability issue can be addressed in both schemes since the SB can be exposed away using the combined dose from double exposures. Dipole with linearly polarized light can significantly improve the image contrast. The key to take advantage of polarization is to convert the layout into the corresponding x y patterns. We have developed model-based layout conversion method to generate both 6% AttPSM that can consider polarization effect. In this study, we share our initial findings through simulation and to report the initial binary mask printing result of DDL with linearly polarization.

Parameter optimization is a key issue to develop low-k1 lithography processes, in which the number of control and error factors has been increasing. This holds especially true for alternating phase-shifting mask (alt-PSM) techniques; i.e., for this technique, not only exposure conditions but also mask structures should be optimized under various error factors (or noise factors), such as defocus, dose fluctuations, lens aberrations, mask making errors and so on. This paper describes a novel method of performing such optimization, which is developed based on a method of design of experiments (DOEs). Stabilities of target performance for various combinations of parameters are simulated by varying noise factor levels which are assigned to an orthogonal array. Optimum values of parameters are determined so as to maximize the stabilities of target performance. This method is applied to a 45-nm node alt-PSM (alternating phase-shifting mask) technique. Optical conditions, such as NA (numerical aperture) and σ-value, and mask structures, such as trench depth and undercut size, are optimized under various noise factors by applying our method for optimization. As a result, high stability of critical dimension (CD) is obtained together with sufficient suppression of image placement errors. The optimized result is further verified by statistic calculations. Finally, we conclude that our method is a very powerful tool to simultaneously optimize lithographic conditions for low-k1 lithography processes.

For the coming technology nodes, lithography options that use 1X masks are becoming practical candidates. Especially the nano-imprint lithography (NIL) is expected as one of the candidates for 32nm node and below, because of its potential low lithography cost. Naturally, 1X masks require features finer than those on today's 4X masks, and for mask making this means a big and hard technology jump. From the mask making point of view, even the 1X mask is still a candidate, it would be a technology driver in terms of patterning process development for the coming nodes. In this paper, we focused on the NIL mold (or mask) making evaluation. Among the important factors dominating the resolution of the mask making process, we studied particularly on the resist and the dry etch. We found that with tools currently used in the commercial mask shops today, and by modification of resists, we could achieve 30nm isolated spaces and 50nm dense lines and holes. We also discuss about our initial results of mask EB writing method evaluation. We found that, to improve the resolution further, the implementation of high resolution EB tools into the mask manufacturing line is inevitable to made molds for 32nm or 22nm technology nodes.

Electron projection lithography (EPL) is one of the most promising candidates for the next generation lithography toward the hp 45 nm-node and beyond. EPL employs a stencil mask made from 200 mm Si wafer without a support frame, therefore chucking of an EPL tool and a metrology tool causes deformation in an EPL reticle. However, linear components of sub-field (SF) position error can be corrected by reticle alignment features of an EPL tool, whereas the non-linear components of SF position error can be corrected where each SF is measured beforehand and the corresponding reticle distortion correction (RDC) data is fed into the EPL exposure tool. In order to realize higher throughput, expanding SF to 4 mm-sq on reticle scale from the present 1 mm-sq is examined at the future EPL tool. For our studies we have investigated global image placement (IP), local IP, and pattern distortion of two kinds of EPL reticle. Currently we find the effect of mask IP on wafer scale is less than 9 nm, and we believe that in the near future the EPL mask IP target for the hp 45 nm-node could be realized for both of SF size.

EUV lithography is the prime candidate for the next generation lithography technology after 193 nm immersion lithography. The commercial onset for this technology is expected for the 45 nm half-pitch technology or below. Several European and national projects and quite a large number of companies and research institutions in Europe work on various aspects of the technological challenges to make EUV a commercially viable technology in the not so far future. Here the development of EUV sources, the development of an EUV exposure tools, metrology tools dedicated for characterization of mask, the production of EUV mask blanks and the mask structuring itself are the key areas in which major activities can be found. In this talk we will primarily focus on those activities, which are related to establish an EUV mask supply chain with all its ingredients from substrate production, polishing, deposition of EUV layers, blank characterization, mask patterning process and the consecutive metrology and defect inspection as well as shipping and handling from blank supply to usage in the wafer fab. The EUV mask related projects on the national level are primarily supported by the French Ministry of Economics and Finance (MinEFi) and the German Ministry of Education and Research (BMBF).

The most critical challenges in EUVL include the manufacturing of defect-free EUVL substrates, blanks, and masks. Developing capability in the areas of sub-100nm defect metrology, characterization, and analysis provides the key path for defect root-cause analysis in the defects elimination roadmap. We have demonstrated successful application of integrated surface analytical techniques, including AES (Auger Electron Spectroscopy), EDX (Electron Dispersion X-ray Spectrometry), SEM, and AFM to review, analyze, and characterize defects on EUVL multilayer blanks and substrates, following the optical defect inspection process by the Lasertec M1350, which does defect scanning, mapping, image review, and fiducial marking. Small defects, 40nm wide and 10nm tall, have been analyzed in morphology as well as in composition. In order to overcome the electron beam charging problem on the substrate materials during analysis, we applied marking and metal film coating on the LTEM substrates and acquired composition data. Defect metrology data serve as finger prints of the EUV blank fabrication process. We have discovered that the majority of the multilayer defects today are embedded bumps, pinholes, and organic materials that originated from the LTEM substrates. Composition data of the defects also suggested that process chemicals and human handling of process are the culprit of these defects. Therefore defect reduction efforts should be focused on the processes or procedures which take place from the glass finishing process to the very first layers of silicon molybdenum deposition.

Extreme ultraviolet lithography (EUVL) is the leading next generation lithography (NGL) technology to succeed optical lithography at the 32 nm nodes and beyond. The technology uses a multilayer-based reflective optical system and the development of suitable, defect-free mask blanks is one of the two greatest challenges facing the commercialization of EUVL. In this paper we describe recent progress towards the development of a commercial tool and process for the production of EUVL mask blanks. Using the resources at the recently formed Mask Blank Development Center at SEMATECH-North we have been able to decrease the mean multilayer-coating-added defect density on 6” square quartz substrates by almost an order of magnitude, from ~0.5 defects/cm² to ~0.055 defects/cm² for particles ≥ 80 nm in size (PSL equivalent). We have also obtained a “champion” mask blank with an added defect density of only ~0.005 defects/cm². This advance was due primarily to a compositional analysis of the particles using FIB/EDX followed by tool and procedural upgrades based on best engineering practices and judgment. Another important specification for masks blanks is the coating uniformity and we have simultaneously achieved a centroid wavelength uniformity of 0.4% and a coating-added defect density of 0.06 def/cm².

One of the biggest challenges in extreme ultraviolet lithography (EUVL) reflective mask blank fabrication is to make a reflective multilayer (ML) blank “defect-free.” SEMI-P38 standard for EUVL mask absorbing film stacks and ML requires ML defect density in the mask quality area to be less than 0.003 defect/cm² at 30nm size for the 32 nm technology node. Due to the technical challenge in making such a defect-free ML EUVL mask blank, the EUVL ML blank yield is expected to be low. In order to reduce EUVL technology cost, it is desirable to reuse a qualified defect-free ML blank a few times. In this paper we will present a new EUVL ML blank design that allows one to reuse the ML blank after a patterned mask is no longer needed. A standard ML design will only allow one time use. The blank, in general, will not be reusable or reclaimable due to the top capping layer (possible a few layers underneath it) damage during the mask patterning, cleaning, and usage. The new ML blank design alters the standard capping layer structures such that the ML blanks can be reused up to a few times after the blank goes through each complete mask patterning and usage cycle. No additional ML re-deposition is needed for reusing the ML blanks. This new ML structure is particularly attractive since a blank, once it is qualified as a defect-free blank, can be reused a few times as a defect-free ML blank.

Due to the non-telecentricity of the EUV illumination, the EUV mask flatness budget dictates the use of an electrostatic chuck in the exposure tool. Since the mask backside flattening provided by the electrostatic chuck in the exposure tool is very different from the 3-point mounts currently employed to hold reticles in pattern generation and registration measurement tools, this raises the question of which mounting techniques to apply in future patterning and registration tools. In case drastic changes need to be made to the tool configurations, it is important to know, and as early as possible, whether backside chucking of reticles, via an electrostatic or vacuum chuck, is absolutely required or if a 3-point mounting scheme can suffice in these tools. Using finite element simulations, the effects on EUV mask image placement of stressed layers and their patterning, as well as substrate and chuck non-flatness were predicted for these different conditions. The results can be used to calculate image placement error budgets and determine what substrate and blank specifications are needed for the implementation of EUV at the 32-nm node.

As design rule continues to shrink towards ITRS roadmap requirements, reticle defect capture criteria are becoming ever more challenging. Pattern fidelity and reticle defects that were once perceived as insignificant or nuisance are now becoming a significant considerable yield impacting factor. More defects are also detectable and presented with increase in implementation of new generation reticle inspection systems. Therefore, how to review and characterize defects accurately and efficiently is becoming more significant. In particular, defect classification time often corresponds directly to the cost and the cycle time of mask manufacturing or new technology development. In this study we introduce a new mask defect review tool called ReviewSmart, which retrieves and processes defect images reported from KLA-Tencor's high sensitivity TeraScan inspection tool. Compared to the traditional defect review method, ReviewSmart provides a much better method to manage defects efficiently by utilizing the concept of defect grouping disposition. Through the application and qualification results with respectable reticle production cases, the implementation of ReviewSmart has been proven to be effective for reducing defect classification loading and improving defect characterizing efficiency. Moreover, the new review tool is helpful to categorically identify tool or process variations thus allowing users to expedite the learning process for developing production worthy leading node processes.

The detection, classification and disposition of defects is an important function that commands significant resources in mask making. Current processes use manual evaluation of defects, which is slow, subject to errors, and provides sparse data for process improvement. The automated defect analysis software described here reads inspection reports from mask inspection tools, classifies each defect, and measures both its size and printability. It combines and compares data from multiple inspections to provide critical process development data. Data from 144 masks is presented showing that the system missed no critical defects found by operators. These inspections also demonstrated numerous occasions for improved classifications compared to that given by the operators. This capability gives improved disposition, an easy path to using simulator based printability for disposition, and significant improvements in mask yield.

With the ever decreasing feature sizes and increasing cost of current and future photolithographic masks the repair of these masks becomes a substantial factor of the total mask production cost. In a collaborative effort NaWoTec, Carl Zeiss Nano Technology Systems Division (NTS) and Carl Zeiss Semiconductor Metrology Systems Division (SMS) have built an electron beam based mask repair tool capable of processing a wide variety of mask types, such as quartz binary masks, phase shift masks, EUV masks, and e-beam projection stencil masks. In this paper, besides a brief overview of the tool platform, we will present the automated repair of clear and opaque defects on Cr and MoSi quartz masks. Emphasis will be put onto the resolution and the speed of the repair procedure and the high grade of automation and integration achievable in the repair of high-end photomasks. An outlook against the ITRS requirements and the extendibility of the presented solution to further technology nodes will be given in the summary.

The Aerial Image Measurement System, AIMS, for 193nm lithography emulation is established as a standard for the rapid prediction of wafer printability for critical structures including dense patterns and defects or repairs on masks. The main benefit of AIMS is to save expensive image qualification consisting of test wafer exposures followed by wafer CD-SEM resist or wafer analysis. By adjustment of numerical aperture (NA), illumination type and partial coherence (σ) to match any given stepper/ scanner, AIMS predicts the printability of 193nm reticles such as binary with, or without OPC and phase shifting. A new AIMS fab 193 second generation system with a maximum NA of 0.93 is now available. Improvements in field uniformity, stability over time, measurement automation and higher throughput meet the challenging requirements of the 65nm node. A new function, “Global CD Map” can be applied to automatically measure and analyse the global CD uniformity of repeating structures across a reticle. With the options of extended depth-of-focus (EDOF) software and the upcoming linear polarisation capability in the illumination the new AIMS fab 193 second generation system is able to cover both dry and immersion requirements for NA < 1. Rigorous simulations have been performed to study the effects of polarisation for imaging by comparing the aerial image of the AIMS to the resist image of the scanner.

For leading edge technologies, mask critical dimension (CD) errors consume a substantial part of the total wafer CD budget. Moreover, the strong optical proximity effects (OPE) can make the impact of a CD error on the mask significantly worse on wafer. At the same time, the mask making capabilities as far as CD control can barely keep up with the wafer fab requirements. To assess the overall mask quality ever more mask CD measurements are taken in the mask qualification process. These measurement points are increasingly placed in the main die area and are often selected in a more or less random fashion. An improved assessment of the mask CD quality can be achieved by taking advantage of the lithography verification step. The wafer simulation capability in the Silicon versus Layout (SiVL) tool is used to identify the high mask error enhancement factor (MEEF), error prone locations on a critical layer. The mask CD qualification process can be improved by including these poor MEEF and error prone sites. In this work, an automated flow is presented in which mask qualification sites are selected based on simulated wafer image contrast.

Currently, the ALTA 4300 generation DUV Laser tool is capable of printing critical and semi-critical photomasks for the 130nm and 90nm IC technology nodes. With improved optical elements, an improved objective lens, and a higher bandwidth data-path the capability of the tool has been dramatically enhanced - culminating with the introduction of the ALTA 4700. Both the ALTA 4300 system’s diffractive optic element (DOE) and acousto-optic modulator (AOM) have been refined. Additionally, the ALTA 4300 system’s 33x, 0.8NA objective lens has been replaced with a 42x, 0.9NA objective lens. Finally, the tool’s data-path has been enhanced to maintain the ALTA system’s superior write time on critical mask layers. Quantitative results of these enhancements will be detailed through reporting of critical feature resolution limits, CD uniformity control, and pattern placement accuracy on mask. Performance will be shown from masks printed pre- and post- hardware upgrade. Experimental results will be compared with theoretical calculations that show expected and actual improvements. In this paper details of the aerial image created when printing wafers with DUV Laser generated photomasks pre- and post- upgrade will be shown. 193nm print results will be shown with multiple illumination conditions. Details of a print test comparison performed on photomasks from each tool configuration will be documented. The print test comparison will include process window characterization from each mask type.

Phase shift mask (PSM) applications are becoming essential for addressing the lithography requirements of the 65 nm technology node and beyond. Many mask writer properties must be under control to expose the second level of advanced PSM: second level alignment system accuracy, resolution, pattern fidelity, critical dimension (CD) uniformity and registration. Optical mask writers have the advantage of process simplicity for this application, as they do not require a discharge layer. This paper discusses how the mask writer properties affect the error budget for printing the second level. A deep ultraviolet (DUV) mask writer with a spatial light modulator (SLM) is used in the experimental part of the paper. Partially coherent imaging optics at the 248 nm wavelength provide improved resolution over previous systems, and pattern fidelity is optimized by a real-time corner enhancement function. Lithographic performance is compared to the requirements for second level exposure of advanced PSM. The results indicate sufficient capability and stability for 2nd level alternating PSM patterning at the 65 nm and 45 nm nodes.