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PROCEEDINGS VOLUME 5837

VLSI Circuits and Systems II
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Volume Details

Volume Number: 5837
Date Published: 30 June 2005
Softcover: 115 papers (1162) pages
ISBN: 9780819458322

Table of Contents
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Substrate noise coupling: a pain for mixed-signal systems
Author(s): Piet Wambacq; Geert Van der Plas; Stephane Donnay; Mustafa Badaroglu; Charlotte Soens
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New CAD issues and considerations for the design of mixed-signal SOCs
Author(s): William Kao; Susan Zhang
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A reuse-based framework for the design of analog and mixed-signal ICs
Author(s): Rafael Castro-Lopez; Francisco V. Fernandez; Angel Rodriguez Vazquez
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Area-, power-, and pin-efficient bus structures using multi-bit-differential signaling
Author(s): Donald M. Chiarulli; Jason D. Bakos; Joel R. Martin; Steven P. Levitan
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A continuous time low-pass sigma delta modulator implemented with transmission lines
Author(s): L. Hernandez; P. Rombouts; E. Prefasi; S. Paton; M. Garcia; C. Lopez
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A dual-mode complex delta-sigma ADC in CMOS for wireless-LAN receivers
Author(s): J. Arias; P. Kiss; V. Prodanov; V. Boccuzzi; M. Banu; D. Bisbal; J. San Pablo; L. Quintanilla; J. Barbolla
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Continuous-time cascaded sigma-delta modulators for VDSL: a comparative study
Author(s): Ramon Tortosa; Jose M. de la Rosa; Angel Rodriguez-Vazquez; Francisco V. Fernandez
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A 0.35-µm CMOS 17-bit@40-kS/s cascade 2-1 sigma-delta modulator with programmable gain and programmable chopper stabilization
Author(s): Oscar Guerra; Sara Escalera; Jose M. de la Rosa; Rocio del Rio; Fernando Medeiro; Angel Rodriguez-Vazquez
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Jitter effect comparison on continuous-time sigma-delta modulators with different feedback signal shapes
Author(s): J. San Pablo; D. Bisbal; L. Quintanilla; J. Arias; L. Enriquez; J. Vicente; J. Barbolla
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Optimization algorithm for linearity enhancement in the design of continuous-time sigma-delta modulators
Author(s): S. Paton; L. Hernandez; R. Frutos; A. Di Giandomenico; A. Wiesbauer
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Bounded budgeted parallel architecture versus control dominated architecture for hazard data-signal processor synthesis
Author(s): Bertrand Le Gal; Emmanuel Casseau; Eric Martin
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Data-driven array architectures: a rebirth?
Author(s): Joao M. P. Cardoso
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A novel gigabit multidrop serial link for high-speed digital systems
Author(s): F. Tobajas; R. Esper-Chain; R. Arteaga; O. Santana; V. de Armas; Roberto Sarmiento
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Linearisation for analogue optical links using integrated CMOS predistortion circuits
Author(s): Fu-Chuan Lin; David M. Holburn
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A 40-Gb/s driver circuit using a novel inductive bandwidth extension technique
Author(s): Daniel Kucharski; Kevin T. Kornegay
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A GmC filter design methodology for high-speed continuous-time sigma-delta A/D converters in a deep sub-micron technology
Author(s): Raf Schoofs; Michiel Steyaert; Willy Sansen
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A 0.18-µm CMOS low-noise highly linear continuous-time seventh-order elliptic low-pass filter
Author(s): Juan F. Fernandez-Bootello; Manuel Delgado-Restituto; Angel Rodriguez-Vazquez
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CMOS current amplifiers exhibiting independent AC and DC current amplification
Author(s): Drew Guckenberger; Kevin Kornegay
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An efficient 2-stage fractional charge pump based on frequency regulation
Author(s): A. Saiz-Vela; P. Miribel-Catala; M. Puig-Vidal; J. Samitier
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A quarter pixel precision motion estimation architecture for H.264/AVC video coding
Author(s): S. Lopez; F. Tobajas; A. Villar; J. Bienes; V. de Armas; G. M. Callico; J. F. Lopez; R. Sarmiento
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Statistically optimized VLSI architecture for buffer for EBCOT in JPEG2000 encoder
Author(s): Amit Kumar Gupta; Saeid Nooshabadi; Juan Montiel-Nelson
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Hardware implementation of the wavelet transform for JPEG2000
Author(s): J. Hormigo; J. M. Prades; J. Villalba; E. Zapata
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Haar wavelet processor for adaptive on-line image compression
Author(s): F. Javier Diaz; Angel M. Buron; Jose M. Solana
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Impact of package parasitics on crosstalk in mixed-signal ICs
Author(s): Giorgio Boselli; Vincenzo Ferragina; Nicola Ghittori; Valentino Liberali; Guido Torelli; Gabriella Trucco
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Net order optimization in analog net bundles
Author(s): Thomas Jambor; Lars Schreiner; Markus Olbrich; Erich Barke
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On the suitability and development of layout templates for analog layout reuse and layout-aware synthesis
Author(s): Rafael Castro-Lopez; Francisco V. Fernandez; Angel Rodriguez Vazquez
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A mismatch characterization and simulation environment for weak-to-strong inversion CMOS transistors
Author(s): J. Velarde-Ramirez; G. Vicente-Sanchez; T. Serrano-Gotarredona; B. Linares-Barranco
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Modeling of power control schemes in induction cooking devices
Author(s): Alessio Beato; Massimo Conti; Claudio Turchetti; Simone Orcioni
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Behavioral study and design of a digital interpolator filter for wireless reconfigurable transmitters
Author(s): V. Ferragina; A. Frassone; N. Ghittori; P. Malcovati; A. Vigna
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Modeling and design of high-order phase locked loops
Author(s): Brian Daniels; Gerard Baldwin; Ronan Farrell
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Voltage-buffer-based low-power area-efficient SC FIR filter for wireless communication
Author(s): Rafal Dlugosz; Ryszard Wojtyna
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Band-pass transimpedance read-out circuit for UHF MEMS resonator applications
Author(s): Humberto Campanella; Arantxa Uranga; Zachary Davis; Jaume Esteve; Lluis Teres; Nuria Barniol
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An integrated controller for a flexible and wireless atomic force microscopy
Author(s): Juanjo Lacort; Raimon Casanova; Jordi Brufau; Anna Arbat; Angel Dieguez; Marc Nierlich; Oliver Steinmetz; Manel Puig; Josep Samitier
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A CMOS latched driver using bootstrap technique for low-voltage applications
Author(s): Jose Carlos Garcia; Juan A. Montiel-Nelson; Saeid Nooshabadi
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Performance analysis of full adders in CMOS technologies
Author(s): Javier Castro; Pilar Parra; Antonio J. Acosta
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Temperature effects on circuit synchronism
Author(s): Sebastian A. Bota; Josep L. Rossello; Marcos Rosales; Jaume Segura
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Review of energy harvesting techniques and applications for microelectronics
Author(s): Loreto Mateu; Francesc Moll
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Ring oscillator behavior after oxide breakdown
Author(s): R. Fernandez; R. Rodriguez; M. Nafria; X. Aymerich
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Transient electro-thermal investigations of interconnect structures exposed to mechanical stress
Author(s): Stefan Holzer; Christian Hollauer; Hajdin Ceric; Stephan Wagner; Erasmus Langer; Tibor Grasser; Siegfried Selberherr
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A 2.5-V 4-mA GSM base-band transmit port with 2.8-mm2 area in CMOS 0.18 µm
Author(s): Emmanuel Marais; Roberto Rivoir
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A programmable baseband chain for a WCDMA/WLAN (802.11b) multi-standard zero-IF receiver
Author(s): Delia Rodriguez de Llera Gonzalez; Mohammed Ismail
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Low-power short-range transceivers for sensor network applications
Author(s): J. M. Lopez-Villegas
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CMOS implementation of ultra-wideband systems
Author(s): Wim Vereecken; Michiel Steyaert
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A 2-V 0.35-µm CMOS DECT RF front end with on-chip frequency synthesizer
Author(s): D. Guermandi; E. Franchi; A. Gnudi; P. Rossi; F. Svelto; R. Castello
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High bit rate BPSK receiver
Author(s): J. A. Osorio-Marti; J. J. Sieiro; J. M. Lopez-Villegas
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Power analysis methodology and library in SystemC
Author(s): L. Pieralisi; M. Caldari; G. B. Vece; M. Conti; S. Orcioni; C. Turchetti
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Energy estimation and optimization in architectural descriptions of complex embedded systems
Author(s): Ana Abril; Habib Mehrez; Frederic Petrot; Jean Gobert; Carolina Miro
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Algorithms to get the maximum operation frequency for skew-tolerant clocking schemes
Author(s): D. Guerrero; M. Bellido; J. Juan; A. Millan; P. Ruiz; E. Ostua; J. Viejo
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Embedded design-for-testability strategies to test high-resolution SD modulators
Author(s): Sara Escalera; Alvaro Espin; Oscar Guerra; Jose M. de la Rosa; Fernando Medeiro; Belen Perez-Verdu
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Digital test of a sigma-delta modulator in a mixed-signal BIST architecture
Author(s): Luis Rolindez; Salvador Mir; Guillaume Prenat
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Experimental comparison of different oscillation-based test techniques in an analog block
Author(s): Kay Suenaga; Rodrigo Picos; Sebastia Bota; Miquel Roca; Eugeni Garcia-Moreno
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Voltage to frequency converter for DAC test
Author(s): John Hogan; Ronan Farrell
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Design and modeling of an on-silicon spiral inductor library using improved EM simulations
Author(s): A. Goni-Iturri; S. L. Khemchandani; F. J. del Pino; J. Garcia; B. Gonzalez; A. Hernandez
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Modeling of passive components in VLSI technologies
Author(s): Javier Sieiro; Jose Maria Lopez-Villegas; Jose Cabanillas
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Design considerations for high pass frequency passive filters
Author(s): N. Sainz; I. Cendoya; U. Alvarado; H. Solar; J. de No
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Design considerations and tradeoffs for passive RFID tags
Author(s): Faisal A. Hussien; Didem Z. Turker; Rangakrishnan Srinivasan; Mohamed S. Mobarak; Fernando P. Cortes; Edgar Sanchez-Sinencio
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Integrated wireless systems: The future has arrived
Author(s): Roberto Rivoir
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Performance requirements for analog-to-digital converters in wideband reconfigurable radios
Author(s): David Naughton; Gerard Baldwin; Ronan Farrell
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A modular testbed for hardware reconfigurable radio at the 2.4 GHz ISM band
Author(s): Gerard Baldwin; Ronan Farrell
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Design and simulation of an embedded DRAM cell made up of MOSFETs having alternative gate dielectrics
Author(s): N. Konofaos; Th. Voilas; G. Ph. Alexiou
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A Dickson charge pump circuit driven by boosted clock for low-voltage flash memories
Author(s): Hyoung-Joo Kim; Gil-Su Kim; Soo-Won Kim
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Practical considerations for real-time super-resolution implementation techniques over video coding platforms
Author(s): Gustavo M. Callico; Sebastian Lopez; Rafael Peset Llopis; Ramanathan Sethuraman; Antonio Nunez; Jose Fco. Lopez; Margarita Marrero; Roberto Sarmiento
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Real-time super-resolution over raw video sequences
Author(s): D. Barreto; G. M. Callico; S. Lopez; L. Garcia; A. Nunez
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A low-cost bidimensional smart pixel network for video coding operations
Author(s): S. Lopez; G. M. Callico; J. F. Lopez; R. Sarmiento
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FPGA implementation of a fuzzy based video de-interlacing algorithm
Author(s): P. Brox; S. Sanchez-Solano; I. Baturone; A. Barriga
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Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK
Author(s): Jesus Ruiz-Amaya; Jose M. de la Rosa; Manuel Delgado-Restituto; Angel Rodriguez-Vazquez
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Geometrically constrained parasitic-aware synthesis of analog ICs
Author(s): Rafael Castro-Lopez; Francisco V. Fernandez; Angel Rodriguez Vazquez
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Simulation-based low-level optimization tool for analog integrated circuits
Author(s): Gines Domenech-Asensi; Jose Alejandro Lopez-Alcantud; Ramon Ruiz Merino
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Emitter degenerated voltage controlled oscillators for millimeter wave operation
Author(s): Brian Welch; Kevin Kornegay
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A 3.2-GHz fully integrated low-phase noise CMOS VCO with self-biasing current source for the IEEE 802.11a/hiperLAN WLAN standard
Author(s): C. Quemada; I. Adin; G. Bistue; R. Berenguer; J. Mendizabal
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NMOS symmetric load ring VCOs modeling for submicron technologies
Author(s): M. Helena Fino
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An 18-GHz integrated double-balanced direct down-conversion mixer and emitter degenerated quadrature VCO in 47-GHz ft SiGe
Author(s): Yanxin Wang; Brian P. Welch; Kevin T. Kornegay
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A functional validation methodology based on error models for measuring the quality of digital integrated circuits
Author(s): Celia Lopez-Ongil; Luis Entrena-Arrontes; Teresa Riesgo-Alcaide; Javier Uceda-Antolin
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Built-in test engine and fault simulation for memory
Author(s): P. McEvoy; R. Farrell
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A one-step algorithm for finding the optimum solution of the state justification problem in RTL designs using MILP
Author(s): Hector Navarro; Juan A. Montiel-Nelson; Javier Sosa; Jose C. Garcia
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A complete hardening method for the generation of fault tolerant circuits
Author(s): Marta Portela-Garcia; Mario Garcia-Valderas; Celia Lopez-Ongil; Luis Entrena
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Parallel-pipeline 2-D DCT/IDCT processor chip
Author(s): G. A. Ruiz; J. A. Michell; A. Buron
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Evaluation of architectures for an ASP MPEG-4 decoder using a system-level design methodology
Author(s): Luz Garcia; Victor Reyes; Dacil Barreto; Gustavo Marrero; Tomas Bautista; Antonio Nunez
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System level design and power analysis of architectures for SATD calculus in the H.264/AVC
Author(s): Conti Massimo; Francesco Coppari; Simone Orcioni; Giovanni B. Vece
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Design of a 12-bit 80MS/s pipeline analog-to-digital converter for PLC-VDSL applications
Author(s): Jesus Ruiz-Amaya; Manuel Delgado-Restituto; Juan F. Fernandez-Bootello; Jose M. de la Rosa
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A high linearity 14-bit pipelined charge summation ADC
Author(s): Nigel Duignan; Ronan Farrell
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A simple 3.8-mW 300-MHz 4-bit flash analog-to-digital converter
Author(s): Laurent de Lamarre; Marie-Minerve Louerat; Andreas Kaiser
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Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications
Author(s): Jesus Ruiz-Amaya; Manuel Delgado-Restituto; J. Francisco Fernandez-Bootello; Jose M. de la Rosa
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10-bit 100-MS/s sample-and-hold amplifier adopting positive feedback technique
Author(s): Gil-Su Kim; Jae-Tack Yoo; Hoon-Jae Ki; Soo-Won Kim
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FPGA implementation of sparse matrix algorithm for information retrieval
Author(s): Slobodan Bojanic; Ruzica Jevtic; Octavio Nieto-Taladriz
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Integrated circuit debug through FPGA emulation: application to a PIC-18 macrocell
Author(s): Mario Garcia-Valderas; Eduardo de la Torre-Arnanz; Fernando Casado-Ortiz; Luis Entrena-Arrontes; Teresa Riesgo-Alcaide
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ACE16k based stand-alone system for real-time pre-processing tasks
Author(s): Luis Carranza; Francisco Jimenez-Garrido; Gustavo Linan-Cembrano; Elisenda Roca; Servando Espejo Meana; Angel Rodriguez-Vazquez
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Self-similar module for FP/LNS arithmetic in high-performance FPGA systems
Author(s): Lambert Spaanenburg; Stefan Mohl
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VLSI implementation of RSA encryption system using ancient Indian Vedic mathematics
Author(s): Himanshu Thapliyal; M. B. Srinivas
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CHIADO: compilation of high-level computationally intensive algorithms to dynamically reconfigurable computing systems
Author(s): Joao M. P. Cardoso
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A methodology for the characterization of arithmetic circuits on CMOS deep submicron technologies
Author(s): Adrian Estrada; Carlos J. Jimenez; Manuel Valencia
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An efficient structural technique for Boolean decomposition
Author(s): Andres Martinelli; Elena Dubrova
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Technology mapping in library-free logic synthesis
Author(s): Jingyue Xue; Dhamin Al-Khalili; Come N. Rozon
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Computing a perfect input assignment for probabilistic verification
Author(s): Maxim Teslenko; Elena Dubrova; Hannu Tenhunen
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A new geometrical approach to design centering of analog circuits
Author(s): Francesco Grasso; Stefano Manetti; Maria Cristina Piccirilli
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CMOS integrator based lock-in pixel for heterodyne interferometry
Author(s): Oleg Soloviev; Gleb Vdovin
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Single poly PMOS-based CMOS-compatible low voltage OTP
Author(s): Paola Vega-Castillo; Wolfgang H. Krautschneider
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Modeling of frequency agile devices: development of PKI neuromodeling library based on hierarchical network structure
Author(s): P. Sanchez; J. Hinojosa; R. Ruiz
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A temperature control system for integrated resistive gas sensor arrays
Author(s): Giuseppe Ferri; Nicola Guerrini; Vincenzo Stornelli
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CCII-based inductance simulators for mechanical oscillation control
Author(s): Giuseppe Ferri; Nicola Guerrini
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Novel low-voltage fully differential buffer
Author(s): Giuseppe Ferri; Nicola Guerrini; Manolo Sperini
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Application of clock gating techniques at a flip-flop level to switching noise reduction in VLSI circuits
Author(s): Pilar Parra; Javier Castro; Manuel Valencia; Antonio J. Acosta
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DC modeling of PN integrated cross varactors
Author(s): Benito Gonzalez; Jose Antonio Perez; Sunil L. Kemchandani; Amaya Goni-Iturri; Javier del Pino; Javier Garcia
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Sectored receiver model for calculation of the impulse response on IR wireless indoor channels using Monte Carlo based ray-tracing algorithm
Author(s): B. R. Mendoza; S. Rodriguez; R. Perez-Jimenez; O. Gonzalez; A. Ayala
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Study of the proximity effect in high q inductors for wireless LAN (WLAN)
Author(s): I. Cendoya; J. Mendizabal; N. Sainz; I. Gutierrez; U. Alvarado; J. de No
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Prototype board for the test of self-timed circuits developed in FPGAs
Author(s): M. Sanchez Raya; R. Jimenez Naharro; J. Castro Ramirez
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An approach to a VHDL-AMS library for RF component models
Author(s): Jose-Alejandro Lopez-Alcantud; Gines Domenech Asensi; Juan Hinojosa Jimenez; Juan Martinez-Alajarin; Francisco Javier Garrigos-Guerrero
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Multiphase clock generators with controlled clock impulse width for programmable high order rotator SC FIR filters realized in 0.35 µm CMOS technology
Author(s): Rafal Dlugosz; Pawel Pawlowski; Adam Dabrowski
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A fully integrated low-noise amplifier in SiGe 0.35 µm technology for 802.11a WIFI applications
Author(s): R. Pulido; S. L. Khemchandani; A. Goni-Iturri; R. Diaz; A. Hernandez; J. del Pino
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Search strategy for relevant parasitic elements and reduction of their influence on the operation of SC FIR filters realized in CMOS technology
Author(s): Rafal Dlugosz
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A deterministic BIST scheme for test time reduction in VLSI circuits
Author(s): Jose M. Solana
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Low-cost printed antenna design in the band of 2.4 GHz
Author(s): Pere Marti; Moises Serra; Jordi Carrabina
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Rapid prototyping with the visual data environment of an OFDM WLAN system
Author(s): Moises Serra; Pere Marti; Jordi Carrabina
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Evaluation of a MEMS based theft detection circuit for RFID labels
Author(s): Damith C. Ranasinghe; Peter H. Cole
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Turn-on circuits based on standard CMOS technology for active RFID labels
Author(s): David Hall; Damith C. Ranasinghe; Behnam Jamali; Peter H. Cole
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