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Proceedings of SPIE Volume 5117

VLSI Circuits and Systems
Editor(s): Jose Fco. Lopez; Juan A. Montiel-Nelson; Dimitris Pavlidis
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Volume Details

Volume Number: 5117
Date Published: 21 April 2003
Softcover: 63 papers (636) pages
ISBN: 9780819449771

Table of Contents
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VLSI architecture for MPEG-4 core profile video codec with accelerated bitstream processing
Author(s): Walter Stechele
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FPGA implementation of Santos-Victor optical flow algorithm for real-time image processing: an useful attempt
Author(s): Pedro Cobos Arribas; Felix Monasterio Huelin Macia
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Integer cosine transform chip design for image compression
Author(s): Gustavo A. Ruiz; Juan A. Michell; Angel M. Buron; Jose M. Solana; Miguel A. Manzano; J. Diaz
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Mapping of real-time and low-cost super-resolution algorithms onto a hybrid video encoder
Author(s): Gustavo Marrero Callico; Rafael Peset Llopis; Antonio Nunez; Ramanathan Sethuraman
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State of the art in CMOS threshold logic VLSI gateimplementations and applications
Author(s): Peter Celinski; Sorin D. Cotofana; Jose Fco. Lopez; Said F. Al-Sarawi; Derek Abbott
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New efficient offset voltage cancellation techniques using digital trimming
Author(s): Said F. Al-Sarawi
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Novel 1.25-Gb/s CMOS burst mode optical receiver with automatic gain controllable preamplifier and a highly sensitive peak detector without external reset signal
Author(s): Ja-Won Seo; Seop Han; Quan Le; Sang-Gug Lee; Man-Seop Lee; Tae-Whan Yoo
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Scheduling components for multigigabit network SoCs
Author(s): Theofanis Orphanoudakis; George Kornaros; Ioannis Papaefstathiou; Helen-Catherine Leligou; Stylianos Perissakis; Nicholas Zervos
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CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using a low-voltage power line
Author(s): Sara Escalera; Carlos Manuel Dominguez-Matas; Jose Manuel Garcia-Gonzalez; Oscar Guerra; Angel Rodriguez-Vazquez
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High-speed clock recovery unit based on a phase aligner
Author(s): Efrain Tejera; Roberto Esper-Chain; Felix Tobajas; Valentin De Armas; Roberto Sarmiento
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Practical high-level methodology case study: implementation of an ATM over SDH transceiver from the system specification
Author(s): Ruben Arteaga; Felix Tobajas; Roberto Esper-Chain; Valentin De Armas; Roberto Sarmiento
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High-bandwidth low-latency global interconnect
Author(s): Christer M Svensson; Peter Caputa
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Leakage control for deep-submicron circuits
Author(s): Kaushik Roy; Hamid Mahmoodi-Meimand; Saibal Mukhopadhyay
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Scaling down photonic waveguide devices on the SOI platform
Author(s): Pavel Cheben; Dan-Xia Xu; Siegfried Janz; Andre Delage
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Theoretical analysis on characteristics and efficiency of CdS/CdTe heterojunction solar cell
Author(s): Jiang Guo; Chunyang Kong; Wanlu Wang
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Signaling in the heterogeneous architecture multiprocessor paradigm
Author(s): Antonio Nunez; Victor Reyes; Tomas Bautista
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High-performance VLSI architecture for video processing
Author(s): Hector Navarro; Juan A. Montiel-Nelson; Javier Sosa; Jose C. Garcia; Roberto Sarmiento; Saeid Nooshabadi
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System-level verification methodology for advanced switch fabrics
Author(s): Javier Sosa; Juan A. Montiel-Nelson; Hector Navarro; Mahendra V. Shahdadpuri; Roberto Sarmiento
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Models and algorithm for the calculation of the impulse response on IR-wireless indoor channels
Author(s): Silvestre Rodriguez; Rafael Perez-Jimenez; Francisco J. Lopez-Hernandez; Oswaldo B. Gonzalez; Beatriz R. Mendoza
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VESTA: a system-level verification environment based on C++
Author(s): Mahendra V. Shahdadpuri; Javier Sosa; Héctor Navarro; Juan A. Montiel-Nelson; Roberto Sarmiento
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MHDL CAD tool with fault circuit handling
Author(s): Guillermo Espinosa Flores-Verdad; Leopoldo Altamirano Robles; Leticia Osorio Roque
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Switch-based interconnect architecture for future systems on chip
Author(s): Partha Pratim Pande; Cristian S Grecu; Andre Ivanov; Resve A Saleh
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CMOS receiver circuits for high-speed data transmission according to LVDS standard
Author(s): Stefan Hirsch; Hans-Jorg Pfleiderer
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System-level optimization of baseband filters for communication applications
Author(s): Manuel Delgado-Restituto; Juan F. Fernandez-Bootello; Angel Rodriguez-Vazquez
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Analog filter circuits testing using voltage and current measurements
Author(s): Mahmoud A Al-Qutayri
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Iterative current mode per pixel ADC for 3D SoftChip implementation in CMOS
Author(s): Stefan W. Lachowicz; Alexander Rassau; Seung-Minh Lee; Kamran Eshraghian; Mike Myung-Ok Lee
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Novel low-voltage low-power Gb/s transimpedance amplifier architecture
Author(s): Drew Guckenberger; Kevin Kornegay
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Sigma-delta modulator for a programmable gain low-power high-linearity automotive sensor interface
Author(s): Jose M. de la Rosa; Fernando Medeiro; Belen Perez-Verdu; Rocio del Rio; Angel Rodriguez-Vazquez
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LP-LV high-performance monolithic DTMF receiver with on-chip test facilities
Author(s): Diego Vazquez; Gloria Huertas; Maria José Avedillo; Jose María Quintana; Adoracion Rueda; Jose Luis Huertas
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Flexible coprocessor architectures for ambient intelligent applications in the mobile communication and automotive domain
Author(s): Winfried Gehrke; Joern Jachalsky; Martin Wahle; Wido Kruijtzer; Carlos Alba; Ramanathan Sethuraman
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Lifting folded pipelined discrete wavelet packet transform architecture
Author(s): Guillermo Paya; Marcos M. Peiro; J. Francisco Ballester; Vicente Herrero; Francisco Mora
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Turbo decoder core design for system development
Author(s): Xiaoyi Chen; Qingdong Yao; Peng Liu
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Some experiences using system-on-chip buses
Author(s): Pedro P Carballo; Pablo Santos; Margarita Marrero; Antonio Nunez
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Performance optimization of an MPEG-2 to MPEG-4 video transcoder
Author(s): Hari Kalva; Anthony Vetro; Huifang Sun
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New lifting folded pipelined discrete wavelet transform architecture
Author(s): Guillermo Paya; Marcos M. Peiro; J. Francisco Ballester; Vicente Herrero; Ricardo Colom
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0.25-µm technology arithmetic codec for mobile multimedia communicators
Author(s): Alberto Alvarez; Sebastian Lopez; Jose Fco. Lopez; Roberto Sarmiento
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New distributed arithmetic discrete wavelet packet transform architecture
Author(s): Guillermo Paya; Marcos M. Peiro; J. Francisco Ballester; Rafael Gadea; Ricardo Colom
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Mixed-signal early vision chip with embedded-image and programming memories and digital I/O
Author(s): Gustavo Linan-Cembrano; Angel Rodriguez-Vazquez; Rafael Dominguez-Castro; Servando Espejo
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Approaching nanoscale integration
Author(s): Dieter Draxelmayr
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Holographic study of microsystems during space missions in the 21st century
Author(s): Valery D. Petrov
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Evaluation of package and technology effects on substrate-crosstalk isolation in CMOS RFIC
Author(s): Xavier Aragones; Diego Mateo; Olga Boric-Lubecke
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Low-cost VLSI-compatible resonant-cavity-enhanced p-i-n in micron-Si operating at the VCSEL wavelengths around 850 nm
Author(s): Luca De Stefano; Luigi Moretti; Ivo Rendina; Caterina Summonte
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Macromodel for exact computation of propagation delay time in GaAs and CMOS technologies
Author(s): Jose C. Garcia; Juan A. Montiel-Nelson; Javier Sosa; Hector Navarro; Roberto Sarmiento
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Simulation of void formation in interconnect lines
Author(s): Alireza Sheikholeslami; Clemens Heitzinger; Helmut Puchner; Fuad Badrieh; Siegfried Selberherr
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Timing and power model for CMOS inverters
Author(s): Richard Geibler; Hans-Jorg Pfleiderer
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Empirical model of the metal losses in integrated inductors
Author(s): F. Javier del Pino; Javier Garcia; Benito Gonzalez; Jose Ramón Sendra; Antonio Hernandez; Andres Garcia-Alonso; Antonio Nunez
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On-chip training for cellular neural networks using iterative annealing
Author(s): Dirk Feiden; Ronald Tetzlaff
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Optimal design of a leak-proof SRAM cell using MCDM method
Author(s): Qi Wang; Sung-Mo Kang
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Evolutionary design and FPGA implementation of digital filters
Author(s): Antonia Azzini; Matteo Bettoni; Valentino Liberali; Roberto Rossi; Andrea Tettamanzi
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Hierarchical test pattern composition to testing a foveal imager ASIC
Author(s): Martin Gonzalez; Jose R. Salinas; Francisco J. Coslado; Pelegrin Camacho; Francisco Sandoval
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Experimental characterization of a synchronous frequency-hopping spread-spectrum transceiver for wireless optical communications
Author(s): Santiago T Perez Suarez; Jose Alberto Rabadan; Francisco Alberto Delgado; Jose Ramon Velazquez; Rafael Perez Jimenez
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Analysis of current-mode flip-flops in CMOS technologies
Author(s): Raul Jimenez; Pilar Parra; Pedro M Sanmartin; Antonio J. Acosta
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Temperature in HFETs when operating in DC
Author(s): Benito Gonzalez; Antonio Hernandez; Javier Garcia; F. Javier del Pino; Antonio Nunez; Jose Ramón Sendra
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Laser-induced structure defects and their use for modification of the properties of (Cd,Hg)Te epitaxial layers and CdTe crystals
Author(s): Bohdan K. Kotlyarchuk; Apollinariy O. Zaginey; Yuriy E. Syvenkyy
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Design and simulation of an a-Si:H/GaAs HBT with improved DC and high-frequency characteristics
Author(s): Fortunato Pezzimenti; Francesco G. Della Corte
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Diffusion barrier layer fabrication by plasma immersion ion implantation
Author(s): Mukesh Kumar; - Rajkumar; Dinesh Kumar; P. J. George; A. K. Paul
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Switching-noise reduction in clock distribution in mixed-mode VLSI circuits
Author(s): Pilar Parra; Antonio J. Acosta; Manuel Valencia
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Integrated optical scheme for residue-based logic operations
Author(s): Partha Ghosh
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Digital optical switch based on amorphous silicon waveguide
Author(s): Luigi Sirleto; Mario Iodice; Francesco G. Della Corte; Ivo Rendina
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1.55-µm reflection-type optical waveguide switch based on thermo-optic effect
Author(s): Francesca LB Cantore; Francesco G. Della Corte
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Comparison of CMOS and BiCMOS optical receiver SoCs
Author(s): Horst Zimmermann; Robert Swoboda; Kerstin Schneider; Johannes Knorr
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Method of generating trustworthy performance estimations for soft IPs
Author(s): Margarita Marrero; Pedro P. Carballo; Antonio Nunez
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IC technology trends for wireless local area networks
Author(s): Neil Weste
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