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Proceedings of SPIE Volume 5042

Design and Process Integration for Microelectronic Manufacturing
Editor(s): Alexander Starikov
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Volume Details

Volume Number: 5042
Date Published: 10 July 2003
Softcover: 35 papers (416) pages
ISBN: 9780819448477

Table of Contents
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Layout optimization at the pinnacle of optical lithography
Author(s): Lars W. Liebmann; Greg A. Northrop; James Culp; Leon Sigal; Arnold Barish; Carlos A. Fonseca
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Dense only phase-shift template lithography
Author(s): Michael Fritze; Brian Tyrrell; Renee D. Mallen; Bruce Wheeler; Peter D. Rhyins; Patrick M. Martin
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Assessing technology options for 65-nm logic circuits
Author(s): Dipankar Pramanik; Michel L. Cote; Kevin Beaudette; Valery Axelrad
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Generalization of the photo process window and its application to OPC test pattern design
Author(s): Hans Eisenmann; Kai Peter; Andrzej J. Strojwas
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Technology CAD for integrated circuit fabrication technology development and technology transfer
Author(s): Samar Saha
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Performance-impact limited-area fill synthesis
Author(s): Yu Chen; Puneet Gupta; Andrew B. Kahng
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Simulation-based data processing using repeated pattern identification
Author(s): Youping Zhang
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Model-assisted placement of subresolution assist features: experimental results
Author(s): Travis E. Brist; Juan Andres Torres
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OPC on real-world circuitry
Author(s): Sean C. O'Brien; Tom Aton; Mark E. Mason; Carl Vickery; John N. Randall
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Characterization and modeling of intradie variation and its applications to design for manufacturability
Author(s): Sharad Saxena; Carlo Guardiani; Michele Quarantelli; Nicola Dragone; Sean Minehane; Patrick McNamara; Jeff A. Babcock
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Lithography-driven layout of logic cells for 65-nm node
Author(s): Dipankar Pramanik; Michel L. Cote
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Improved manufacturability by OPC based on defocus data
Author(s): Jorg Thiele; Ines Anke; Henning Haffner; Armin Semmler
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LithoScope: an advanced physical modeling system for mask data verification
Author(s): Qi-De Qian
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Investigation of product design weaknesses using model-based OPC sensitivity analysis
Author(s): Sergei V. Postnikov; Kevin Lucas; Cesar M. Garza; Karl Wimmer; Patrick LaCour; James C. Word
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Device characteristics of sub-20-nm silicon nanotransistors
Author(s): Samar Saha
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NBTI improvement for pMOS by Cl-contained 1st oxidation in 20A/65A dual-nitrided gate oxide of 0.13-um CMOS technology
Author(s): Ching-Chen Hao; Min-Hwa Chi; Chao-Chi Chen; Hung-Jen Lin; Yu-Fang Lin; C. H. Hsieh; Chih-Hsiung Lee; Kuang-Hui Chang; H. T. Wu; Chin-Heng Shen
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Library-based process test vehicle design framework
Author(s): Kelvin Yih-Yuh Doong; L.-J. Hung; Susan Ho; S. C. Lin; K. L. Young
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Design-to-process integration: optimizing 130-nm X architecture manufacturing
Author(s): Robert Dean; Vinod K. Malhotra; Nahid King; Michael Sanie; Susan S. MacDonald; James D. Jordan; Shigeru Hirukawa
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Using the CODE technique to print complex two-dimensional structures in a 90-nm ground rule process
Author(s): Serdar Manakli; Yorick Trouiller; Olivier Toublan; Patrick Schiavone; Yves Fabien Rody; Pierre Jerome Goirand
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New stream format: progress report on containing data size explosion
Author(s): Patrick LaCour; Alfred J. Reich; Kent H. Nakagawa; Steffen F. Schulze; Laurence Grodd
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Optimization of the data preparation for variable-shaped beam mask writing machines
Author(s): Steffen F. Schulze; Patrick LaCour
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Compression algorithms for dummy-fill VLSI layout data
Author(s): Robert B. Ellis; Andrew B. Kahng; Yuhong Zheng
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Precision control of poly-gate CD by local OPC for elimination of microloading effect on 0.13-um CMOS technology
Author(s): Tzy-Kuang Lee; Yao-Ching Wang; Min-hwa Chi; C. Y. Lu; C. H. Hsieh; R. G. Liu; H. J. Liao; S. S. Yang; Chih-Hao Chang
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Creation and verification of phase-compliant SoC IP for the fabless COT designers
Author(s): Vinod K. Malhotra; Nahid King; Raymond Leung; Zain Zia; Shakeel Jeeawoody
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Statistical data assessment for optimization of the data preparation and manufacturing
Author(s): Steffen F. Schulze; Patrick LaCour
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Lithographic tradeoffs between different assist feature OPC design strategies
Author(s): James C. Word; Siuhua Zhu
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Resolution enhancement technology requirements for 65-nm node
Author(s): Armen Kroyan; Hua-Yu Liu
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PsmLint: bringing AltPSM benefits to the IC design stage
Author(s): Pradiptya Ghosh; Chung-Shin Kang; Michael Sanie; Judy A. Huckabay
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Optimizing manufacturability for the 65-nm process node
Author(s): Dipankar Pramanik; Michel L. Cote
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Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs
Author(s): Robert C. Pack; Valery Axelrad; Andrei Shibkov; Victor V. Boksha; Judy A. Huckabay; Rachid Salik; Wolfgang Staud; Ruoping Wang; Warren D. Grobman
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Optimized cobalt silicide formation through etch process improvements
Author(s): David S. Tucker; Richard Yang; Heather Maines
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Effective multicutline QUASAR illumination optimization for SRAM and logic
Author(s): Travis E. Brist; George E. Bailey
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Modification of existing chip layout for yield and reliability improvement by computer-aided design tools
Author(s): Mu-Jing Li; Suryanarayana Maturi; Pankaj Dixit
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Applications of image diagnostics to metrology quality assurance and process control
Author(s): John A. Allgair; Victor V. Boksha; Benjamin D. Bunday; Alain C. Diebold; Daniel C. Cole; Mark P. Davidson; Jerry Dan Hutcheson; Andrew W. Gurnell; David C. Joy; John M. McIntosh; Sylvain G. Muckenhirn; Joseph C. Pellegrini; Robert D. Larrabee; James E. Potzick; Andras E. Vladar; Nigel P. Smith; Alexander Starikov; Neal T. Sullivan; Oliver C. Wells
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OPC methods to improve image slope and process window
Author(s): Nicolas B. Cobb; Yuri Granik
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